EP0862841A1

EP0862841A1 - Updating a card unit in an electronic apparatus

Info

Publication number: EP0862841A1
Application number: EP96938260A
Authority: EP
Inventors: Hannu Esala; Esko Rautanen
Original assignee: Nokia Telecommunications Oy
Current assignee: Nokia Oyj
Priority date: 1995-11-24
Filing date: 1996-11-22
Publication date: 1998-09-09
Also published as: AU7575496A; FI955674A0; CN1203010A; FI955674A; FI100156B; WO1997020448A1

Abstract

The invention relates to updating properties of a card unit (SUBn) in an electronic apparatus, especially a telecommunication apparatus, with new properties. In order for the updating to be performed flexibly without a need to anticipate future properties during the manufacture of the card unit, the new properties are formed on a separate additional card (AB) that is attached in parallel with the card unit (SUBn) and functionally connected to the card unit by allocating data corresponding to the new properties in available time slots of a time-division bus (BUS2) formed on the card unit.

Description

Updating a card unit in an electronic apparatus

The invention relates to a method according to the preamble of appended claim 1 and to an arrangement according to the preamble of appended claim 5 for updating a card unit in an electronic apparatus, especially a telecommunication apparatus.

As is well known, a telecommunication apparatus comprises several card units that are placed in parallel in card locations situated in the framework of the apparatus. The card units comprise connectors required for connecting external devices to the telecommunication apparatus and for connecting the telecommunication apparatus to the telecommunication network. When recommendations of international standardization organizations change or when they define completely new properties for apparatuses or systems, or when a need occurs for some other reason to provide an existing apparatus with new properties, these changes must be carried out on an apparatus by updating the card units of the apparatus with corresponding properties. In this connection updating refers generally to changes in properties of a card unit, such as providing the unit with new properties or replacing old properties with new properties.

Updatmgs are presently carried out typically m such a way that the entire card unit is replaced w th a new card unit provided with new properties. Such a change of the entire card unit is an economically unsatisfactory solution since the existing card units cannot be utilized efficiently, but they can only be used occasionally after the change for example as spare components m maintenance or for instructional purposes.

An alternative manner of performing an updating s to modify the existing card unit in such a way that the use of the unit can be continued in the same apparatus after the modification. However, in practice such a modification of existing card units into a card unit having new properties is very difficult and often even impossible. Especially in cases where it has not been possible to anticipate the new functions during the manufacture of the card unit, the change of the entire unit is almost the only alternative in practice.

The object of the present invention is to eliminate the above-described drawback by providing a new type of method for performing updatmgs . This object is achieved with a method according to the invention that is characterized by what is described in the characterizing part of appended claim 1. The arrangement according to the invention is in turn characterized by what is described n the characterizing part of appended claim 5.

The idea of the invention is to provide new properties on an additional card that is attached to the existing card unit of the apparatus and functionally connected to the card unit by allocating data corresponding to the new properties to the available time slots of the time-division bus formed on the card unit.

The arrangement according to the invention provides flexible updating properties without wasting the existing equipment. An especially important further advantage is that the arrangement also makes t possible to flexibly add such properties that cannot be anticipated at all during the manufacture of the card unit. The arrangement only requires that the existing card unit comprises suitable interfaces and a time-division bus with available capacity (available time slots) .

In the following, the invention and the preferred embodiments thereof will be described in greater detail with reference to the examples according to the accompanying drawings, in which Figure 1 illustrates, on the network level, a possible apparatus environment where the updating according to the invention is carried out,

Figure 2 shows schematically a card unit to be used m the environment of Figure 1 and forming the base card used in the solution according to the invention,

Figure 3 illustrates an example of functions that can be carried out with a base card,

Figure 4 illustrates the updating of the base card of Figure 3 by means of an additional card, and

Figures 5a to 5c illustrate the frame structure of a bus on the base card and the use thereof in updating.

Figure 1 shows, on the network level, a possible environment where the method according to the invention can be applied. The example shown in the figure relates to a point-to-point connection formed by means of two multiplexer units DM1 and DM2. The connection may be for example a 32-channel PCM connection according to the ITU-T

(former CCITT) recommendation G.704, having a data rate of 2048 kbit/s. The multiplexer units comprise, in a manner known per se, subscriber interface cards SUB1 to SUBn to which subscriber equipments, such as phones SD1 and SD2, are connected. There may be several types of subscriber interface cards depending on the different kinds of subscriber equipments used, and one or several subscriber equipments may be connected to one interface card. In addition to a conventional subscriber interface card SUB1,

Figure 1 also shows a subscriber interface card SUBn that can be used to set up both an audio link of high quality and a data link. The audio link s formed m this example between a microphone MP and a loudspeaker LD, and the data link is formed between computers TE1 and TE2.

The subscriber interface cards are connected via their back connector to an internal bus of the multiplexer units, denoted by IB. Since the data link shown in Figure 1 is realized with technology known per se and it is not related to the actual inventive idea, it will not be described in greater detail in this connection.

Figure 2 illustrates the (mechanical) structure of the individual subscriber interface card of Figure 1, as regards updatmgs, by showing the card unit in side view.

A subscriber interface card may comprise one or several front connectors and one or several back connectors. In this example, there are two front connectors, FC1 and FC2, and one back connector, BC1. These connectors are preferably connectors according to some standard, for example Euroconnectors . The new properties are formed according to the invention on a separate additional card, and two pin strips are formed on the subscriber interface card for each additional card. One card unit may therefore comprise a reserved location for one or more additional cards. In the example of the figure there are two locations. Pin strips formed for the first additional card are denoted by NRl and NR2 and pin strips formed for the second additional card are denoted by NR3 and NR4. The additional card is coupled with its own connectors to these connectors that are already provided on the card unit. Some of the pins of the front connector, in this case the pins of the second and third quarters in the connector (the quarters are separated from one another with broken lines) , are connected directly to the corresponding pin strip (NRl or NR3) . This is illustrated by arrows C. The pins of the pin strips NR2 and NR4 are in turn connected to the subscriber interface card. In the figure, each additional card is illustrated by a broken line denoted by AB. The additional card is thus placed "on" the subscriber interface card, and the signals propagate via the aforementioned pins of the front connectors and the pins of the pin strip NRl (or NR3) to the additional card and from there via the pins of the pin strip NR2 (or NR4, respectively) to the subscriber interface card. Since the subscriber interface card forms the existing card on which (or parallel to which) an additional card is placed, if required, the subscriber interface card will also be called hereinafter a base card.

Figure 3 illustrates schematically functions provided on a base card. The figure shows as an example a subscriber interface card SUBn via which both an audio link and a data link are formed. Audio interfaces are denoted by references AUDI01 and AUDI02 and data interfaces by references DATA1 and DATA2. For the sake of clarity and simplicity, pin strips provided on the base card are not shown.

The pins of the audio links are connected to a converter unit 31 comprising A/D and D/A converters and connected in turn via an internal bus BUSO formed on the base card to a cross-connection circuit XC which carries out the cross connection between incoming and outgoing time slots. (The cross-connection circuit may be a programmable logic circuit, such as an XC 3090, manufactured by Xilinx, USA, or AT&T, USA) . The base card also comprises two digital signal processors DSP1 and DSP2 each of which is provided for a separate audio interface. From the cross- connection circuit there are two bidirectional serial mode time-division buses of 2048 kbit/s, BUS1 and BUS2, and each signal processor is connected to its own bus: DSP1 to BUS1 and DSP2 to BUS2. Each signal processor has certain time slots in the frame structure of the bus and it operates in those slots. The cross-connection circuit is connected via the back connector of the base card BC1 to the internal bus of the multiplexer unit IB and from there to a PCM connection between the multiplexer units. (Several base cards are connected to the internal bus IB.) An analog audio signal received for example from the microphone MP to the audio interface is subjected m the unit 31 to an A/D conversion, whereafter the signal propagates in a digital form and in serial mode via the fast bus BUSO to the cross-connection circuit XC from where it is further connected to the signal processor. Only digital samples therefore pass through the cross-connection circuit, the samples having the length of for example 16 bits. The signal processor subjects the samples to coding which may be for example SBADPCM coding according to the ITU-T recommendations G.725 and H.221, by means of which coding the encoded audio signal is transmitted in a channel of 64 kbit/s (i.e. in one time slot of the basic channeling system of 2048 kbit/s) . Altogether six samples are taken m this case from the analog signal in the unit 31 for one frame of 125 μs in the basic channeling system, so that the signal processor receives six samples having the width of 16 bits during each frame of the signal of 2048 kbit/s. The signal processor packs these samples into one time slot of the frame of the bus (BUS1 or BUS2), the time slot being connected back to the cross-connection circuit and from there to the internal bus of the multiplexer unit IB.

In the other transmission direction, the data of the desired time slots is received to the cross-connection circuit XC which connects the time slots further to the signal processor which decodes the data of the time slot into six separate samples. These samples are applied at even intervals via the cross-connection circuit to the D/A converter of the unit 31 from where the analog signal is connected further via the audio interface.

The data interfaces DATA1 and DATA2 of the subscriber interface card (base card) form in this example a known V.28/V.24 interface which corresponds to a conventional RS232 serial interface. On the subscriber interface card, the outgoing and incoming signals are subjected to a level conversion in conversion circuits 32 wherein the incoming V.28-adapted signals are converted into TTL-level signals (+5V) and the outbound TTL-level signals are converted into V.28-adapted signals. The conversion circuits are connected to a packing circuit 33 which subjects the incoming signals to packing according to the recommendation V.110 and the outbound signals to unpacking. V.110 is an ITU-T recommendation which indicates how different terminal equipment rates are adapted to the frame structure of a signal of 2048 kbit/s (i.e. the bus BUS2) . For example the terminal equipment rate of 9600 bit/s is adapted according to the V.110 recommendation to the frame structure of the signal of 2048 kbit/s by taking two bits for use from one time slot of the frame. The bits are connected forward via the cross-connection circuit XC. In this manner, a bidirectional data link is formed between the computers 15 and 16 via the subscriber interface card SUBn.

Figure 3 also shows a processor 34 which controls all the functions of the base card (i.e. in this example the signal processors, the circuit 33 and the cross connection) . In practice, such a control processor may be for example a 68302, manufactured by Motorola, USA.

Since the V.28/V.24 interface on the subscriber interface card supports bit rates between 0 and 56 kbit/s, there may easily occur a need to form on the card a new and faster data interface which is for example in accordance with the recommendation V.ll. Such a need may occur for example when the user wants to replace a conventional microcomputer with a work station comprising a V.ll interface. (The V.ll supports rates of hundreds of kilobits per second, and it also reaches clearly greater distances than a V.28/V.24 interface.)

The updating is carried out by connecting to the pin strips of the base card (only the pm strip NR3 is shown in the figure) an additional card AB in the manner shown m Figure 4, the additional card being provided with new properties. In the example of Figure 4, two V.ll interfaces, DATA3 and DATA4, are supplied to the two middle quarters of the front connector FC2. The previous interfaces, DATA1 and DATA2, remain the same and their signals pass from the pins of the first and fourth quarters of the front connector FC2 on the base card to the conversion units 32 and further to the circuit 33 (that is left under the additional card on the base card) . The pins of the two middle quarters of the front connector FC2 are connected on the base card directly to the pin strip NR3 whose pins are connected further to conversion circuits 42 provided on the additional card, m which circuits the incoming V.ll-adapted signals are converted into TTL-level signals and the outbound TTL-level signals are converted into signals according to the V.ll recommendation. The conversion circuits are further connected to an adaptation circuit 43 which adapts the continuous data stream arriving from the direction of the connector FC2 to the internal bus BS2 of the base card to the correct time slots (i.e. it collects data into sections of suitable size and feeds them in the correct time slots to the bus BUS2) . In the opposite transmission direction, the adaptation circuit reads the data in certain time slots on the bus and forms from the data a continuous data stream towards the connector FC2. The adaptation circuit can be implemented for example m the form of an ASIC, a RAM-based FPGA circuit or a PLD circuit. In practice it can be implemented for example with the aforementioned circuit of the type XC 3090.

According to the invention, it is therefore essential that the base card comprises a time-division bus that can be configured in such a way that each component utilizing the bus can be allocated a time slot in which it operates. The bus must also comprise available time slots for new functions to be provided by means of an additional card. Figure 5a illustrates the frame structure of the buses BUS1 and BUS2. Each of the successive frames comprises 32 time slots (TSO to TS32) and each time slot comprises altogether eight bits (Bl to B8) . The frame structure of the buses corresponds otherwise to the frame structure according to the recommendation G.704, but the time slots TSO and TS16 do not have to be used in this case in the manner described in the recommendation (since the bus is an internal bus of the apparatus) . Figure 5b shows the situation before updating (Figure 3) wherein for example the time slots TSO and TSI are allocated to the signal processors (one for each) and the time slot TS29 is allocated to the circuit 33. Figure 5b shows the situation after the updating; the previously available time slots TS2, TS3, TS30 and TS31 are allocated to the circuit 43.

According to the invention, it is preferable that the bus of the control processor is connected via a pin strip (NR2 or NR4) to the additional card since in such a case the control processor of the base card can control the bus adaptation circuit 43 and therefore it can flexibly change the time slots allocated to the bus adaptation circuit. This is not necessary for the invention, however, since the bus adaptation circuit may be permanently allocated one or more time slots.

Also synchronization information must be supplied from the base card to the circuit 43 so that the circuit can operate at the correct time slot. The interfaces NR2 and NR4 therefore comprise a synchronization interface. The cross-connection circuit on the base card is particularly advantageous for the invention if one or more time slots are permanently allocated to the bus adaptation circuit 43. In such a case, it is still possible to "mix" the time slots in the cross-connection circuit, if some other card unit connected to the bus IB would happen to use

The above description of updating relates to the data interfaces of the base card. When an additional card is connected to the pin strips NRl and NR2, it is also possible to update the properties of the audio interfaces. By means of the additional card, one could for example add locally stored voice messages to different announcement systems, or different devices, such as CD players or DAT recorders, could be connected to an audio link.

Even though the invention is described above with reference to the examples according to the accompanying drawings, it is clear that the invention is not restricted thereto but it can be modified within the scope of the inventive idea disclosed above and in the appended claims. The detailed implementation of the invention will vary according to the type of the base card and the updating properties m question. It also depends on the operating environment for example if a direct access is needed from external pms of the card unit to the additional card. In principle, the additional card could also comprise a separate external interface so that the pm strips NR2 and NR4 would not be needed on the base card.

Claims

1. A method for updating properties of a card unit (SUB1 to SUBn) in an electronic apparatus, especially a telecommunication apparatus, with new properties, c h a r¬ a c t e r i z e d in that the new properties are formed on a separate additional card (AB) that is attached in parallel with the card unit and functionally connected to the card unit by allocating data corresponding to the new properties to available time slots of a time-division bus (BUS2) formed on the card unit.

2. A method according to claim 1, c h a r a c¬ t e r i z e d in that the allocation is carried out by means of a control processor (34) provided on said card unit, an interface (NR2; NR ) between the card unit and the additional card comprising control signals to be connected from the control processor to the additional card.

3. A method according to claim 1, c h a r a c- t e r i z e d in that some of the external pins of the card unit are connected directly to p s (NRl; NR3) formed on the card unit for the additional card, said external pins providing a direct access to the additional card.

4. A method according to claim 1, c h a r a c- t e r i z e d in that a place is reserved on the same card unit for more than one additional card (AB) .

5. An arrangement for updating properties of a card unit (SUB1 to SUBn) in an electronic apparatus, especially a telecommunication apparatus, with new properties, the arrangement comprising a time-division bus (BUS2) on the card unit, c h a r a c t e r i z e d in that it also comprises

- an additional card (AB) that is provided with said new properties, - connection means (NRl, NR2; NR3, NR4 ) provided on the additional card and the card unit for electrically connecting the additional card to the card unit, and

- bus adaptation means (43) provided on the additional card (AB) for writing data that corresponds to the new properties in the available time slots of the time- division bus (BUS2) and/or for reading said data from said time slots.

6. An arrangement according to claim 5, c h a r a c t e r i z e d in that some of the external pins of the card unit are connected directly to pins (NRl; NR3) formed on the card unit for the additional card, said external pins providing a direct access to the additional card.

7. An arrangement according to claim 5, c h a r a c t e r i z e d in that the connection means comprise an interface to data and address buses of a control processor (34) provided on the card unit.

8. An arrangement according to claim 5, c h a r a c t e r i z e d in that there is more than one additional card (AB) for the same card unit.