EP0853850A1 - Transmitting data between multiple computer processors - Google Patents
Transmitting data between multiple computer processorsInfo
- Publication number
- EP0853850A1 EP0853850A1 EP96931682A EP96931682A EP0853850A1 EP 0853850 A1 EP0853850 A1 EP 0853850A1 EP 96931682 A EP96931682 A EP 96931682A EP 96931682 A EP96931682 A EP 96931682A EP 0853850 A1 EP0853850 A1 EP 0853850A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- ring
- data
- rings
- node
- message
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/12—Avoiding congestion; Recovering from congestion
- H04L47/125—Avoiding congestion; Recovering from congestion by balancing the load, e.g. traffic engineering
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/42—Loop networks
- H04L12/437—Ring fault isolation or reconfiguration
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/46—Interconnection of networks
- H04L12/4637—Interconnected ring systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/11—Identifying congestion
Definitions
- the present invention relates to a method and apparatus for transmitting data between multiple computer processors.
- Prior art techniques for transmitting data between processors or nodes have proposed recovery mechanisms in the event of a fault occurring in a ring connecting the processors, wherein data messages to be transmitted are looped back at a particular node and directed to an unaffected ring by a physical connection to an unaffected link at the node. None of the prior art techniques suggests a way of monitoring the data traffic on each of the rings linking the processors to select an optimum route for data traffic to travel to its destination processor or node.
- a method of transmitting data between a plurality of nodes containing computer processors including the steps of: connecting the nodes by a plurality of unidirectional transmission rings such that each ring is in a closed loop configuration, said transmission rings being arranged to transmit data in alternately opposed directions around the rings between the processors; dynamically monitoring the traffic of data in each ring to obtain traffic information in each ring; and utilising said traffic information to select one of the rings to transmit data in accordance with certain criteria.
- the rings may be arranged in a layered configuration preferably comprising one or more pairs of unidirectional rings with each pair of rings being arranged to transmit data in opposite directions.
- each node comprises a plurality of message processors, one for each transmission ring.
- a communications system for transmitting data between a plurality of nodes in a network, comprising: a closed loop configuration of two or more unidirectional transmission rings connecting the nodes, the transmission rings being arranged to transmit data between the nodes in alternately opposed directions around the rings; each node including a respective message processor for each of the transmission rings; wherein the message processors are programmed to select one of the rings to be used for transmitting a message from a node to another node in accordance with certain criteria.
- Each node preferably includes a host processor which is linked to the message processors of the node.
- the host processor is preferably arranged to send the data message to each message processor associated with the originating node, and the message processors of the originating node select a ring on which the data is to be transmitted by utilizing the monitored information.
- the traffic of data in each ring may be monitored to obtain information on any one or more of the following: the available ring capacity; the data flow rate or traffic loading on each ring; and fault identification.
- the message processors may perform their selection on the basis of information obtained from a look-up table.
- the look-up table may contain information about the number of ring links along which a data message has to travel along each ring between the nodes to reach its destination so that the shortest route for the data message can be determined.
- the look-up table may also contain information about the data flow rate or traffic loading on each ring. Thus when one ring contains a lot of traffic and is congested, another ring may be selected.
- the look-up table is preferably dynamically updated for each new data message to be sent. For this purpose, counting means may be provided for counting the number of messages queued for transmission at a node or nodes of the system.
- a method in accordance with the invention may include the steps of determining whether data to be transmitted is priority data containing priority information and selecting one of the rings to transmit the priority data so as to provide the most expeditious route for the data to reach a destination node.
- Packets of data containing priority information may contain a flag in a priority field to enable a message processor to determine that the data packet contains priority information. Packets of data having priority and queued for transmission may be transmitted ahead of packets queued for transmission that do not have priority.
- one ring may be selected to transmit data of a particular kind and all other data is arranged to be transmitted on the other ring of a ring pair or, where there are more than two rings, on the other rings of the system. This is particularly useful when there is a large amount of data for a particular task to be transmitted from one node to another.
- the method and system of the present invention may include means for performing maintenance functions, such as fault detection means for detecting when faults occurs in the transmission rings.
- fault detection means for detecting when faults occurs in the transmission rings.
- the system when a fault is detected in one of the transmission rings, the system is arranged to transmit data messages only on the ring or rings not affected by the fault. This is in contrast to prior art techniques in which data messages are looped back at a node by a physical correction and directed onto an unaffected ring.
- the method and system of the invention utilize Scalable Coherent Interface (SCI) technology.
- SCI Scalable Coherent Interface
- the nodes in the system of the present invention preferably include scalable coherent interfaces (SCIs) which provide bus services by transmitting packets of data on print-to-print unidirectional links between the nodes.
- SCIs scalable coherent interfaces
- FIG. 1 is a schematic circuit block diagram of a communications system in accordance with the invention
- Figure 2 is a flow chart of a traffic control process used in the invention
- Figure 3 is a particular example of the diagram of Figure 1;
- Figure 4 is a schematic block diagram showing the maintenance functions associated with a node
- Figure 5 is a frame structure for messages transmitted between message and most processors
- Figure 6 shows the maintenance (MA) information flow between a host processor and message processors at a node
- Figure 7 shows the transfer of maintenance information in the event of a fault occurring in one of the transmission rings of the system
- Figure 8 shows a fault recovery mechanism flow chart when a fault occurs
- Figure 9 is a block diagram of the main components of a message processor
- Figure 10 is a block diagram showing the architecture of a NodeChip interconnection of the transmission rings and the message processors of the system.
- a topology of a Scalable Two- Way Ring (S2R) Structure comprising a loop 10 and four nodes, A to D, connected therein.
- the loop 10 comprises a pair of transmission rings 1 and 2 with each of the nodes A to D connected in the path of each ring 1 and 2.
- the structure has a scalable architecture which provides for multiple ring-layers so as to cope with various services, capacity and fault tolerances.
- the particular topology shown in Figure 1 is an example of a two-layer physical configuration to provide for services and single fault recovery over the same physical layer.
- the loop 10 may be considered as two identical ring layers, an inner ring 1 and an outer ring 2.
- the loop 10 provides a bus service with packets that it transmits on point- to- point unidirectional links 21 and 22 between the nodes A to D.
- Each node, A to D comprises two identical Interface Message Processors (IMPs), labelled 5 and 6, each being connected to a respective ring 11 or 12 of the loop 10.
- IMPs Interface Message Processors
- Each node may have more than two IMPs depending on the number of rings required.
- a host processor at an originating node is required to send the same message to all identical IMPs associated with each ring at the same originating node. The IMPs then decide which ring is to be used to send the message.
- the decision will be based on the information provided from a Dynamic Look-Up Table in accordance with a Traffic Control process, to be discussed with reference to Figure 2.
- the host will sequentially retrieve the message from each of the IMPs, e.g. 5 and 6, on the same node.
- the transmission paths of inner ring 1 and outer ring 2 are arranged in opposite directions.
- the transmission path of data in the inner ring 1 is in a clockwise direction from node A to node D.
- the transmission path of data in the outer ring 2 is in a counter-clockwise direction from node D to node A.
- packets can easily be routed between two adjacent nodes without going through the whole ring 1 or 2, to avoid traffic congestion. For example, when data is to be transmitted from node A to node B it may be transmitted along ring 1 and when data is to be transmitted from node A to node D it may be transmitted along ring 2.
- data may be transmitted from node A to node D along ring 1 when there is less traffic in that ring than in ring 2. It is to be noted that any number of rings may be used, with the rings arranged in a layered structure, and that any number of nodes may be connected within each ring.
- S2R protocol In order to handle the non-stop transmitting data between multiple computer processors over the network, a protocol, called the S2R protocol, has been developed on top of SCI protocols in the IMP.
- the S2R protocol will perform the functions of traffic control and data integrity control.
- Start Node being the originating node from which a message is to be transmitted
- EJ being the destination or termination node for the message
- R j Ring Identity
- NJ Node Cost (NJ, being the number of ring links a message has to pass through to reach the destination node;
- T-J Traffic Loading
- Next Ring Used being the next ring chosen to transmit a message, on the basis of a decision of the IMPs using the Traffic Control Process;
- Ring Total being the total number of rings in the network
- TL,J Maximum Traffic Load
- This table will be dynamically updated to reflect the amount of traffic in the network. Therefore, by implementing the dynamic table of traffic control process, when a packet is received by a local traffic controller in an IMP, it will be able to select the most efficient routing.
- the steps that the algorithm uses can be demonstrated using the flow chart of Figure 2.
- the source address and destination address are set to S n and E n respectively, at step 202, to initiate the search of the dynamic table at step 204.
- Ring #11 A transmission from 61 to 66, Ring #11 is chosen.
- the updated entries are:
- Ring #11 A transmission from 61 to 66, Ring #11 is chosen.
- the updated entries are:
- Ring #11 5 61 69 11 3 2 11 5 A transmission from 61 to 66, Ring #11 is chosen.
- the updated entries are:
- Ring #12 A transmission from 61 to 66, Ring #12 is chosen.
- the updated entries are:
- Ring #11 A transmission from 61 to 62, Ring #11 is chosen.
- the updated entries are:
- Ring #12 A transmission from 61 to 62, Ring #12 is chosen.
- the updated entries are:
- the initial set up shows two entries 1 and 2 for a message to be transmitted from start node 61 to end node 66 along rings 11 and 12 respectively, two entries 3 and 4 for a message to be transmitted from start node 61 to end node 62; and two entries 5 and 6 for a message to be transmitted from start node 61 to end node 6.
- the next ring to be used NR is the outer ring 11 for all entries 1 to 6.
- the ring identity is ring 12
- step 212 the process proceeds to step 212 to see if R id equals NR U .
- R id equals NR U .
- it does and so the message is transmitted on the same ring, i.e. ring 11 and the T ld for ring 11 is incremented by 1 to the value of 3 as seen in table 1(d) for entry 1.
- the next ring used NR U for entries 1 and 2 is then updated to ring 12 in table 1(d).
- a new message to be sent from start node 61 to end node 66 will now be transmitted on ring 12 and the values of T M and C c for entries 2, 4 and 6 are incremented as shown by Table 1(e). For entries 2, 4 and 6 the traffic loading is updated to 1. The traffic loading for entry 1 remains at 4 as it has now changed rings.
- the priority routing concept can be employed. This will ensure that a packet with a high priority can by-pass the normal rule of routing and get to the destination as soon as possible. For example, if a packet is queued for transmission at node 61 and intended for node 66 along inner ring 11, if it has priority over other packets queued ahead of it, then that priority packet may be transmitted to node 66 along ring 12 provided that this is the most expeditious path.
- the force ring scheme can be used to delegate a task to a particular ring. That is, a selected ring will only be used to transmit particular specified messages while the other ring will carry the remainder of the traffic. It is particularly useful when there is a large amount of data required to transfer from one node in the network to another node. Data Integrity Control To ensure the message is transmitted correctly and accurately within the network, Message Verification and Message Sequencing will be utilized during the transmission.
- a Checksum, Address Validation and Message Length Check will be used for the Message Verification.
- a host processor sends a message to the IMPs, there must be a Checksum attached to the message.
- Each IMP makes its own calculation and compares it to the Checksum received in the message. If there is a mismatch, the message is discarded and an error signal will be issued to the host.
- UFC User-defined Flow Control
- a response ACK will be generated and returned to the sending node. If the message is faulty in some way, the message will be discarded and no response will be generated.
- Both the value of the timeout T ⁇ and the RC m are programmable from the host by setting the Control and Status Registers (CSR) in IMP.
- CSR Control and Status Registers
- each IMP 5, 6 includes a S2R maintenance module 410 for performing
- SCI maintenance functions Between the S2R maintenance modules and the maintenance software in each host processor 60, there is established an S2R protocol which can implement the functions when necessary.
- a local processor bus protocol is established between the S2R and SCI maintenance modules 410 and
- the layer maintenance handles the specific maintenance information flows and provides the services to the upper layer.
- FIG. 5 there is shown the frame structure 500 for a message transmitted between a host processor 60 and its associated IMPs 5, 6.
- the first field of bits 510 is reserved for the User-defined Flow Control (UFC), the coding and functionality of the bits being determined depending on the user application.
- the second field 520 is the destination address field, the bits indicating address data relevant to the destination node.
- the PT field 530 designates the Payload Type and is coded in 2 bits indicating the type of message including the data message, command message and the idle message.
- the Maintenance (MA) field 540 of 4 bits carries the information related to side identifier, fault and traffic status.
- the Priority (P) field 550 indicates whether or not a message has priority over other messages to be transmitted.
- the Payload Field 560 contains the actual data to be transmitted or command data such as for the dynamic look-up table, or for the CSR during initialisation.
- the last field 570 is reserved for the Checksum for message verification.
- Figure 6 shows information flow relating to the maintenance (MA) between the host and the message processors 5, 6.
- MA maintenance information bits
- packets 620 When a message is transmitted from the host 60 to any of message processors 5 and 6, packets 620 have the maintenance information bits (MA) 630 attached to them via multiplexer 610.
- the MA field is placed in the frame header resulting in the combined packet 640 being transmitted.
- the host 60 will extract or strip the MA bits 630 from each packet 650 and place the maintenance bits in the MA field of the next outgoing message.
- SCI Maintenance Functions SCI Maintenance Functions
- CRC Cyclic Redundancy Check
- the node When sending a packet, the node will expect an acknowledgement to occur within a timeout period. If the sender does not receive the acknowledgement within this timeout period, it will increment the fault counter and cause the Status bit of Echo timeout to be asserted. Retransmission might then be done dependent on the application of the maintenance software.
- the IMP defines a working mode and a protection mode. In normal operation, the IMP is configured in a working mode. If a fault X is detected, say on ring 12 of the network shown in Figure 7, the MA bits will be sent from IMP 5, connected in the faulty ring 12, via its host processor 60 to the other IMP 6 associated with each particular node so that transmission can resume on ring 11. In this way the IMP is reconfigured in a protection mode whereby all packets can be transmitted on the fault-free ring 11. This fault recovery mechanism is normally expected to be handled by S2R maintenance functions as shown in Figure 8.
- the maintenance functions monitor each IMP for faults at step 810, and if a fault 815 is detected at 815, the maintenance functions are invoked to reconfigure the IMP to the protection mode at 820.
- the IMP is re-initialized at 830 when repairs have been carried out to remove the fault.
- the particular procedure will be as follows:
- Node installation or node replacement will not affect the normal traffic over the network.
- Each host will send a command message to IMPs to update the dynamic look-up table and CSR after the new node has been installed.
- the IMP of the new ring will send MA bits to the other side to take over the traffic, the old ring can then be disconnected and installed with the new IMP for the new node.
- each IMP of the working ring i.e. protection node
- the same procedure will also be applied to the node replacement except the update of the dynamic table.
- Each IMP shown as 13 in Figure 9, comprises three main parts, a transmitter/receiver section 15, a S2R Protocol Controller (SPC) 16 and an SCI NodeChip 17.
- the SPC 16 contains digital logic in a single Application Specific Integrated
- ASIC Circuit/Field Programmable Gate Array
- FPGA Field Programmable Gate Array
- Node-to-Node interconnection is implemented using the SCI NodeChip 17, which is a single-chip solution complaint with the physical and logical layers of the SCI standard as defined in the American National Standards Institute/Institute of Electrical and Electronics Engineers (ANSI/IEEE) Standard 1596-1992.
- the NodeChip is a Trade Mark of Dolphin Intemconnect Solutions and its functions are explained in technical reference manual of the manufacturer.
- the SCI NodeChip 17 is implemented in low-power, CMOS technology. It provides an input link 19 and output link 20 for unidirectional communication suitable for node-to-node ring topologies.
- a 64-bit bidirectional bus 18, called CBus, provides a communication path between the SCI NodeChip 17 and SPC 16.
- the link control unit 21 of NodeChip 17 comprises an input control 22 for receiving packets of data from other IMPs, an output control 23 for transmitting packets from its respective IMP to other IMPs on the same ring, and a bypass first in first out (FIFO) buffer 24 connected between each input control 22 and output control 23 of the NodeChips 17 associated with each IMP.
- FIFO bypass first in first out
- Figure 10 shows the architecture of an S2R loop having two ring layers 1 and 2 with three nodes A, B and C in which the output control 23 of a first NodeChip 17A is connected via a link 21 of a transmission ring to the input control 22 of the 17B associated with a neighbouring node B on the same ring layer 1 and so on until the ring is complete.
- the output control 23 of the NodeChip 17C of the last node C in the ring is linked to the input control of the first IMP NodeChip 17A.
- the bypass FIFO 24 is connected between the input control 22 and output control 23 of each NodeChip 17.
- Buffer control 25 oversees the control of storing and queuing packets of data that have been received in RX buffer 26 and those packets stored and queued ready for transmission in the TX buffer 27.
- Each of the NodeChip 17 and SPC 16 has a CBus Interface Unit 30 and 31 respectively for translating the packets and signals transmitted and received on CBus 18 into a format suitable for use respectively by the NodeChip 17 and SPC 16.
- the Control and Status Registers (CSR) 29 store data for carrying specified tasks within the IMP and the host.
- the SPC 16 interfaces the SCI NodeChip 17 to the host processor and translates read and write transactions supported by the NodeChip 17 to transfer data between the host processor bus 14 and the remote S2R nodes.
- the protocol conversion functions between the NodeChip 17 and host processor are carried out under the control of S2R Protocol Control Unit 32.
- CBus control unit 33 oversees the control of data transmitted over and received from the CBus 18.
- FIFO buffers 34 and 35 stack the packets of data being transmitted to and received from the host and NodeChip 17 on a first-in first-out basis.
- the buffers are connected between CBus Interface Unit 31 and Bus Interface Unit 36 which receives and transmits the data packets to the TX/RX section 15.
- a two-byte wide differential pseudo-ECL signal provides the link speed between the nodes of 125 Mbytes/s.
- a Hewlett Packard G-Link HDMP-1000 parallel-to-serial chipset is used.
- the NodeChip can directly interface to this chipset to achieve 1 Gbit/s serial coaxial communication over distances of tens of metres.
- the interconnection of each of the IMPs associated with a particular node is done through a processor bus 37, where each associated IMP is on a different ring layer. This enables each node to select the most appropriate ring to use to transmit a particular message.
- the embodiment described hereinabove has disclosed a Scalable Two- Way Ring (S2R) architecture that uses the SCI technology to produce a highly reliable self-recovery ring system.
- S2R Scalable Two- Way Ring
- a simple self-recovery procedure has been described based on the SCI protocols and leads to a rapid recovery from transmission line failure.
- the S2R protocol has the advantages of scalability, modularity, rapid self- recovery and real-time node installation and replacement.
- a dynamic traffic control algorithm has been described which enhances the utilisation of the dual-ring capacity.
- the user-defined flow control scheme handles the data sequencing while force ring and priority routing schemes provide the user the flexibility of the ring system.
- the maintenance information flow scheme avoids the physical connections between the IMPs as well as providing a cost-effective transfer of maintenance information over the ring system.
- the described embodiment discloses a dual ring loop or system using a commercial SCI chipset. Clearly, because of its scalable architecture it can be designed in multiple loop layers to
- the dual ring architecture has the ability to recover rapidly from transmission line failure by having an altemative ring-layer and a simple recovery procedure. If one ring goes down the other will take over its work at reduced performance, but the system can still maintain a certain degree of traffic until the faulty part is fixed and brought back into operation. For military, banking, telecommunication and many other applications, the ability to continue operating in the face of hardware problems is of great importance. Since modifications within the spirit and scope of the invention may be readily effected by persons skilled in the art, it is to be understood that the invention is not limited to the particular embodiment described, by way of example, hereinabove.
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AUPN5737A AUPN573795A0 (en) | 1995-10-02 | 1995-10-02 | Transmitting data between multiple computer processors |
AUPN5737/95 | 1995-10-02 | ||
PCT/AU1996/000621 WO1997013344A1 (en) | 1995-10-02 | 1996-10-02 | Transmitting data between multiple computer processors |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0853850A1 true EP0853850A1 (en) | 1998-07-22 |
EP0853850A4 EP0853850A4 (en) | 2001-04-18 |
Family
ID=3790065
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP96931682A Withdrawn EP0853850A4 (en) | 1995-10-02 | 1996-10-02 | Transmitting data between multiple computer processors |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0853850A4 (en) |
AU (1) | AUPN573795A0 (en) |
CA (1) | CA2231380A1 (en) |
WO (1) | WO1997013344A1 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6487606B1 (en) * | 1998-11-18 | 2002-11-26 | Nortel Networks Limited | System and method for delivering messages through a totem communications system |
SE514430C2 (en) * | 1998-11-24 | 2001-02-26 | Net Insight Ab | Method and system for determining network topology |
JP2001285322A (en) * | 2000-03-28 | 2001-10-12 | Fujitsu Ltd | Inter-lan communication equipment and inter-lan communication network using the equipment |
EP1276262A1 (en) * | 2001-07-10 | 2003-01-15 | Lucent Technologies Inc. | Communication network ring with data splitting in the nodes |
US7280482B2 (en) * | 2002-11-01 | 2007-10-09 | Nokia Corporation | Dynamic load distribution using local state information |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4663748A (en) * | 1984-04-12 | 1987-05-05 | Unisearch Limited | Local area network |
JP2663687B2 (en) * | 1990-07-27 | 1997-10-15 | 日本電気株式会社 | ATM communication system in dual ring network |
FR2665967B1 (en) * | 1990-08-16 | 1994-09-16 | France Etat | COMPUTER NETWORK WITH WRITING RING AND READING RING, STATION INSERABLE IN SUCH A NETWORK, METHOD FOR CONNECTION, RECONFIGURATION AND PROTOCOL FOR ACCESSING SUCH A NETWORK. |
JP2513919B2 (en) * | 1990-09-05 | 1996-07-10 | 株式会社日立製作所 | Reconfiguration function stop prevention method for configuration controller |
US5179548A (en) * | 1991-06-27 | 1993-01-12 | Bell Communications Research, Inc. | Self-healing bidirectional logical-ring network using crossconnects |
US5406401A (en) * | 1992-10-02 | 1995-04-11 | At&T Corp. | Apparatus and method for selective tributary switching in a bidirectional ring transmission system |
US5282199A (en) * | 1992-12-29 | 1994-01-25 | International Business Machines Corporation | Method and apparatus for interoperation of FDDI-I and FDDI-II networks |
-
1995
- 1995-10-02 AU AUPN5737A patent/AUPN573795A0/en not_active Abandoned
-
1996
- 1996-10-02 EP EP96931682A patent/EP0853850A4/en not_active Withdrawn
- 1996-10-02 WO PCT/AU1996/000621 patent/WO1997013344A1/en not_active Application Discontinuation
- 1996-10-02 CA CA002231380A patent/CA2231380A1/en not_active Abandoned
Non-Patent Citations (2)
Title |
---|
No further relevant documents disclosed * |
See also references of WO9713344A1 * |
Also Published As
Publication number | Publication date |
---|---|
AUPN573795A0 (en) | 1995-10-26 |
EP0853850A4 (en) | 2001-04-18 |
WO1997013344A1 (en) | 1997-04-10 |
CA2231380A1 (en) | 1997-04-10 |
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