EP0838104A1 - Method and apparatus for amplifying an electrical signal - Google Patents
Method and apparatus for amplifying an electrical signalInfo
- Publication number
- EP0838104A1 EP0838104A1 EP96922628A EP96922628A EP0838104A1 EP 0838104 A1 EP0838104 A1 EP 0838104A1 EP 96922628 A EP96922628 A EP 96922628A EP 96922628 A EP96922628 A EP 96922628A EP 0838104 A1 EP0838104 A1 EP 0838104A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- output
- stage
- voltage
- input
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
- H03F1/083—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
Definitions
- the present invention is related to electronic amplifiers. More particularly, multiple output stage amplifiers which provide a first output stage for driving an error stage and a second output stage for driving an output load are contemplated.
- the output signal source might be an output terminal of an amplifier stage driving a next stage (which may be more circuitry or perhaps an electro-mechanical device such as a audio speaker) having a load impedance Z L .
- the loading effect 2 ⁇ of the following stage causes reduction and/or nonlinearities in a gain and a phase response of the amplifier stage.
- the result is an output signal which has both a distorted magnitude and a distorted phase.
- phase distortion Historically, a primary focus of the amplifier designer has been on elimination of gain distortion. In essence, this has been driven by two factors. First, the causes of phase distortion require more sophisticated analysis. Second, and perhaps most importantly, past applications have relied mainly on the magnitude of the output signal, often ignoring the phase component. Hence, even if phase distortion was present in the output signal, it was not a significant problem.
- a few example technologies in which the presence of phase distortion is typically not an issue include audio, radio, telecommunications, and electromechanical technology such as that utilized in strain gauges.
- the amplifier 10 includes an input 12, an output 14, a converting stage 16, a load resistor R L1 , an inverting stage 20, and a buffer output stage 22.
- the converting stage 16 is coupled to the input 12 and receives an input signal having a voltage V ⁇ present on the input.
- the converting stage 16 then converts the voltage V ⁇ to a current signal through a transconductance Al (voltage to current gain) and transmits this current to the load resistor R L1 .
- the resistor R L1 is coupled together with both the converting stage 16 and the inverting stage 20 at one end of the resistor, and to a ground reference 24 at the resistor R L1 's other end.
- the current generated by the converting stage is reconverted to a second voltage which is received by the inverting stage 20.
- the inverting stage 20 amplifies the second voltage by a gain -A2 to generate a third voltage transmitted to the buffer output stage 22.
- gains Al and A2 are frequency dependent parameters that introduce signal response poles and generally degrade stability under feedback conditions. That is, if the amplifier 10 is inco ⁇ orated into an electrical system which utilizes feedback, the signal response pole introduced by gains Al and A2 will degrade the overall performance of the electrical system. Additionally, gain A3 can vary with the output load demand, generating distortion in the output signal whether or not the amplifier 10 is utilized within a feedback system.
- FIG. 2 Another amplifier 35 of the prior art will be described.
- the amplifier 35 is a common attempt to modify Fig. 1 through feedback providing phase compensation.
- a capacitor C c is connected around the output of the inverting stage 20 and coupled to the input of the inverting stage 20 and to the resistor R L1 .
- the gain A2 of the inverting stage 20 amplifies the capacitance C c delivering an equivalent capacitance of A2*C C .
- the value of C c actually required for successful phase compensation reduces to a level realizable with integrated circuit fabrication.
- C c While the introduction of C c may result in beneficial phase compensation and perhaps more stable feedback systems, the feedback through C c introduces significant distortion and may limit a slewing rate of the amplifier 35.
- the distortion results from an interaction between an output resistance R o2 of the inverting stage 20 and a parasitic capacitance C p coupled to the ground reference 24.
- the parasitic capacitance C p is introduced by C c .
- parasitic capacitance such as C P is generated during most integrated circuit fabrication processes and is due to a standard junction isolation technique.
- the parasitic capacitance C p is generated at a point in the structure of amplifier 35 where the full voltage V ou ⁇ of the output signal will drop across C p . Accordingly, a resulting parasitic capacitive current I p develops causing an error voltage with the output resistance R o2 of the inverting stage 20. If the error voltage were constant it would be a determinable offset (i.e. a constant error as opposed to distortion) for which could be compensated (say by adding a correction signal or tuning a larger feedback system in which the amplifier 35 is present). However, the magnitude of the parasitic capacitance C p is not constant, but rather, it varies with the voltage drop across C p . Hence, the error in the output signal varies with the magnitude input voltage. That is, the output signal is distorted.
- the C c connection also effects the slewing rate for the amplifier 35.
- an amplifier's slewing rate defines the maximum rate of change in voltage across the input and output teirninals of the amplifier and is normally expressed in volts per second (dV/dt). It will now be shown that the amplifier 35 of Fig. 2 produces a slewing- rate versus current efficiency compromise.
- voltage gain stages such as the inverting amplifier 20 typically have output current limits determined by the level of their quiescent currents (provided by, e.g., the amplifiers internal, substantially constant, biasing current source).
- the amplifier 40 compensates for the relatively high output resistance of the inverting amplifier 20 by coupling the feedback capacitor C c to the output of the buffer amplifier stage 22 (instead of the inverting amplifier 20).
- the electrical characteristics of the buffer amplifier stage 22 make it more suitable (in some ways) for providing the feedback current I FB than the inverting stage 20.
- the internal resistance R o3 is usually much smaller than R o2 as the buffer amplifier stage is intended to provide the large output current I Q ⁇ .
- the capacitive current I-, drawn through C p in the amplifier 40 will be much smaller than that drawn in amplifier 35 of Fig. 2.
- the voltage error across C c of Fig. 3 will be smaller than the voltage error across C c of Fig. 2.
- the buffer amplifier stage 22 since the buffer amplifier stage 22 is intended to drive the output load, it typically has a much larger quiescent current. The larger available output current results in an improved skewing rate dV/dt.
- the amplifier 40 of Fig. 3 retains a significant gain distortion and introduces a subtle phase distortion as a result of the variability of the output resistance R o3 of the buffer amplification stage 22.
- the higher load currents necessary for driving the output load R L3 cause significant variation in the output resistance R o3 .
- the effect of R o3 on the gain of the amplifier 40 can be determined as follows.
- the output resistance R o3 V I L where, as will be appreciated by those skilled in the art, V t is the semiconductor thermal voltage of the output stage 22.
- Fig. 4 illustrates another prior art power amplifier 44 which substantially eliminates the aforementioned phase distortion by introducing an isolation stage 30.
- the isolation stage 30 eliminates the dependence of A3 upon the load current I L by isolating the feedback capacitor C c from the output stage 22. Because of the isolation, the gain product A2*A3 that influences the f c pole frequency is immune to the effects of load current I L . Nevertheless, the amplifier 44 reintroduces some gain distortion and further leaves a couple of issues unresolved.
- the amplifier 44 has no error control circuitry in direct relation to its output 14 (e.g., feedback or feedforward), no gain correction is provided.
- the I L current demands produce gain distortion through the inevitable output resistance modulation of the load-driving output stage 22.
- the amplifier 44 provides an improvement in phase distortion only at the expense of greater gain distortion.
- an isolation current I IS0 driving the feedback capacitor C c still loads the isolation stage 30 causing distortion therein.
- any distortion in the isolation stage 30 causes a corresponding distortion at the output
- a dual-output stage amplifier includes an amplifier stage having an input and an output, a first output stage having an input and an output, a second output stage having an input and an output and an error stage having an input and an output.
- the first output stage output is coupled with the output of the amplifier stage and responsive to the amplifier stage. If the first output stage output is coupled to an output load, the first output stage is capable of providing an output current to the output load such that a first output voltage related to an input voltage at the input of the amplifier stage is maintained across the output load.
- the second output stage input is coupled with the output of the amplifier stage and in parallel with the first output stage.
- the second output stage output is coupled to the input ofthe error stage while the output of the error stage is coupled to the input of the amplifier stage.
- the error stage is capable of providing a feedback current to the amplifier stage input such that a difference between a second output voltage generated by the second output stage and a desired second output voltage is reduced.
- the error stage has a gain operable to amplify an electrical signal applied at the error stage input.
- the gain of the error stage may have a current gain greater than unity, a voltage gain greater than unity, or may have both a current gain and a voltage gain greater than unity.
- a multiple amplification stage amplifier in another, separate embodiment of the present invention, includes an input amplification stage having an input and an output, a plurality of successive amplification stages each having an input and an output, a plurality of error stages each having an input and an output and corresponding to a unique one of the plurality of successive amplification stages, and an output stage having an input and an output.
- the input of a first one of the plurality of successive amplification stages is connected to the output of the input amplification stage and further, with the exception of a last one of the plurality of successive amplification stages, the output of any given amplification stage is connected to the input of a next amplification stage immediately subsequent to the given amplification stage.
- each amplification stage drives a single, next amplification stage.
- each error stage output is connected to the input amplification stage input and each error stage output is connected to the output of its corresponding unique amplification stage.
- the present embodiment further teaches that any given error stage is capable of providing a feedback current to the amplification stage input such that a difference between a voltage generated at the output of its corresponding amplification stage and a desired voltage is reduced.
- the output stage input is coupled with the input of the last amplification stage, and, if the output stage output is coupled to an output load, the output stage is capable of providing an output current to the output load such that an output voltage related to an input voltage at the input of the input amplification stage is maintained across the amplifier load.
- a power amplifier comprising, a power amplifier input coupled to an input signal having a voltage V m and a current 1 ⁇ , a power amplifier output at which an output signal is generated having a voltage V ou ⁇ and a current I ou ⁇ , an amplifier stage coupled to the power amplifier input and responsive to the input signal to generate an amplified signal having a voltage an isolation stage coupled to the amplifier stage and responsive to the amplified signal to generate an isolated signal having a voltage V IS0 and I IS0 , an error stage coupled between the isolation stage and the power amplifier input and responsive to a difference between the V IS0 and a desired V ⁇ to generate a feedback current I FB operative to modify the input signal such that the difference between the V 1S0 and the desired V IS0 is reduced and a difference between the V ou ⁇ and a desired V ou ⁇ is also reduced, an output stage coupled between the amplifier stage and the power amplifier output and responsive to the amplified signal to generate the output signal, and a current dumping resistor R CD coupled between the isolation stage
- a method for amplifying an electrical signal, the method including the steps of receiving an input signal having a voltage V ⁇ and a current 1 ⁇ , generating an amplified signal having a voltage and a current related to the input signal, generating an isolated signal having a voltage V ISO and a current I B0 related to the amplified signal, generating an output signal having a voltage V ou ⁇ related to the amplified signal and a current I ou ⁇ related to an output load, sensing a difference between the voltage V JSO ⁇ a desired V IS0 , and, generating a feedback current 1 ⁇ related to the difference between the voltage V IS0 and the desired V IS0 .
- the present invention teaches that when the current l ⁇ is included into the current I IN , the difference between the voltage V IS0 and the desired V ⁇ is reduced and, further, a difference between the voltage V ou ⁇ and a desired V ou ⁇ is reduced.
- Fig. 1 is a schematic illustration of a basic amplifier of the prior art
- Fig. 2 is a schematic illustration of an amplifier of the prior art which improves upon the basic amplifier of Fig. 1;
- Fig. 3 is a schematic illustration of another amplifier of the prior art which improves upon the amplifier of Fig. 2;
- Fig. 4 is a schematic illustration of one other amplifier ofthe prior art
- Fig. 5 is a schematic block diagram of a dual stage output amplifier in accordance with one embodiment ofthe present invention.
- Fig. 6 is a schematic/block diagram of a dual stage output amplifier in accordance with another embodiment ofthe present invention.
- Fig. 7 is a schematic illustration of a bipolar dual stage output amplifier in accordance with yet another embodiment of the present invention.
- Fig. 8 is a schematic illustration showing in more detail one bipolar output stage in accordance with still another embodiment of the present invention, the bipolar output stage suitable for use as isolation stage 54 or output stage 58 of Figs. 5 and 6;
- Fig. 9 is a schematic block diagram of a multi-stage amplifier in accordance with another embodiment ofthe present invention.
- Figs. 1-4 illustrate the prior art.
- the power amplifier 50 includes an amplifier stage 52, an isolation stage 54 (equivalently a second output stage), an error stage 56, an output stage 58, a power amplifier input 60, and a power amplifier output 62.
- a converting stage 64 Also shown in Fig. 5 is a converting stage 64, a load resistor R L1 coupled between the power amphfier input 60 and a ground reference 66, and an output load resistor R coupled between the power amplifier output 62 and the ground reference 66. Note that, unless otherwise indicated, all voltages discussed herein are defined with reference to the ground reference 66.
- a voltage signal received by the converting stage 64 is amplified and converted into a current signal ⁇
- a current 1 ⁇ is formed in part from current I cs and is reconverted into a voltage signal V ⁇ by the load resistor R LI .
- the amplifier stage 52 amplifies this input signal and generates an amplified signal having a voltage and a current I AMP .
- the amplified signal serves to drive both the isolation stage 54 and the output stage 58.
- the isolation stage 54 generates an amplified signal having a voltage V IS0 and a current I IS0 and the output stage 58 generates an amplified signal at the power amphfier output 62 having a voltage V ou ⁇ and a current I ou ⁇ driving the load resistor R .
- the actual load may be a simple resistive load such as R M or it may be an impedance Z ⁇ .
- R M simple resistive load
- Z ⁇ impedance
- the error stage 56 is coupled across the isolation stage 54 and the input 60 and is responsive to a difference between the voltage V IS0 and a desired voltage V 1S0 to generate a feedback current l m .
- the current I FB will "correct" 1 ⁇ such that the difference between the voltage V, so and a desired voltage V ISO is decreased. Furthermore, this will ⁇ -inimize a difference between the voltage V ou ⁇ and a desired voltage V ou ⁇ thereby minimizing distortion in the output signal.
- the error stage 56 consists of a buffer amplifier with a unity voltage gain and a greater than unity current gain driving a capacitor C c . Then, in comparison to the power amphfier 44 of Fig. 4, the current gain would reduce the current I ISO loading upon the isolation stage 54 for a reduction of the distortion arising from the variable output impedance of isolation stage 54.
- the error stage 56 includes an amplifier having a voltage gain G greater than unity driving a capacitor having a capacitance C c /G.
- the voltage gain reduces the value of the capacitance required to provide adequate phase compensation.
- the error stage 56 includes an amplifier having a voltage gain G and a current gain greater than unity, and a capacitor having a capacitance C ⁇ JG. In this embodiment, the gains of the amphfier both reduce distortion and reduce the required feedback capacitance size.
- the gain of the amphfier stage 52 is defined as A2
- the gain of the isolation stage 54 is defined as A3
- the gain of the error stage 56 is defined as A- ⁇
- the gain of the output stage 58 is defined as A4.
- the isolation stage 54 isolates the amplifier stage 52 from any parasitic capacitance in the circuit without having to supply the amplifier 50' s output load current I ou ⁇ .
- A3 is not subject to variations in the output load current I ou ⁇ . Therefore the gain product A2*A3 which helps define the pole f CI remains immune to the effects of the output load current I ou ⁇ .
- the phase distortion of power amplifier 50 of Fig. 5 is greatly reduced with respect to the phase distortion of power amplifier 40 of Fig. 3.
- the error stage 56 provides one of current gain greater than unity, voltage gain greater than unity, or a combination of current and voltage gain greater than unity, the power amphfier 50 has correspondingly improved characteristics over the power amplifier 44 of Fig. 4.
- the amplifier 70 is a strategic modification of the amphfier 50 of Fig. 5 which permits a compromise balance between a correction in gain distortion and a correction in phase distortion.
- the gains A3 and A4 are equal.
- the gain A ⁇ of the error stage 56 may be solely capacitive, or A ⁇ may provide current gain, voltage gain, or a combination of current and voltage gain.
- Like names and reference numbers will be used for like elements.
- the output load current demands may cause a gain distortion through an output resistance modulation of the output stage 58.
- This is similar to that described above with reference to Figs. 3 and 4.
- the output resistance modulation of the output stage 58 causes variation in the gain A4 which, in turn, produces gain distortion in the power amplifier gain A ⁇ .
- the two parallel output stages enable a technique defined herein as "current dumping.”
- R CD draws its current from the isolation stage 54 and thus may distort the gain A3, which, in turn, results in potential phase distortion. Therefore, the value of R CD , should be chosen to produce a desired compromise balance between gain and phase distortion. Additionally, when the error stage 56 has a current gain greater than unity, less current I IS0 is demanded of the isolation stage 54.
- the amphfier stage 52 includes an amplifier 82, two diode-connected transistors Ql and Q2, and a current source I s .
- the amplifier 82 can be one of a variety of standard construction well familiar to those skilled in the art, as well as any other amplifier designed for a particular application.
- the transistors Ql and Q2, together with the current source I s provide a common bias current supply for the two output stages 54 and 58.
- Transistors Q3 and Q4 form the isolation stage 54, driving the error stage 56 and the optional current dumping resistor R CD .
- Transistors Q5 and Q6 form the output stage 58 which serves as the primary source of the load current I ou ⁇ . Both of these stages 54 and 58 are powered from a bipolar power source of voltage V+ and V-.
- the output stage 58 are what is termed in the art "open loop.” That is, they do not include any internal error correction mechanism. While open loop operation of the amplifiers may be suitable for some applications, other applications may require a more robust mechanism. In particular, the output stage 58 will be more likely than the isolation stage 54 to require error correction. This is due, in part, to the error correction provided to the isolation stage 54 by the error stage 56 and the larger current requirements of the output stage 58.
- bipolar output stage 300 in accordance with a further embodiment of the present invention will now be described.
- the bipolar output stage 300 is well suited for applications where a current efficient output stage is required and may be used for either isolation stage 54, output stage 58, or two separate instances of output stage 300 may be used for both.
- the bipolar output stage 300 can be figuratively divided into two circuits: a first circuit which provides a positive component of the output current I out ; and a second circuit (which is a mirror of the first set) which provides a negative component of the output current I out .
- Elements of the first circuit of the output stage 300 are indicated with the marker "a” appended to their respective reference numbers while the mirrored elements are indicated with the marker "b” appended to their respective reference numbers.
- the modifying terms "positive” and "negative” have been added to the names of the different stages.
- the output stage 300 includes positive and negative feedforward stages
- V+ 165 a and V- 165b providing power to the bipolar output stage 300.
- the positive current mirror 158a provides a variable, demand driven biasing current to the positive amplifying stage 160a as follows.
- the positive feedforward stage 156a senses a voltage difference between the amplified signal and the output signal
- the positive feedforward stage 156a increases the current control signal I c correspondingly.
- the positive current mirror 158a mirrors and amplifies I c to generate a correspondingly larger demand driven current signal I d .
- the second circuit is arranged to generate a negative current I ou ⁇ .
- power amplifier 300 can generate a bipolar output signal.
- the bipolar output stage 300 is able to generate an output signal in a current efficient manner.
- V SAT is the maximum voltage drop across the positive current mirror 158a and V BE is a voltage drop across a standard amplifier.
- FIG. 9 a multi-stage amplifier 75 in accordance with another embodiment of the present invention will be described.
- a core concept of the present invention is the isolation of a signal driving an error stage from unnecessary loads which may result in phase distortion and/or gain distortion. While the embodiments of Figs. 5 and 6 illustrate this concept of the present invention, it will be appreciated that this concept can be suitably applied in other circuits. For example, it is sometimes necessary or preferable to design an amplifier with multiple stages of amplification. Such is the case in Fig. 9.
- Fig. 9 includes an integer N number of stages of amplification.
- the multi-stage amphfier 75 includes an amplifier stage 1 52-1, an isolation stage 1 54-1, an error stage 1 56-1, and so forth, on up to amplifier stage N 52-N, an isolation stage N 54-N, and an error stage 1 56-N.
- each error stage i 56-i (where l ⁇ i ⁇ N) is isolated from its corresponding amplifier stage i 56-i and further from the output stage 58.
- the output stage 58 is driven by the output of the final amplifier stage N 52-N and an optional current dumping resistor R CD is coupled between the output 62 and the output of the final isolation stage N 54-N.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
Description
Claims
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US716 | 1987-01-06 | ||
US71695P | 1995-06-30 | 1995-06-30 | |
US08/666,859 US5736900A (en) | 1996-06-19 | 1996-06-19 | Method and apparatus for amplifying an electrical signal |
US666859 | 1996-06-19 | ||
PCT/US1996/011134 WO1997002655A1 (en) | 1995-06-30 | 1996-06-28 | Method and apparatus for amplifying an electrical signal |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0838104A1 true EP0838104A1 (en) | 1998-04-29 |
EP0838104A4 EP0838104A4 (en) | 2001-11-21 |
Family
ID=26668041
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP96922628A Withdrawn EP0838104A4 (en) | 1995-06-30 | 1996-06-28 | Method and apparatus for amplifying an electrical signal |
Country Status (2)
Country | Link |
---|---|
EP (1) | EP0838104A4 (en) |
WO (1) | WO1997002655A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7061313B2 (en) | 2000-05-05 | 2006-06-13 | Telefonaktiebolaget Lm Ericsson (Publ) | Dual feedback linear amplifier |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4524327A (en) * | 1981-07-09 | 1985-06-18 | Tokyo Shibaura Denki Kabushiki Kaisha | Operational amplifier |
US4751474A (en) * | 1986-02-28 | 1988-06-14 | Sgs-Thomson Microelectronics S.P.A. | Broadband amplifier incorporating a circuit device effective to improve frequency response |
US5117200A (en) * | 1990-12-03 | 1992-05-26 | Crystal Semiconductor Corporation | Compensation for a feedback amplifier with current output stage |
US5121080A (en) * | 1990-12-21 | 1992-06-09 | Crystal Semiconductor Corporation | Amplifier with controlled output impedance |
-
1996
- 1996-06-28 EP EP96922628A patent/EP0838104A4/en not_active Withdrawn
- 1996-06-28 WO PCT/US1996/011134 patent/WO1997002655A1/en not_active Application Discontinuation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4524327A (en) * | 1981-07-09 | 1985-06-18 | Tokyo Shibaura Denki Kabushiki Kaisha | Operational amplifier |
US4751474A (en) * | 1986-02-28 | 1988-06-14 | Sgs-Thomson Microelectronics S.P.A. | Broadband amplifier incorporating a circuit device effective to improve frequency response |
US5117200A (en) * | 1990-12-03 | 1992-05-26 | Crystal Semiconductor Corporation | Compensation for a feedback amplifier with current output stage |
US5121080A (en) * | 1990-12-21 | 1992-06-09 | Crystal Semiconductor Corporation | Amplifier with controlled output impedance |
Non-Patent Citations (1)
Title |
---|
See also references of WO9702655A1 * |
Also Published As
Publication number | Publication date |
---|---|
WO1997002655A1 (en) | 1997-01-23 |
EP0838104A4 (en) | 2001-11-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0618673B1 (en) | A differential amplification circuit wherein a DC level at an output terminal is automatically adjusted | |
US6313704B1 (en) | Multi-stage signal amplifying circuit | |
US5789981A (en) | High-gain operational transconductance amplifier offering improved bandwidth | |
EP1444777B1 (en) | A power amplifier module with distortion compensation | |
KR950007836B1 (en) | Cmos power amplifier | |
US5736900A (en) | Method and apparatus for amplifying an electrical signal | |
US6542033B2 (en) | Differential amplifier circuit requiring small amount of bias current in a non-signal mode | |
CN111414039A (en) | Linear voltage regulator circuit adopting on-chip compensation technology | |
US6833760B1 (en) | Low power differential amplifier powered by multiple unequal power supply voltages | |
JP2000223970A (en) | Rail-to-rail amplifier and signal amplification processor | |
CN117792300B (en) | Amplifier and oscilloscope | |
US6294958B1 (en) | Apparatus and method for a class AB output stage having a stable quiescent current and improved cross over behavior | |
US6621439B1 (en) | Method for implementing a segmented current-mode digital/analog converter with matched segment time constants | |
KR100416168B1 (en) | Power amplifier | |
WO1997002655A1 (en) | Method and apparatus for amplifying an electrical signal | |
US20060132233A1 (en) | Integrated circuit devices having a control circuit for biasing an amplifier output stage and methods of operating the same | |
JP4027981B2 (en) | Bridge amplifier with load feedback | |
US5519357A (en) | Biasing arrangement for a quasi-complementary output stage | |
EP2293434B1 (en) | Switched amplifier circuit arrangement and method for switched amplification | |
US6563384B1 (en) | High gain amplifier with rail to rail range and frequency compensation | |
US6870426B2 (en) | Output stage, amplifier and associated method for limiting an amplifier output | |
US6771120B2 (en) | Reference generation technique for multiple-reference amplifier | |
US9985589B2 (en) | System and method for improving total harmonic distortion of an amplifier | |
TW531954B (en) | RF power amplifier with distributed bias circuit | |
JP2004179998A (en) | Preamplifier |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 19980130 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): DE FR GB IE IT NL |
|
RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: SMITH, DOUGLAS, L. |
|
A4 | Supplementary search report drawn up and despatched |
Effective date: 20011005 |
|
AK | Designated contracting states |
Kind code of ref document: A4 Designated state(s): DE FR GB IE IT NL |
|
RIC1 | Information provided on ipc code assigned before grant |
Free format text: 7H 03F 3/26 A, 7H 03F 1/08 B |
|
17Q | First examination report despatched |
Effective date: 20021218 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 20030429 |