EP0817097A3 - Sous-système d'interconnexion utilisant un agencement de commutation de degré limité pour un système multiprocesseur avec un petit nombre de processeurs - Google Patents

Sous-système d'interconnexion utilisant un agencement de commutation de degré limité pour un système multiprocesseur avec un petit nombre de processeurs Download PDF

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Publication number
EP0817097A3
EP0817097A3 EP97304720A EP97304720A EP0817097A3 EP 0817097 A3 EP0817097 A3 EP 0817097A3 EP 97304720 A EP97304720 A EP 97304720A EP 97304720 A EP97304720 A EP 97304720A EP 0817097 A3 EP0817097 A3 EP 0817097A3
Authority
EP
European Patent Office
Prior art keywords
nodes
topologies
class
ring
ladder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP97304720A
Other languages
German (de)
English (en)
Other versions
EP0817097A2 (fr
Inventor
Steven K. Heller
Guy L. Steele
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of EP0817097A2 publication Critical patent/EP0817097A2/fr
Publication of EP0817097A3 publication Critical patent/EP0817097A3/fr
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17306—Intercommunication techniques
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17375—One dimensional, e.g. linear array, ring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/12—Discovery or management of network topologies

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computing Systems (AREA)
  • Multi Processors (AREA)
EP97304720A 1996-07-01 1997-06-30 Sous-système d'interconnexion utilisant un agencement de commutation de degré limité pour un système multiprocesseur avec un petit nombre de processeurs Withdrawn EP0817097A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/675,629 US5859983A (en) 1996-07-01 1996-07-01 Non-hypercube interconnection subsystem having a subset of nodes interconnected using polygonal topology and other nodes connect to the nodes in the subset
US675629 1996-07-01

Publications (2)

Publication Number Publication Date
EP0817097A2 EP0817097A2 (fr) 1998-01-07
EP0817097A3 true EP0817097A3 (fr) 2000-07-05

Family

ID=24711327

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97304720A Withdrawn EP0817097A3 (fr) 1996-07-01 1997-06-30 Sous-système d'interconnexion utilisant un agencement de commutation de degré limité pour un système multiprocesseur avec un petit nombre de processeurs

Country Status (4)

Country Link
US (3) US5859983A (fr)
EP (1) EP0817097A3 (fr)
JP (1) JPH1091602A (fr)
KR (1) KR980010820A (fr)

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US6111859A (en) * 1997-01-16 2000-08-29 Advanced Micro Devices, Inc. Data transfer network on a computer chip utilizing combined bus and ring topologies
US6018782A (en) * 1997-07-14 2000-01-25 Advanced Micro Devices, Inc. Flexible buffering scheme for inter-module on-chip communications
US6266797B1 (en) 1997-01-16 2001-07-24 Advanced Micro Devices, Inc. Data transfer network on a computer chip using a re-configurable path multiple ring topology
US5974487A (en) * 1997-07-14 1999-10-26 Advanced Micro Devices, Inc. Data transfer network on a chip utilizing a mesh of rings topology
US6490661B1 (en) 1998-12-21 2002-12-03 Advanced Micro Devices, Inc. Maintaining cache coherency during a memory read operation in a multiprocessing computer system
US6393529B1 (en) 1998-12-21 2002-05-21 Advanced Micro Devices, Inc. Conversation of distributed memory bandwidth in multiprocessor system with cache coherency by transmitting cancel subsequent to victim write
US6631401B1 (en) 1998-12-21 2003-10-07 Advanced Micro Devices, Inc. Flexible probe/probe response routing for maintaining coherency
US6370621B1 (en) 1998-12-21 2002-04-09 Advanced Micro Devices, Inc. Memory cancel response optionally cancelling memory controller's providing of data in response to a read operation
US6603742B1 (en) 1999-06-02 2003-08-05 Sun Microsystems, Inc. Network reconfiguration
US6631421B1 (en) * 1999-06-02 2003-10-07 Sun Microsystems, Inc. Recursive partitioning of networks
US6791939B1 (en) 1999-06-02 2004-09-14 Sun Microsystems, Inc. Dynamic generation of deadlock-free routings
US20020091855A1 (en) * 2000-02-02 2002-07-11 Yechiam Yemini Method and apparatus for dynamically addressing and routing in a data network
JP3718621B2 (ja) * 2000-06-23 2005-11-24 株式会社ルートレック・ネットワークス インターネットアドレス決定方法及び装置
US6996504B2 (en) * 2000-11-14 2006-02-07 Mississippi State University Fully scalable computer architecture
US20040158663A1 (en) * 2000-12-21 2004-08-12 Nir Peleg Interconnect topology for a scalable distributed computer system
US8086738B2 (en) * 2007-05-24 2011-12-27 Russell Fish Distributed means of organizing an arbitrarily large number of computers
US20030009509A1 (en) * 2001-06-22 2003-01-09 Fish Russell H. Distributed means of organizing an arbitrarily large number of computers
US7035539B2 (en) * 2002-01-09 2006-04-25 Fujitsu Limited Interconnecting nodes in an optical communication system
AU2003252157A1 (en) * 2002-07-23 2004-02-09 Gatechange Technologies, Inc. Interconnect structure for electrical devices
US7620736B2 (en) * 2003-08-08 2009-11-17 Cray Canada Corporation Network topology having nodes interconnected by extended diagonal links
US7853754B1 (en) * 2006-09-29 2010-12-14 Tilera Corporation Caching in multicore and multiprocessor architectures
US8140719B2 (en) * 2007-06-21 2012-03-20 Sea Micro, Inc. Dis-aggregated and distributed data-center architecture using a direct interconnect fabric
US7872990B2 (en) * 2008-04-30 2011-01-18 Microsoft Corporation Multi-level interconnection network
US11271871B2 (en) 2008-09-11 2022-03-08 Juniper Networks, Inc. Methods and apparatus related to a flexible data center security architecture
US9847953B2 (en) * 2008-09-11 2017-12-19 Juniper Networks, Inc. Methods and apparatus related to virtualization of data center resources
US20120155273A1 (en) * 2010-12-15 2012-06-21 Advanced Micro Devices, Inc. Split traffic routing in a processor
US9436637B2 (en) * 2013-05-17 2016-09-06 Advanced Micro Devices, Inc. Network-on-chip architecture for multi-processor SoC designs
US10747298B2 (en) 2017-11-29 2020-08-18 Advanced Micro Devices, Inc. Dynamic interrupt rate control in computing system
US10503648B2 (en) 2017-12-12 2019-12-10 Advanced Micro Devices, Inc. Cache to cache data transfer acceleration techniques
US11210246B2 (en) 2018-08-24 2021-12-28 Advanced Micro Devices, Inc. Probe interrupt delivery

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0234618A1 (fr) * 1986-01-30 1987-09-02 Koninklijke Philips Electronics N.V. Réseau de stations de traitement de données
WO1989001665A1 (fr) * 1987-08-14 1989-02-23 Regents Of The University Of Minnesota Topologie hypercube pour systemes multiprocesseurs avec voies de communication additionnelles entre les noeuds ou topologies avec angles substitues
WO1989003564A1 (fr) * 1987-10-08 1989-04-20 Eastman Kodak Company Architecture d'entree/sortie amelioree pour ordinateurs en parallele connectes toroidalement et a memoires reparties
DE3911206A1 (de) * 1989-04-06 1990-10-11 Siemens Ag Automatisierungsgeraet
EP0514043A2 (fr) * 1991-05-13 1992-11-19 International Business Machines Corporation Système de calculateur

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US4797882A (en) * 1985-10-02 1989-01-10 American Telephone And Telegraph Company, At&T Bell Laboratories Mesh-based switching network
US5170482A (en) * 1987-08-14 1992-12-08 Regents Of The University Of Minnesota Improved hypercube topology for multiprocessor computer systems
US5170393A (en) * 1989-05-18 1992-12-08 California Institute Of Technology Adaptive routing of messages in parallel and distributed processor systems
US5134690A (en) * 1989-06-26 1992-07-28 Samatham Maheswara R Augumented multiprocessor networks
US5280607A (en) * 1991-06-28 1994-01-18 International Business Machines Corporation Method and apparatus for tolerating faults in mesh architectures
JP2512272B2 (ja) * 1992-01-10 1996-07-03 インターナショナル・ビジネス・マシーンズ・コーポレイション マルチプロセッサ・コンピュ―タ・システムおよびそのデ―タ割振り方法
US5271014A (en) * 1992-05-04 1993-12-14 International Business Machines Corporation Method and apparatus for a fault-tolerant mesh with spare nodes
US5642524A (en) * 1994-09-29 1997-06-24 Keeling; John A. Methods for generating N-dimensional hypercube structures and improved such structures
US5592610A (en) * 1994-12-21 1997-01-07 Intel Corporation Method and apparatus for enhancing the fault-tolerance of a network
US5610744A (en) * 1995-02-16 1997-03-11 Board Of Trustees Of The University Of Illinois Optical communications and interconnection networks having opto-electronic switches and direct optical routers

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0234618A1 (fr) * 1986-01-30 1987-09-02 Koninklijke Philips Electronics N.V. Réseau de stations de traitement de données
WO1989001665A1 (fr) * 1987-08-14 1989-02-23 Regents Of The University Of Minnesota Topologie hypercube pour systemes multiprocesseurs avec voies de communication additionnelles entre les noeuds ou topologies avec angles substitues
WO1989003564A1 (fr) * 1987-10-08 1989-04-20 Eastman Kodak Company Architecture d'entree/sortie amelioree pour ordinateurs en parallele connectes toroidalement et a memoires reparties
DE3911206A1 (de) * 1989-04-06 1990-10-11 Siemens Ag Automatisierungsgeraet
EP0514043A2 (fr) * 1991-05-13 1992-11-19 International Business Machines Corporation Système de calculateur

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
HERBORDT M C ET AL: "COMPUTING PARALLEL PREFIX AND REDUCTION USING COTERIE STRUCTURES", PROCEEDINGS OF THE SYMPOSIUM ON THE FRONTIERS OF MASSIVELY PARALLEL COMPUTATION,US,LOS ALAMITOS, IEEE COMP. SOC. PRESS, vol. SYMP. 4, 1992, pages 141 - 149, XP000344493 *

Also Published As

Publication number Publication date
EP0817097A2 (fr) 1998-01-07
US6138166A (en) 2000-10-24
KR980010820A (ko) 1998-04-30
US6138167A (en) 2000-10-24
US5859983A (en) 1999-01-12
JPH1091602A (ja) 1998-04-10

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