EP0812439A1

EP0812439A1 - Architecture for efficient interpolator

Info

Publication number: EP0812439A1
Application number: EP96902734A
Authority: EP
Inventors: Paul Asher Kline; Dirk Anderson Bell
Original assignee: Watkins Johnson Co
Current assignee: BAE Systems Aerospace Electronics Inc
Priority date: 1995-01-26
Filing date: 1996-01-22
Publication date: 1997-12-17
Also published as: WO1996023264A1; EP0812439A4

Abstract

An efficient architecture for an interpolator (100) disposed to process oversampled data is disclosed herein. The interpolator (100) includes an input divider circuit (104) configured to receive an input data word over an input data line. A register (108) is provided for latching the divided input data word from the divider (104). The divided input data word is added within a summer (112) to a latched divided data word from the register, thereby forming a summed data word. A multiplexer (116) produces an interpolated output by multiplexing the summed data word with an input data word. In a preferred implementation, the register (108) is latched at a first clock rate, and the multiplexer (116) is clocked at twice the first clock rate. The efficient filter architecture allows interpolation to be performed in the absence of multipliers, and in a manner using filter coefficients equivalent to powers of two. This enables the interpolator (100) to be realized inexpensively, and renders the filter particularly suitable for implementation within integrated circuits.

Description

ARCHITECTURE FOR EFFICIENT INTERPOLATOR

Field of the Invention This invention relates generally to the field of digital filters used for digital signal processing and communications. In particular, it pertains to a digital architecture for performing high-speed interpolation of oversampled signals without relying upon multipliers, and by using filter coefficients that are powers of two.

Background of the Invention In general, the purpose of a communication system is to transmit information-bearing message signals from a source to a user destination. A communication system generally consists of three basis components: transmitter, channel, and receiver. The transmitter has the function of processing the message signal into a form suitable for transmission over the channel. This processing of the message signal is referred to as modulation. In any communication system, the "channel bandwidth" defines the range of frequencies that the channel can handle for the transmission of signals with satisfactory fidelity. Channel bandwidth is important because, for a prescribed band of frequencies characterizing a message signal, the channel bandwidth determines the number of such message signals that can be multiplexed over the channel. In other words, for a prescribed number of independent message signals that have to share a common channel, the channel bandwidth determines the band of frequencies that may be allotted to the transmission of each message signal without discernible distortion.

Analog and digital transmission methods are used to transmit a message signal over acommunication channel. The use of digital methods offers several operational advantages over analog methods, including but not limited to: increased immunity to channel noise and interference, flexible operation of the system, and a common format for the transmission of different kinds of message signals.

In high-speed digital transmitters, the task of creating wideband communication channels often involves producing a frequency-division multiplexed (FDM) wideband signal from input narrowband baseband signals. For example, the input signals may comprise many voice channels with bandwidths of only a few kilohertz, which prior to transmission are combined into a wideband signal spanning many megahertz. In order to prevent aliasing of the information included within the wideband signal, it will generally be necessary that the sample rate of the voice channels be significantly increased during conversion of the narrowband signal to a wideband signal.

The process of increasing the sample rate is typically performed by "interpolating" the sampled information in one or more stages. At each stage of interpolation, a higher sample rate is achieved by effectively inserting one or more zero samples between each incoming sample of the incident lower-rate data stream. Following this zero-padding operation, the data stream is filtered in order to suppress spurious signal energy created by the zero-padding. This filtering has often been performed using finite impulse response (FIR) digital filters.

The conventional hardware implementation of an FIR digital filter utilizes delay units, multipliers, and adders. Among these filter components, multipliers often occupy a relatively large circuit area, which tends to increase the cost of the filter. Moreover, cost is often not the only significant factor of interest, and operational speed may often be of even greater significance at the high sample rates required during the later stages of interpolation. In the conventional FIR digital filter, the maximum sample rate is often determined by the speed of the multipliers. Accordingly, to improve operational speed and reduce cost, it is desirable to eliminate multipliers from FIR filters.

One such "multiplierless" FIR digital filter is described by Benvenuto et al., Dynamic Programming Methods for Designing FIR Filters Using Coefficients -1, 0 and +1; IEEE Transactions on Acoustics, Speech and Signal Processing, Volume ASSP-34, Number 4, August 1986. These filters are comprised of a transversal filter with tap coefficients restricted to a coefficient space of -1 , 0 and + 1 , and cascaded with simple recursive sections. This type of filter is well-suited to high-speed (i.e., high sample rate) filtering applications since the integral tap coefficients are easily implemented in digital hardware. However, improved performance can be achieved, while maintaining ease of implementation, through a multiplierless filter characterized by a coefficient space of 2 ⁿ.

Objects of the Invention Accordingly, it is an object of the present invention to provide an efficient architecture for interpolating oversampled data.

Summary of the Invention

In summary, the present invention comprises an efficient architecture for interpolating oversampled data, such as a stream of digitized voice data. The efficient interpolator includes an input divider circuit, which receives an input data word over an input data line. A register is provided for latching the divided input data word from the divider. The divided input data word is added within a summer to the previously latched data word from the register, thereby forming a summed data word. A multiplexer produces an interpolated output by multiplexing the summed data word with the input data word.

In a preferred implementation the register is latched at a first clock rate, and the multiplexer is clocked at twice the first clock rate.

The efficient interpolator architecture allows interpolation to be performed in the absence of multipliers, and simultaneously allows filtering to be achieved using coefficients equivalent to powers of two. This enables the interpolator to be realized inexpensively, and renders the interpolator particularly suitable for implementation within integrated circuits.

Brief Description of the Drawings Additional objects and features of the invention will be more readily apparent from the following detailed description and appended claims when taken in conjunction with the drawings, in which:

FIG. 1 shows a simplified block diagrammatic representation of the architecture of an interpolator using a conventional 3-tap filter.

FIG. 2 shows a block diagram of the architecture of an interpolator of the present invention.

FIG. 3 depicts a specific hardware realization of an interpolator of the present invention.

FIG. 4 is a block diagram of an interpolator network designed to interpolate by a factor of thirty two. FIG. 5 is a block diagram of a specific hardware implementation of an interpolating filter which does not require an output multiplexer. Detailed Description of the Preferred Embodiment In order to provide appropriate context for a description of the present invention, an overview is initially provided of a conventional manner in which the sample rate of a digital sequence is increased by a factor of 2 through a zero-padding and filtering process. In particular, consider an infinite sample sequence x(k), where x(k) = ..., x(-2), x(-l), x(0), x(l), x(2), x(3), ..., which may be represented in the digital frequency domain as X(w), where co X(w) = Σ x(k)e^jwk k = -oc

Assuming the samples x(k) to be of a sample rate f_s, increasing the sample rate to 2f, by zero padding yields the sample sequence y(k), where y(k) = ..., x(-2), 0, x(-l), 0, x(0), 0, x(l), 0, x(2),... That is, y(k) ^•= x(k/2), k even y(k) = 0, k odd. In the digital frequency domain,

OO CO

Y(w) = Σ y(k)e^{jwk =} Σ y(k)e^"jwlc k = -co k=-co k,even

CO = Σ y(2k)e^{"j wk} k =- oo

= X(2w)

It is observed that X(w) is periodic with a period of 2τ radians, and that Y(w) is periodic with a period of T radians. This results in an image of the input frequency domain response appearing within the frequency domain representation of the zero-padded output, i.e. , within Y(w) centered at a frequency equivalent to the sample rate of the input sequence x(k). In order to eliminate the unwanted high-frequency "image" arising within Y(w) due to zero padding, the sequence y(k) will typically be passed through a low-pass filter having an impulse response represented by h(k). The resultant filtered sequence, y_Lp(k), may be expressed as: co co co y_LP(k) = Σ y(i) (k-i) = Σ y(ι)h(k-/) = Σ y(2 )h(k-2/) = - CO = - co = - co i even o

J = - 00

The low-pass filter employed to obtain y_LP(k) is typically realized using two distinct filters. A first filter, characterized by impulse response h_e(k) is applied to the samples of the sequence x(k); and a second filter, having an impulse response h₀(k), is also utilized to filter the samples of x(k). Specifically, if h_e(k) = h(2k) h₀(k) = h(2k+ l), then the even samples in the low-pass filtered sequence may be represented by: co y_LP(2p) = Σ x(j)h(2p-2j) j = -co

00

= Σ x(j)h(2(p-j)) j = -oo

and the odd samples in the low-pass filtered output sequence may be expressed as:

co y_LP(2p+ l) == Σ J , xx(Gi))hh((22pp++ ll--22j) j = -∞

co

= ∑ x(j)h(2(p-j) + l), j = -∞ Accordingly, co y_LP(2p) = Σ x(j)h_e(p-j), j = -•» where y_LP(2p) corresponds to the sequence x(k) filtered by h_e(k). Similarly, co y_LP(2p+ l) = Σ x(j)h₀(p-j), j = -co which corresponds to the sequence x(k) filtered by h₀(k).

Turning now to FIG. 1 , a simplified block diagrammatic representation is provided of the architecture of a 3-tap interpolating filter 10 designed to effect the zero padding and low-pass filtering operations described above. The interpolating filter 10 includes a switch 14, which alternately couples the even, i.e., y_LP(2p), and odd, i.e., y_LP(2p+ l), low-pass filtered samples to the filter output. As is indicated by FIG. 1 , the input sample sequence is provided to an input shift register 18, which stores consecutive input samples x(p) and x(p-l). Input register 18 provides the sample x(p) to first and second multipliers 20 and 22, and provides the sample x(p-l) to a third multiplier 24. The "even" filter coefficients h_e(0) and h_e(l) are stored within a first filter register 28, and are respectively provided to the multipliers 20 and 24. The "odd" filter coefficient, h_o(0), is stored within a second filter register 32 connected to multiplier 22.

The scaled sample values x(p) and x(p-l) produced by multipliers 20 and 24 are summed within adder 36, which produces the "even" low-pass filtered output samples y_LP(2p). The "odd" low-pass filtered output samples, y_Lp(2p+ 1), are produced by multiplier 22. The complete low-pass filtered output sequence is obtained by toggling the switch 14 between the outputs of adder 36 and multiplier 22.

Unfortunately, implementation of the filter architecture of FIG. 1 at a high sample rate is relatively expensive, as it is necessary to realize digital multipliers. Moreover, the large wafer area, or "real-estate" generally required by digital multipliers renders the architecture of FIG. 1 particularly disadvantageous for integrated circuit implementations. Referring to FIG. 2, a block diagram is provided of the architecture of the interpolating filter 100 of the present invention. The interpolating filter 100 is seen to not include any digital multipliers, thereby enabling cost-effective integrated circuit implementation. As is indicated by FIG. 2, the input sample sequence x(m) impressed upon input terminal 102 is received by a divide-by-two circuit 104. The divided samples of the input sequence are sequentially latched, at the clock rate of the input sequence x(m), by a register 108. Each consecutive pair of divided samples, i.e. , x(m)/2 and x(m-l)/2, are combined within adder 112. The output of adder 112 forms the "even" terms of the interpolated output sequence applied to a first input terminal 114 of the multiplexing output switch 116. The sequence of even terms is denoted as y_LP(2m), and the sequence of odd terms as y_LP(2m + l), where m = ... -2, -1 , 0, 1 , 2, ... The output multiplexing switch

116 operates to multiplex, at twice the input clock rate, the sequences of even and odd terms applied to the switch terminals 114 and 118.

The output sequence y_LP(n) may be viewed as comprising an interpolated (by a factor of two) version of the input sequence x(n). Specifically, the filtering of the sequence y(n) during the interpolation process is performed in accordance with the impulse response function h(n), wherein: h(n) = 1/2, n = 0

1 , n = 1

1/2, n = 2 0, else

Alternately, h(n) may be expressed as: h(n) = h_e(n/2), for even values of n, h₀([n-l]/2), for odd values of n, where even and odd samples of the input sequence x(n) are processed by a filter having an impulse response specified by h_e(n) and h₀(n), respectively. Recall h_e(n) = h(2n) and h₀(n)=h(2n + l), so: h_e(n) = 1/2, n = 0

1/2, n = 1 0, else, and, h₀(n) = 1, n = 0

0, else

The filtering of x(n) in accordance with the impulse response h_e(n), yields a filtered output sequence y_LP(2m): co y_LP (2m) -= Σ xO)h_e( -j) = x(m)h_e(0) + x(m-l) h_e(l) j = -°°

= [1/2] • x(m) + [1/2] • x(m-l)

= [1/2] • [x(m) + x(m-l)] wherein "•" denotes multiplication. Similarly, the output samples of the output sequence y_LP(2m + 1) may be expressed as: co y_Lp(2m + l) = Σ x(j)h₀(m-j) = x(m)h_o(0) =x(m)l j = -^oo = x(m) That is, the "odd" samples within the output sequence y_LP(m), i.e., y_LP(2m + 1), correspond to the input sequence. This correspondence is seen to be manifested within the filter architecture of FIG. 2, since the switch terminal 118 is directly connected to the input terminal 102. Similarly , direct correspondence is also seen to exist between this expression for y_LP(2m) and the architecture of the filter 100. Namely, the divide-by-two circuit 104 introduces the factor of (1/2) and the register 108 is used to provide the samples [1/2] • x(m) and [1/2] • x(m-l), the adder 112 performs the required addition operation. Turning now to FIG. 3, there is shown a specific hardware realization of an interpolating filter 200 of the present invention. In the embodiment of FIG. 3, the filter 200 processes the 14-bit samples comprising the input sequence x(n). The thirteen most significant bits (MSBs) of each 14-bit input sample are simultaneously clocked, at the input sample rate f_s, into a 13-bit register 204. Since each 14-bit input sample corresponds to a binary number, the extraction of the thirteen MSBs from each sample effectively results in division by two. The 13-bit register 204 will generally be comprised of a set of thirteen D-type flip-flops, each of which latches one of the thirteen MSBs of each input sample. The thirteen MSBs of each pair of consecutive samples are added within 13-bit adder 208, and the 14-bit result provided to an output multiplexer 212. The multiplexer 212 operates to produce the output sequence y_LP(m) by multiplexing, at the output sample rate of twice f„ the sequence of 14-bit values from the adder 208 with the 14-bit input sequence x(n). In a preferred implementation , the "even " output sample component associated with a given input sample is output by the filter 200 before the corresponding "odd" sample component. The filter 200 is seen to be capable of being realized very efficiently, in that it requires only a register comprised of 13 flip-flops, a 14-bit adder, and a multiplexer. Using terminology familiar to those skilled in the art, the filter 200 may be described as functioning as a 3-tap finite impulse response (FIR) half-band filter having coefficients of 1/2, 1, 1/2.

Turning now to FIG. 4, there is shown an interpolating filter network 300 designed to interpolate by a factor of thirty-two. The filter network 300 is comprised of a set of five serially-connected interpolation-by-two filters of the present invention (see, e.g. , FIG. 3). The filter network 300 may be included within, for example, a digital transmitter disposed to convert multiple low data rate, oversampled, narrowband input sequences into a high data rate, wideband output sequence. For example, in a specific embodiment input data having a baseband bandwidth of approximately 14 kHz is applied at a rate of 960 Ksps to the network 300. The oversampled characteristic of the input data (i.e., high sampling rate relative to the Nyquist rate) allows each interpolation-by-two stage to be realized using the half-band architecture of FIG. 3. In this exemplary application each interpolation-by-two stage provides a low-pass filtering function characterized by a -3 dB frequency of approximately 14 kHz, passband ripple of less than approximately 0.25 dB, and image rejection on the order of 67dB.

Referring to FIG. 5, a block diagram is provided of an alternate realization of an inteφolating filter 400 of the present invention. In the embodiment of FIG. 5, the filter 400 processes the 14-bit samples comprising the input sequence x(n) of sample rate f_s. The bits of each 14-bit input sample are simultaneously clocked, at a rate of 2f_s, into a 14-bit register 404. The 14-bit register 404 will generally be comprised of a set of fourteen D-type flip-flops, each of which latches one of the bits of each input sample. The fourteen bits of each pair of consecutive samples are added within 14-bit adder 408, and the 14 MSBs from the result of each addition comprise the output of the filter 400. In particular, the output of the filter 400 may be represented as:

... x(n), l/2[x(n) + x(n-l)], x(n-l), l/2[x(n-l) + x(n-2)], x(n-2), ... The filter 400 may be described as functioning as a 3-tap finite impulse response (FIR) half-band filter having coefficients of 1/2, 1, 1/2, which is disposed to operate upon a zero-padded sample sequence (i.e. , one "padding" zero per sample). While the present invention has been described with reference to a few specific embodiments, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims.

Claims

WHAT IS CLAIMED IS:

1. An inteφolator comprising: means for receiving an input data word, and for dividing said input data word by removing one or more bits from said input data word; a register for latching said divided input data word; a summer for summing said divided input data word with a latched data word from said register to thereby form a summed data word; and a multiplexer for producing an inteφolated output by multiplexing said input data word with said summed data word.

2. The inteφolator of claim 1 wherein said input data word includes N data bits, said divided input data word being comprised of N-l most significant bits of said input data word.

3. The inteφolator of claim 2 wherein said register comprises an N-l bit parallel data register.

4. The inteφolator of claim 1 wherein said register is latched at a first clock rate and said multiplexer is clocked at twice said first clock rate.

5. An inteφolator comprising: a divider for dividing each data word within a sequence of input data words; a register for latching each of said divided input data words received from said divider; a summer having first and second input data ports respectively connected to an output of said divider and to an output of said register, said summer producing a sequence of summed data words; and a multiplexer for multiplexing each of said input data words with one of said summed data words.

6. The inteφolator of claim 5 wherein said register is latched at a first clock rate and said multiplexer is clocked at a second clock rate approximately twice said first clock rate, said multiplexer producing an inteφolated output at twice said first clock rate.

7. The inteφolator of claim 5 wherein each of said input data words includes N bits, said divider forming each of said divided data words by extracting the N-l least significant bits from a corresponding one of said input data words.

8. A method for inteφolating a sequence of input data words comprising the steps of: dividing each of said input data words; delaying each of said divided input data words; summing each of said divided input data words with a delayed one of said divided input data words to thereby produce a sequence of summed data words; and multiplexing each of said input data words with one of said summed data words.

9. The method of claim 8 wherein said step of delaying each of said input data words includes the step of latching each of said input data words at a first clock rate.

10. The method of claim 9 wherein said step of multiplexing is performed at a second clock rate equal to twice said first clock rate.

11. The inteφolator of claim 2 wherein said register comprises an N-l bit parallel register and said summer comprises an N-bit adder with input sign extension.

12. An inteφolator comprising: an N-bit input data line upon which is impressed an N-bit input data word; an N-l bit register connected to most significant N-l bit lines of said input data line; a summer having a first input port connected to said N-l bit lines of said input data line and having a second input port connected to an N-l bit output data line of said N-l bit register, said summer producing an N-bit result; and a multiplexer having an input connected to said N-bit input data line and an input for receiving said N-bit result from said summer, said multiplexer impressing an N-bit output data word upon an N-bit output line.

13. The inteφolator of claim 12 wherein said N-l bit register is latched at a first clock rate and said multiplexer is clocked at a second clock rate twice said first clock rate.