EP0754350A4 - Cavity filled metal electronic package - Google Patents

Cavity filled metal electronic package

Info

Publication number
EP0754350A4
EP0754350A4 EP95913778A EP95913778A EP0754350A4 EP 0754350 A4 EP0754350 A4 EP 0754350A4 EP 95913778 A EP95913778 A EP 95913778A EP 95913778 A EP95913778 A EP 95913778A EP 0754350 A4 EP0754350 A4 EP 0754350A4
Authority
EP
European Patent Office
Prior art keywords
electronic package
package
cavity
base
leadframe
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP95913778A
Other languages
German (de)
French (fr)
Other versions
EP0754350A1 (en
Inventor
Arvind Parthasarathi
Paul R Hoffman
Dexin Liang
Deepak Mahulikar
Anthony M Pasqualoni
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olin Corp
Original Assignee
Olin Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olin Corp filed Critical Olin Corp
Publication of EP0754350A1 publication Critical patent/EP0754350A1/en
Publication of EP0754350A4 publication Critical patent/EP0754350A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • H01L23/295Organic, e.g. plastic containing a filler
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01012Magnesium [Mg]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16151Cap comprising an aperture, e.g. for pressure control, encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/163Connection portion, e.g. seal
    • H01L2924/16315Shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

There is provided an electronic package (70) where the package components (52, 54) define a cavity (56). A semiconductor device (16) and a portion (18) of a leadframe (20) occupy part of the cavity (56). Substantially the remainder of the cavity (56) is filled with a polymer (26) so that an outermost surface (74) of the polymer (26) is coplanar with a surface (76) of one of the package components (54).

Description


  
 



   CAVITY FILLED METAL ELECTRONIC PACKAGE
 This invention relates to an electronic package for housing at least one semiconductor device. More particularly, by filling the package cavity with a compliant polymer the seal width of an adhesive sealant is reduced. When the package cavity is at least partially filled with a polymer, the requirement of a separate cover component is eliminated. Also, the rigidity of certain of electronic packages is increased.



   Integrated circuit devices, such as silicon based semiconductor circuits, are encased within a package to protect the device from mechanical shock.



  The packages are manufactured from a variety of materials, such as plastics, ceramics and metals.



   U. S. Patent No. 4,939,316 to Mahulikar et al discloses an anodized aluminum alloy base and cover defining a cavity. A leadframe is disposed between the base and cover and bonded to both by an adhesive seal ring. An integrated circuit device is electrically interconnected to the leadframe and encased within the cavity. The assembled package is light weight, durable and efficiently dissipates heat generated by the device.



   The aluminum alloy package components have a coefficient of thermal expansion significantly lower than the adhesive sealants, typically an epoxy, used to seal the package. When the packages are heated, thermally generated mechanical stresses can cause delamination between the leadframe and the adhesive.



  As the packages are heated or cooled, air trapped within the package cavity expands and contracts.



  The cavity has a fixed volume so the expansion and contraction of the trapped air is compensated as changes in air pressure. The pressure changes apply  a stress on the seal ring which could eventually lead to delamination.   




   Seal ring delamination results in a gross leak    failure. One way to identify gross leak failure is by immersing the package in an inert liquid fluorocarbon heated to 125 C typically for about 1 minute. A stream of bubbles emanating from the package indicates seal delamination and a passageway to the package cavity. Water vapor and other contaminants can enter the package cavity leading to corrosion of the device or electric circuitry.



   One method to prevent seal delamination is to increase the width of the seal path. This solution is contrary to a primary electronic package manufacturing objective, namely to maximize the area available within the package cavity for housing the electronic device-. One continuing goal of electronic packaging is to encapsulate the largest device possible within a given package outline.



   As discussed below, Applicants increase the area available for the semiconductor device by filling the package cavity with a compliant polymer, such as a silicone gel. In U. S. Patent No.



  4,961,106 to Butt et al a package cavity is filled with a fluid or gel having good thermal conductivity, such as helium or hydrogen gas and silicone or silicate gels.



   U. S. Patent No. 5,060,114 to Feinberg et al discloses a conformable gel pad inserted within the cavity of a package. The gel pad has a compressible matrix made from silicone or polyurethane with a thermally conductive material dispersed throughout.  



   "Glop topping"is utilized in molded plastic packages as disclosed in U. S. Patent No. 4,965,227 to Chang et al. The package cavity is filled with a soft gel, for example silicone, to provide environmental protection. The glop top is used in molded packages because the molding resin is permeable to moisture. The glop top prevents corrosion of package components by inhibiting moisture diffusion.



   While the addition of a compliant polymer to a package cavity has been disclosed for improving thermal conductivity and for providing a moisture barrier, compliant polymers have not, until now, been used to reduce the seal path width thereby increasing the size of the electronic device which can be encapsulated within a fixed package outline.



   Additionally, the polymers have not been used to eliminate the need for a separate cover component in electronic packages having a discrete base component. Further, the use of the polymers to increase the rigidity of a metallic package has not been recognized.



   Accordingly, it is a first object of the invention to provide an electronic package having an adhesive seal ring with a reduced width. A second object of the invention is to provide an electronic package in which the cavity defined by a base component and window frame is filled with a polymer such that a discrete cover component is not required. A further object of the invention is to provide an electronic package having metallic base and cover components with increased rigidity.  



   It is a feature of the invention that the package cavity is filled with a compliant polymer to prevent the ingress of contaminants. It is a benefit of the invention that larger integrated circuit devices or multiple devices can be housed within a fixed package outline. It is a further benefit of the invention that the cavity is essentially contaminant free, facilitating the use of aluminum based bond wires rather than gold based bond wires. By filling the package cavity with a gel, the bond wires are held firmly in place. The bond wires do not move during mechanical shock or vibration reducing the chance of adjacent wires touching and creating an electrical short circuit.



  Also, vibration of the bond wires can cause the wire to work harden, become brittle and break.



   Yet another benefit of the invention is that thermoplastic polymer sealants may be used in addition to thermosetting adhesives to assemble the package. By sealing the package lid with a thermoplastic adhesive, a sealed package may be subsequently opened for replacement or repair. As another benefit of the invention, the compliant gel may be selected to be ultraviolet light transparent and the package sealed with a W transmitting glass lid for a package to house an erasable-programmable (EPROM) device.



   In accordance with the invention there is provided an adhesively sealed electronic package.



  The package has a base and a cover defining a cavity. A leadframe electrically interconnected to an integrated circuit device is disposed between the base and cover with the device and a portion of the  leadframe positioned within the cavity. A compliant polymer fills substantially the remainder of the cavity. An adhesive having a reduced seal width bonds the leadframe to both the base and to the cover.



   In accordance with a second embodiment of the invention, there is provided an electronic package having a base and a window frame defining a. cavity.



  A leadframe is disposed between and bonded to both the base and to the window frame with a first adhesive. A semiconductor device is electrically interconnected to the leadframe such that the device and a portion of the leadframe occupy a portion of the cavity defined by the base and the window frame.



  A polymer occupies substantially the remainder of the cavity.



   In accordance with yet another embodiment of the invention, there is provided an electronic package having a base and a cover defining a cavity.



  A leadframe is disposed between and bonded to both the base and the cover with a first adhesive. A semiconductor device is electrically interconnected to the leadframe and the device and a portion of the leadframe occupy a portion of said cavity defined by the base and cover. A second adhesive is disposed within the cavity and bonds the semiconductor device to the cover.



   The objects, features and benefits described above will become more apparent from the specification and drawings which follow.  



   Figure 1 shows in cross sectional representation an adhesively sealed metal package as known from the prior art.



   Figure 2 shows in cross sectional representation an adhesively sealed metal package in accordance with a first embodiment of the invention.



   Figure 3 shows in cross sectional representation an adhesively sealed window frame package in accordance with a second embodiment of the invention.



   Figure 4 shows in cross sectional representation a cavity filled window frame package in accordance with an embodiment of the invention.



   Figure 5 shows in cross sectional representation the window frame package of claim 4 further including a die attach paddle.



   Figure 6 shows in cross sectional representation a thin metallic electronic package having increased rigidity in accordance with another embodiment of the invention.



   Figure 7 shows in cross sectional representation an embodiment of the electronic package of Figure 6 in which the bond wires are partially insulated to prevent contact with the metallic cover.



   Figure 1 shows in cross sectional representation a metal electronic package 10 as known from the prior art. The package 10 has a metallic base 12 and a cover 14. The cover 14 is typically formed from the same material as the base 12. To maximize thermal conductivity and minimize package weight, the base 12 and cover 14 can be manufactured from aluminum or an aluminum alloy.  



  One suitable aluminum alloy is designated by the
American Society of Metals (ASM) as A3003 and has the nominal composition by weight of 0.12% copper, 1.2% manganese and the balance aluminum. A3003 can be imparted with a black color by integral color anodization as disclosed in U. S. Patent No.



  5,066,368 to Pasqualoni et al.



   An electronic device 16 is electrically interconnected to the inner leads 18 of a leadframe 20. A first adhesive 22 bonds the leadframe 20 to both the base 12 and to the cover 14. Tenacious adhesion between the first adhesive 22 and the other package components is required to withstand the stresses generated by the coefficient of thermal expansion mismatch between the package components and the adhesive as well as by variations in the pressure of the air trapped within the package cavity 24. To prevent gross leak failures, the first adhesive is selected to be a strongly adherent thermosetting polymer such as an epoxy.



   The peripheral dimension of the package 10, designated"D", is dictated by the available space on a printed circuit board (not shown). This space is limited and due to the trend in the electronics industry for standardization,"D"is usually fixed.



  The maximum size of the device 16 is limited by the size of the cavity 24. The only way to increase the size of the cavity 24 is to reduce the seal width, designated"W". However, when"W"is reduced below a critical value, the mechanical stress on the adhesive induced by the combination of thermal expansion mismatch and the cavity pressure variations causes seal delamination. When the base  12 and cover 14 are an aluminum alloy, the leadframe unplated copper and the sealant a novalac based epoxy, this critical value is about 3.8mm (0.15 * inches).



   Figure 2 illustrates in cross sectional representation an electronic package 30 in accordance with the invention. The package 30 has a base 12 and a cover 14. While both the base 12 and the cover 14 may be manufactured from any suitable material, such as a plastic, ceramic, metal or composite, metals are preferred. Aluminum and aluminum alloys are most preferred due to the low weight and good thermal conductivity of the metals.



  Portions of the base 12 and cover 14 may be anodized to increase corrosion resistance and to improve adhesion to the first adhesive 22. It is most preferred that the base 12 and cover 14 be formed from aluminum alloys of the ASM 3xxx and 6xxx series. 3xxx series aluminum alloys contain up to about 1.5% by weight manganese along with other alloying elements while 6xxx alloys contain magnesium and silicon in an approximate proportion to form Mg2Si. Both alloy series are capable of forming a gray to black color by integral color anodization.



   The package 30 has a reduced seal width designated"RW". As used throughout the specification and claims herein,"RW", or reduced seal width, means a seal ring width less than the critical value. The seal ring width is less than the width required to prevent thermally induced and pressure variation induced adhesive delamination in a package having an unfilled cavity. Since the  peripheral dimension"D"does not change, reducing the seal width"RW"increases the area of the cavity 24. The mechanism by which"W"may be decreased to "RW"is by filling the cavity 24 with a compliant polymer 26.



   Disposed between the base 12 and cover 14 is a leadframe 20. The leadframe is usually manufactured from copper or a copper alloy to maximize electrical conductivity. An integrated circuit device 16 is electrically interconnected to inner lead portions 18 of the leadframe 20. Electrical interconnection may be by means of thin bond wires 28 or thin copper foil strips (not shown) as used in tape automated bonding (TAB). The thin bond wires may be manufactured from any suitable metal such as gold, aluminum, copper or alloys thereof. The bond wires are protected from environmental corrosion by the compliant polymer 26 so it is not necessary to use expensive gold based bond wires. Similarly, it is not necessary to coat the TAB leads with gold or another barrier layer when the compliant polymer 26 is utilized.



   The reliability of the bond wires 28 is further protected by the compliant polymer 26 by being held rigidly in place. The bond wires do not move due to mechanical shock or vibration. Movement of the wires may cause two bond wires to touch creating an electrical short circuit. Vibration can work harden a wire causing the wire to become brittle and break. The compliant polymer yields when stressed so there is not the problem of bond wire breakage due to coefficient of thermal expansion mismatch as occurs in molded plastic  packages such as PDIPs (plastic dual in line packages) and PQFPs (plastic quad flat packages).



   The integrated circuit device 16 may be free floating within the cavity 24 or bonded to the package base 12 by a compliant adhesive 31. For ease of assembly, the integrated circuit device 16 is usually bonded to a die attach paddle 32. That portion of leadframe 20 which includes the inner leads 18 and die attach paddle 32 as well as the semiconductor device 16 occupies a portion of the cavity 24. The first adhesive 22 bonds the leadframe 20 to both the base 12 and cavity 24.



   Substantially the remainder of the cavity 24 is occupied by the compliant polymer 26. The compliant polymer 26 may be any suitable material such as a viscous liquid, a gel or a compliant plastic. Gelatinizable materials which are introduced into the cavity 24 in liquid form and subsequently coagulated into a gelatinous solid are preferred. While in the liquid phase, the gelatinizable compliant polymer 26 should have a sufficiently low viscosity to fill all corners and hidden features of the cavity 24. After coagulating to a gel, the viscosity should be sufficiently high to avoid cavity leakage through the seal ring. The coagulated gel should further be chemically inert with respect to the leadframe 20, integrated circuit device 16 and bond wires 28.

   Ideally, the compliant material 26 should have good thermal conductivity to aid in the removal of heat from the integrated circuit device 16. However, in metallic packages good thermal conductivity is not critical because most thermal dissipation is through the base 12.  



   Preferred compliant polymers include liquids, gels and plastics such as gelatinazable silicones, fluorocarbons and epoxies. A most preferred polymer is a gelatinazable silicone manufactured by Dow
Corning, Midland, Michigan.



   The compliant polymer while in the liquid phase is introduced to the cavity 24 through a first vent port 34 by any suitable means such as a large diameter hypodermic needle. Sufficient compliant polymer is introduced to the cavity 24 such that substantially the entire cavity is filled. To remove air displaced from the cavity 24, a second vent port 36 is provided. The compliant polymer is added until there is sufficient compliant polymer that both the first 34 and second 36 vent ports are at least partially filled. The compliant polymer, if gelatinizable, is coagulated into a gel and the vent ports sealed.



   Once the cavity 24 is filled with the gel, seal ring delamination is not a problem.



  Delamination is less likely because the air in the package has been displaced. The pressure variation induced stress on the first adhesive 22 during package heating and cooling has been eliminated.



  Beneficially, should a portion of the first adhesive 22 delaminate, the result is not a gross leak failure. The flow of contaminants into the package cavity 24 is inhibited by the compliant polymer 26.



  Contaminants are unable to reach bond wires 28 or semiconductor device 16.



   One additional benefit realized is that because the bond wires 28 are fully protected from chlorides and other contaminants, aluminum or  aluminum alloy bond wires may be utilized rather than the more chemically inert, but much more costly gold or gold alloys.



   A second additional benefit which is realized is that the adhesive strength of the first adhesive 22 is less critical. When the package cavity is not filled, or only partially filled, any delamination of the first adhesive 22 leads to a gross leak failure. When the package cavity 24 is substantially filled, in accordance with the invention, delamination can be tolerated. The primary function of the first adhesive 22 changes from maintaining package hermeticity to merely holding the package components together. As a result, rather than a tenacious adhesive such as an epoxy being required, less tenacious adhesives such as thermoplastic polymer may be utilized.



   Suitable thermoplastic polymers include those commonly referred to as"Hot-Melt"Adhesives. These adhesives, with the addition of suitable fillers, will remain solid up to about 175 C and can withstand momentary exposure to higher temperatures the package may achieve during soldering to a printed circuit board. As the temperature is increased above the melting temperature, the adhesives rapidly melt to a low viscosity fluid which rapidly sets when the temperature is lowered again. Because the adhesives are thermoplastic, the melting/resolidification process is repeatable. Hot melt adhesives include ethylene and vinyl acetate copolymers (EVA), polyvinyl acetate (PVA), polyethylene, amorphous polypropylene, block copolymers such as those based on styrene and  elastomeric segments or ether and amide segments (ie. thermoplastic elastomers), polyamides and polyesters.

   EVA is one preferred hot melt adhesive.



   A primary advantage of using a thermoplastic polymer as the first adhesive 22 is that the package can be reopened after sealing to perform device repair or replacement. Repair is not possible with a thermosetting polymer such as an epoxy.



   Figure 3 illustrates in cross sectional representation a window frame package 50 in accordance with the invention. The package has a base which may be a metal plate 52, optionally containing a depressed central region for receiving the semiconductor device. The metallic plate 52 may be manufactured from any suitable material and is preferably metallic, and most preferably aluminum or an aluminum alloy. The leadframe 20 with an electrically interconnected semiconductor device 16 is disposed between the metallic plate 52 and a window frame 54. A first adhesive 22 bonds the leadframe 20 to both metallic plate 52 and the window frame 54. The window frame 54 is manufactured from a suitable material, such as plastic, metal or ceramic. Preferably, the window frame 54 has a coefficient of thermal expansion about equal to that of metallic plate 52.

   Most preferably, the window frame 54 is manufactured from the same material as the metallic base plate 52.



   After bonding the leadframe and electrically interconnecting the semiconductor device 16, the metallic plate 52 and window frame 54 define a cavity 56. The cavity 56 is filled with a compliant polymer 26 up to the sealing surface 58 of the  window frame 54. Because the center of the window frame 54 is a large aperture, introduction of the compliant material may be by any suitable means such as injection from a small diameter tube. After the compliant polymer coagulates to a gel, a cover 60 is bonded to the seal surface 58 by a lidding adhesive 62. The lidding adhesive 62 is any suitable material such as a thermosetting polymer, a thermoplastic polymer or a solder. A thermoplastic polymer such as the hot melt adhesives (ie EVA) is preferred so that the cover 60 is removable. The cover 60 may be any suitable material such as a plastic, glass, ceramic or metal.

   To prevent thermally induced flexure of the package, in one preferred embodiment, the cover 60 is manufactured from the same material as the metallic plate 52.



   In a second embodiment of the invention, the cover 60 is selected to be a glass capable of transmitting a certain wavelength of electromagnetic radiation. Exposure of certain devices to electromagnetic radiation erases the device memory, these devices are commonly referred to as EPROM devices. A preferred cover would be capable of transmitting ultraviolet (W) light. One UV transparent cover is quartz (silicon dioxide). The selected compliant polymer should also be transparent to W radiation. This package is superior to other EPROM packages. By filling the package cavity with the compliant polymer, changes in temperature and the corresponding pressure changes will not flex the glass cover which may distort the W light path. The cover can be sealed  with a thermoplastic adhesive permitting replacement in the event the glass is scratched.



   The window frame package 50 of Figure 3 can encapsulate a larger semiconductor device 16 or a plurality of devices within a fixed package profile than was possible with prior art packages. The coagulated compliant polymer mitigates the destructive effect of delamination. The bond wires 28 may be manufactured from a less inert material than gold and the cover 14 may be sealed with a removable lidding adhesive 62 such as a thermosetting polymer.



   In another embodiment of the invention, the cover 60 can be omitted. With reference to Figure 4, a window frame package 70 has a base 52 and a window frame 54 defining a cavity 56. A leadframe 20 is bonded to both the base 52 and a first surface 72 of the window frame 54. Typically, the leadframe is bonded with a first adhesive 22, such as a thermosetting epoxy.



   A semiconductor device 16 is bonded to a central portion of the base 52. Bond wires 28 electrically interconnect the leadframe 20 to the semiconductor device 16. A portion of the cavity 56 is therefore occupied by the combination of the inner leads 18 of the leadframe 20, the bond wires 28 and the semiconductor device 16. Substantially the remainder of the cavity 56 is filled with a polymer 26. The polymer 26 fills the cavity 56 to sufficient height that the outermost surface 74 of the polymer 26 is substantially coplanar with the second surface 76 of the window frame. The combination of the outermost surface 74 and second  surface 76 form the top surface of the electronic package 70.



   While any polymer satisfying the requirements detailed above is suitable for this embodiment of the invention, namely, initially the polymer has a low viscosity to fill the package cavity 56 and the viscosity subsequently increases during a cure, epoxy potting compounds are preferred. The epoxies are more rigid after curing than silicones or similar materials and better resist deformation or penetration.



   Preferably, the polymer 26 is filled with a thermally conducting, electrically insulating material, such as silicon nitride, to enhance the dissipation of heat from the semiconductor device 16. Additionally, the polymer 26 preferably has a black color to enhance the absorption of infrared radiation during soldering of the outer portions of the leadframe 20.



   Figure 5 illustrates in cross sectional representation, another electronic package 80 of the invention. This package is similar to the electronic package 70 illustrated in Figure 4, but further includes a die attach paddle 82. The die attach paddle 82 is generally formed from the same material as the leadframe 20, typically copper or a copper alloy, and is located within the aperture defined by the inner leads 18. The semiconductor device 16 is bonded to the die attach paddle 82 by a die attach adhesive 84. Following electrical interconnection to the inner leads 18, the device/leadframe assembly is bonded to the package base 12 by pad attach adhesive 31. Preferably, the  pad attach adhesive is cured at essentially the same time as the leadframe 20 is bonded to the base 12 and first surface 72 of the window frame 54.

   The cavity 56 defined by the base 12 and window frame 54 is then filled with a polymer 26, such as an epoxy, such that the outermost surface of the polymer 26 and the second surface 76 of the window frame 54 define the package 80 cover.



   An ongoing goal of electronic packages is to reduce the thickness of the package. A target thickness is a maximum of 1.4mm (0.055 inch). This target thickness requires the package base and cover to have a thickness, in the region overlying or underlying the semiconductor device, of at most about. 25mm (0.01 inch). When the base and cover are formed from metal, the thin package is susceptible to deflection. Exposure of the package to temperature variations, either during assembly or during use, leads to changes in the air pressure within the package cavity. Rather than these pressure changes leading to a gross leak through the first adhesive as occurs with conventional packages, in the thin packages, these pressure excursions are manifest as inward and outward deflection of the base and cover.

   Outward deflection can cause the base (or cover in a cavity down format) to contact a printed circuit board. Inward deflection can cause the lid to contact the bond wires.



   The magnitude of deflection is highly dependent on the cavity size. The larger the cavity, the more severe the problem. Since increasing the cavity volume for a given package outline is a primary packaging goal, for thin metal  packages to be successful, the rigidity must be increased.



   Figure 6 illustrates in cross sectional representation a metal electronic package 90 having increased rigidity. The package has a metallic base 12 and cover 14. While the cover may be any material, preferably the cover has a coefficient of thermal expansion about equal to that of the base to prevent flexure of the package during heating and cooling. Preferably the base and cover are formed from copper, aluminum or alloys thereof, and most preferably from an aluminum alloy coated with an anodization layer.



   A leadframe 20 is bonded to the base 12 and cover 14 by a first adhesive 22. The base 12 and the cover 14 define a cavity 24. A semiconductor device 16 is bonded to the base 12, either directly, or by means of a die attach paddle 32. The semiconductor device 16 is also bonded to the package cover 14 by a second adhesive 92. The second adhesive is any suitable polymer adhesive which is electrically non-conducting to avoid creating an electrical short circuit on the electrically active face of the semiconductor device 16. Also, the second adhesive should be noncorrosive to the electrically active face. A preferred polymer adhesive is an epoxy potting compound.



   A controlled volume of the second adhesive is dispense onto the semiconductor device prior to cover 14 sealing. The cover contacts the second adhesive 92 during sealing and is bonded both to the leadframe 20 by means of the first adhesive 22 and  to the semiconductor device 16 by means of the second adhesive 92.



   To egress the reaction products of the polymer cure, a vent hole 94 is provided. Since the central portion of the base 12 and cover 14 is quite thin, the vent hole is positioned over a thicker peripheral portion to facilitate assembly and sealing. The vent hole can be sealed with a drop of a polymer adhesive.



   The electronic package 90 of Figure 6 eliminates deflection of the package base and cover by forming a rigid beam through the center of the package. However, due to the reduced thickness, the bond wires 28 are close to the cover 14. Contact with the cover could cause an electrical short circuit or cause a bond wire to deflect against an adjoining bond wire or break. These problems are eliminated by the embodiment illustrated in Figure 7. The package 100, illustrated in cross-sectional representation in Figure 7, has the same features as the package 90 of Figure 6, except that the second adhesive 92 extends beyond the perimeter of the semiconductor device 16 and encapsulates the apex 102 of the loop formed by wire bond 28. Preferably, the second adhesive encapsulates the entire wire bond 28, terminating somewhat past the point where the wire bond is joined to the inner lead 18. 

   With this embodiment, the wire bonds are protected from corrosion, deflection and permanently electrically isolated from the cover 14.



   The advantage of the electronic package of the invention will become more apparent from the Example  which follows. The Example is intended to be exemplary and not limiting.



   EXAMPLE
 A series of metal electronic package were assembled with a novalac based epoxy film seal ring of a width as specified in Table 1. The packages had 28mm x 28mm (1.1 inch x 1.1 inch) anodized aluminum base and cover components sealed to a 208 lead copper lead frame. The assembled packages were placed in a pressure cooker at 121 C, 100% relative humidity for 200 hours and then tested for gross leaks. As shown in Table 1, the packages had a critical value of about 3.8mm (. 150 inches).



   Table 1
Seal Ring Width Gross leak Results
 Failures/Parts Tested 1.27mm (. 050 in.) 8/8 1.91mm (. 075 in.) 7/8 2.54mm (. 100 in.) 8/8 3.18mm (. 125 in.) 6/8 3.81mm (. 150 in.) 0/8
 By filling the package cavity with the compliant polymer in accordance with the invention, gross leak failures were eliminated permitting the assembly of packages with a seal ring width of less than 2.54mm.



   To illustrate the advantage of reducing the seal ring width, the portion of the exemplary bases (unfilled cavity), seal ring dimensions (28mm x 3.81mm Outside dimension; 20.4mm x 3.81mm Inside  dimension) available for mounting a semiconductor device is:
Area of Base Area of Seal Ring = Available Area
 (1) 784mm2-369mm2 415mm2
 By filling the cavity with a compliant polymer in accordance with the invention, the adhesive seal width can be reduced to below about 2.54mm and more preferably to the range of about 1.25mm to about 2. Omm. At the upper end of the preferred range, seal width of 2. Omm, the area available for mounting the semiconductor device is:
 (2) 784mm2-246mm2 538mm2
 an increase of 123mm2 or about 30% more area available for mounting the semiconductor device.



   It is apparent that there has been provided in accordance with this invention an adhesively sealed electronic package having a reduced seal ring width which fully satisfies the objects, means and advantages set forth herein above. While the invention has been described in combination with the embodiments thereof. It is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, it is intended to embrace all such alternatives, modifications and variations as fall within the spirit and broad scope of the appended claims.
  

Claims

IN THE CLAIMS 1. An electronic package (70), characterized by : a base (52) and a window frame (54) having first (72) and second (76) opposing surfaces defining a cavity (56); a leadframe (20) disposed between said base (52) and said window frame (54); a first adhesive (22) bonding said leadframe (20) both to said base (52) and to said first surface (72) of said window frame (54); a semiconductor device (16) electrically interconnected to said leadframe (20), wherein said semiconductor device (16) and a portion (18) of said leadframe (20) occupy a portion of said cavity (56); and a polymer (26) occupying substantially the remainder of said cavity (56) wherein an outermost surface (74) of said polymer (26) is substantially coplanar with said second surface (76) of said window frame (54).
2. The electronic package (70) of claim 1 characterized in that said polymer (26) is selected from the group consisting of viscous liquids, gels and compliant plastics.
3. The electronic package (70) of claim 2 characterized in that said polymer (26) is an epoxy.
4. The electronic package (70) of claim 3 characterized in that said epoxy (26) is filled with a thermal conductive, electrically insulating material.
5. The electronic package (70) of claim 4 characterized in that said base (52) and said window frame (54) are both formed from an aluminum alloy and at least partially coated with an anodization layer.
6. An electronic package (90,100), characterized by: a base (12) and a cover (14) defining a cavity (24); a leadframe (20) disposed between said base (12) and said cover (14); a first adhesive (22) bonding said leadframe (20) both to said base (12) and to said cover (14); an adhesive 31 bonding a semiconductor device (16) to said base (12), said semiconductor device (16) electrically interconnected to said leadframe (20), wherein said semiconductor device (16) and a portion (18) of said leadframe (20) occupy a portion of said cavity (24); and a second adhesive (92) disposed within said cavity (24) bonding the semiconductor device (16) to the cover (14) forming a rigid beam through the center of said package (90,100).
7. The electronic package (90,100) of claim 6 characterized in that a vent hole (94) extends through a peripheral portion of said cover (14).
8. The electronic package (90,100) of claim 7 characterized in that said second adhesive (92) is an epoxy.
9. The electronic package (90,100) of claim 7 characterized in that said second adhesive (92) extends over at least a portion of one face of said semiconductor device (16).
10. The electronic package (90,100) of claim 9 characterized in that said second adhesive (92) extends beyond the perimeter of said semiconductor device (16) and encapsulates a bond wire (28) electrically interconnecting said semiconductor device (16) to said leadframe (20) through the apex (102) of the loop formed by said wire bonds (28) terminating at a point where the wire bond (28) is joined to the inner lead (18).
11. The electronic package (90,100) of claim 10 characterized in that said second adhesive (92) extends to encapsulate said portion (18) of said leadframe (20).
12. The electronic package (90,100) of claim 11 characterized in that the thickness of said electronic package (90,100) is less than or equal to about 1.4mm.
13. The electronic package (90,100) of claim 12 characterized in that the thickness of the portion of said base (12) underlying said semiconductor device (16) is less than or equal to about 0.25mm.
14. The electronic package (90,100) of claim 12 characterized in that said base (12) and said cover (14) are both formed from an aluminum alloy and at least partially coated with an anodization layer.
EP95913778A 1994-04-05 1995-03-20 Cavity filled metal electronic package Withdrawn EP0754350A4 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US22320794A 1994-04-05 1994-04-05
US223207 1994-04-05
PCT/US1995/003468 WO1995027308A1 (en) 1994-04-05 1995-03-20 Cavity filled metal electronic package

Publications (2)

Publication Number Publication Date
EP0754350A1 EP0754350A1 (en) 1997-01-22
EP0754350A4 true EP0754350A4 (en) 1998-10-07

Family

ID=22835525

Family Applications (1)

Application Number Title Priority Date Filing Date
EP95913778A Withdrawn EP0754350A4 (en) 1994-04-05 1995-03-20 Cavity filled metal electronic package

Country Status (5)

Country Link
EP (1) EP0754350A4 (en)
JP (1) JPH09511617A (en)
AU (1) AU2103895A (en)
TW (1) TW358238B (en)
WO (1) WO1995027308A1 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6731001B2 (en) 2000-08-10 2004-05-04 Denso Corporation Semiconductor device including bonded wire based to electronic part and method for manufacturing the same
JP4151207B2 (en) * 2000-08-10 2008-09-17 株式会社デンソー Semiconductor device
US6782745B1 (en) * 2003-02-21 2004-08-31 Visteon Global Technologies, Inc. Slosh supressor and heat sink
US7157793B2 (en) * 2003-11-12 2007-01-02 U.S. Monolithics, L.L.C. Direct contact semiconductor cooling
US9112422B1 (en) 2010-03-09 2015-08-18 Vlt, Inc. Fault tolerant power converter
US8966747B2 (en) * 2011-05-11 2015-03-03 Vlt, Inc. Method of forming an electrical contact
US9402319B2 (en) 2011-05-11 2016-07-26 Vlt, Inc. Panel-molded electronic assemblies
JP6268086B2 (en) * 2012-06-15 2018-01-24 株式会社カネカ Heat dissipation structure
US9936580B1 (en) 2015-01-14 2018-04-03 Vlt, Inc. Method of forming an electrical connection to an electronic module
US9967984B1 (en) 2015-01-14 2018-05-08 Vlt, Inc. Power adapter packaging
US10264664B1 (en) 2015-06-04 2019-04-16 Vlt, Inc. Method of electrically interconnecting circuit assemblies
US10903734B1 (en) 2016-04-05 2021-01-26 Vicor Corporation Delivering power to semiconductor loads
US10158357B1 (en) 2016-04-05 2018-12-18 Vlt, Inc. Method and apparatus for delivering power to semiconductors

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0421005A2 (en) * 1988-02-10 1991-04-10 Olin Corporation Process of assembling an electronic package
US5134462A (en) * 1990-08-27 1992-07-28 Motorola, Inc. Flexible film chip carrier having a flexible film substrate and means for maintaining planarity of the substrate
WO1992020096A1 (en) * 1991-05-06 1992-11-12 Sensonor A.S Arrangement for encasing a functional device, and a process for the production of same
WO1994009512A1 (en) * 1992-10-13 1994-04-28 Olin Corporation Metal electronic package with reduced seal width

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2502511B2 (en) * 1986-02-06 1996-05-29 日立マクセル株式会社 Method for manufacturing semiconductor device
US5098864A (en) * 1989-11-29 1992-03-24 Olin Corporation Process for manufacturing a metal pin grid array package
JP2827684B2 (en) * 1992-03-17 1998-11-25 日本電気株式会社 Semiconductor device
US5239131A (en) * 1992-07-13 1993-08-24 Olin Corporation Electronic package having controlled epoxy flow

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0421005A2 (en) * 1988-02-10 1991-04-10 Olin Corporation Process of assembling an electronic package
US5134462A (en) * 1990-08-27 1992-07-28 Motorola, Inc. Flexible film chip carrier having a flexible film substrate and means for maintaining planarity of the substrate
WO1992020096A1 (en) * 1991-05-06 1992-11-12 Sensonor A.S Arrangement for encasing a functional device, and a process for the production of same
WO1994009512A1 (en) * 1992-10-13 1994-04-28 Olin Corporation Metal electronic package with reduced seal width

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
HOFFMAN P ET AL: "DEVELOPMENT OF A HIGH PERFORMANCE TQFP PACKAGE", 1 May 1994, PROCEEDINGS OF THE ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, WASHINGTON, MAY 1 - 4, 1994, NR. CONF. 44, PAGE(S) 57 - 62, INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, XP000479146 *
See also references of WO9527308A1 *

Also Published As

Publication number Publication date
TW358238B (en) 1999-05-11
EP0754350A1 (en) 1997-01-22
JPH09511617A (en) 1997-11-18
WO1995027308A1 (en) 1995-10-12
AU2103895A (en) 1995-10-23

Similar Documents

Publication Publication Date Title
US5324888A (en) Metal electronic package with reduced seal width
US5458716A (en) Methods for manufacturing a thermally enhanced molded cavity package having a parallel lid
EP0421005B1 (en) Process of assembling an electronic package
US8039945B2 (en) Plastic electronic component package
US4594770A (en) Method of making semiconductor casing
US5122858A (en) Lead frame having polymer coated surface portions
CA1200923A (en) Semiconductor packages
US5650663A (en) Electronic package with improved thermal properties
US5477008A (en) Polymer plug for electronic packages
AU2002310466B2 (en) Use of diverse materials in air-cavity packaging of electronic devices
US5243756A (en) Integrated circuit protection by liquid encapsulation
EP0658935A2 (en) Resin sealing type semiconductor device and method of making the same
EP0754350A1 (en) Cavity filled metal electronic package
US5441918A (en) Method of making integrated circuit die package
AU1747492A (en) Arrangement for encasing a functional device, and a process for the production of same
WO1993018546A1 (en) Molded ring integrated circuit package
AU2002310466A1 (en) Use of diverse materials in air-cavity packaging of electronic devices
US5568684A (en) Method of encapsulating an electronic device
EP0645812B1 (en) Resin-sealed semiconductor device
JPH06224314A (en) Semiconductor device
US20030042598A1 (en) Hermetic seal
KR0168841B1 (en) Metal electronic package and the manufacture method
CA1304172C (en) Metal electronic package
JPH03234044A (en) Method of assembling package and package
JPH08148645A (en) Resin-sealed semiconductor device

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19961004

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE GB

A4 Supplementary search report drawn up and despatched

Effective date: 19980820

AK Designated contracting states

Kind code of ref document: A4

Designated state(s): DE GB

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19981001