EP0748055A2 - Method for decoding data blocks received by a RDS receiver - Google Patents

Method for decoding data blocks received by a RDS receiver Download PDF

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Publication number
EP0748055A2
EP0748055A2 EP96106156A EP96106156A EP0748055A2 EP 0748055 A2 EP0748055 A2 EP 0748055A2 EP 96106156 A EP96106156 A EP 96106156A EP 96106156 A EP96106156 A EP 96106156A EP 0748055 A2 EP0748055 A2 EP 0748055A2
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Prior art keywords
stage
bits
data block
output
input
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EP96106156A
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German (de)
French (fr)
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EP0748055B1 (en
EP0748055A3 (en
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Detlev Dipl.-Mathematiker Nyenhuis
Wilhelm Dipl.-Phys. Hegler
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Blaupunkt Werke GmbH
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Blaupunkt Werke GmbH
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H40/00—Arrangements specially adapted for receiving broadcast information
    • H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H60/00—Arrangements for broadcast applications with a direct linking to broadcast information or broadcast space-time; Broadcast-related systems
    • H04H60/27—Arrangements for recording or accumulating broadcast information or broadcast-related information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H2201/00—Aspects of broadcast communication
    • H04H2201/10—Aspects of broadcast communication characterised by the type of broadcast system
    • H04H2201/13—Aspects of broadcast communication characterised by the type of broadcast system radio data system/radio broadcast data system [RDS/RBDS]

Definitions

  • the object of the property right is a method for decoding data blocks received with an RDS receiver according to the preamble of claim 1 and a circuit arrangement suitable for carrying out this method according to the preamble of claim 3.
  • Receivers for the radio data system are defined in DIN EN 50 067.
  • the structure of an RDS receiver connected to the MPX output of a conventional radio receiver is shown as a block diagram on page 5 in figure 2 and an embodiment of a decoder in the data processor of the RDS receiver is shown on page 34 in figure B 4 and explains how it works.
  • the method according to the invention differs from the mode of operation of the known also error-correcting decoder, which is covered in the preamble of the main claim, by the features mentioned in the characterizing part of the main claim.
  • the new method offers the advantage of higher security, since the error bits are also detected during the error correction. H. only an error that cannot be corrected - also in the check bits - leads to the rejection of the data.
  • a test word consisting of ten bits is appended to the information word of interest in the receiver, which consists of sixteen bits, and one of six defined offset words, which also consists of ten bits, is superimposed on this. Errors can occur in the bits to be transmitted on the way from the transmitter to the receiver.
  • the known decoder has to recover the information word from the received infinite bit stream.
  • it is designed in such a way that it separates the offset word known to it in the synchronized state from the test word in an X-OR stage and feeds the information word and the test word to a syndrome register for error checking and temporarily stores the bits of the information word. After the error check, the information word which may have been corrected in a further X-OR stage is output.
  • the memory cells for syndrome calculation are linked to one another in such a way that if a code word is received correctly, the syndrome at the end of the block is calculated to be zero.
  • the sixteen information bits are then read from the buffer at a fast clock rate in the period associated with the last bit of the respective block.
  • the content of the syndrome register is circulated in it, in which the links between the memory cells remain effective. If zeros are written into the first five cells of the syndrome register, the circulation of the content in the syndrome register is interrupted and then the content of the syndrome register is read out bit by bit and added to the data stream from the buffer. This may result in an error correction.
  • the syndrome register is reset to zero.
  • the bits received serially by the RDS receiver 1 via a data switch 2 in its I position are read into a 26-bit shift register 3.
  • the content of the shift register 3, controlled by shift clocks V is read out after the data switch 2 is switched to its position II, in which the output of the shift register 3 is connected to its input, so that the content also rotates in the shift register 3.
  • bit clocks T regenerated by the RDS receiver are counted in a bit counter 4, from whose overflow the block clock B can be removed after twenty-six bit clocks.
  • a synchronized state of the decoder is assumed.
  • the output of the shift register 3 is connected to the first input of a first X-OR stage 5, the second input of which is connected to the output of an offset word generator 6.
  • This offset word generator 6 generates the ten bits of the offset word belonging to the block during the readout of the last ten bits of the block stored in the shift register 3.
  • the bits at the output of the first X-OR stage 5 are read into a syndrome register 8 via a blocking stage 7 which is opened during the first reading, in which the syndrome belonging to the code word is calculated.
  • the exact wiring of the syndrome register with the elements of a linking loop 19 for the syndrome calculation and for a possible error correction is explained in detail in DIN EN 50 067 and justified, so that it is assumed to be known here and it is therefore not necessary to explain it in more detail.
  • the output of the first X-OR stage 5 is connected in parallel to the input of the blocking stage 7 to the one input of a second X-OR stage 9, the second input of which is connected to the output of the syndrome register 8, in which a gate circuit 10 is located. which can be released by a NOR gate circuit 11.
  • the bits of the error-free information word can be removed at the output of the second X-OR stage 9 when the shift register 3 is read out a second time.
  • the 26-bit shift register 3 before the first X-OR stage 5 replaces the 16-bit buffer for the information word provided in the known decoder after the first X-OR stage.
  • the readout of the bits from the shift register 3 and the other processes, such as the blocking of the blocking stage 7, is effected by a control unit 12, for the clock unit of which an exemplary embodiment is shown in FIG.
  • the clock unit is explained in more detail with reference to FIG. 2.
  • a 114 kHz generator 13 is connected to the input of the clock unit. Its pulses clock a 4-bit counter 14, the overflow of which in turn clocks a 2-bit counter 15. Both counters are cleared by a reset pulse of a 2.37 kHz generator 16 applied to the reset input.
  • the clock unit is constructed such that the 4-bit counter 14 alternately counts to ten or to sixteen. The counting method was controlled by the output of a third X-OR stage 17 in the output of the 2-bit counter 15.
  • the 4-bit counter 14 In the first state (0.0) of the 2-bit counter 15, the 4-bit counter 14 to ten counts. Its overflow switches the 2-bit counter 15 into its second state (1.0). In this state of the 2-bit counter 15, the 4-bit counter 14 to sixteen counts. During this state (1.0) and the third state (1.1) of the 2-bit counter 15, in which the 4-bit counter 14 counts to ten again, a gate circuit 18 is opened, on which a total of twenty-six shift clocks V (sixteen plus ten) appear at a frequency of 114 kHz on the shift clock line V. These shift clocks V control the reading of the shift register 3 and the syndrome register 8. The ten shift clocks V output in the third state (1.1) of the 2-bit counter 15 also control the output of the offset word from the offset word generator 6.
  • the gate circuits 21 and 22 in the input and in the reset input of the clock unit are only opened by the block clock B, which the bit counter 4 supplies. You avoid decoding before the last bit period of a block.
  • the control unit 12 is programmed such that after reading the last bit of a block into the shift register 3, when the block clock B appears, the input of the shift register 3 is separated from the RDS receiver 1 and connected to the output of the shift register 3, and that Syndrome register 8 is cleared; e.g. B. when the 4-bit counter 14 has counted 15 to four in the first state of the 2-bit counter.
  • the contents of the shift register 3 are then read out for the first time with the first packet of 26 shift clocks V. At the same time, the content rotates in shift register 3.
  • the block read in the first X-OR stage 5 is linked to the offset word read out from the offset word generator 6 with the same clock, and the code word is freed from the superimposed offset word.
  • the code word is read into the previously deleted syndrome register 8 via the open blocking stage 7.
  • the associated syndrome is calculated by linking the cells in the known manner, and a possible error correction is prepared in the process.
  • the first readout is followed by a second readout of the shift register during the second cycle of the clock unit.
  • the blocking stage 7 is blocked via the repetition line W and the second X-OR stage 9 is output of the code word released.
  • the deletion of the syndrome register 8 and a switchover of the data switch 2 at the fourth counting cycle are suppressed in the second counting cycle.
  • the blocking of the blocking stage 7 prevents bits from being read into the syndrome register 8 again in the second packet of twenty-six shift clocks. Only that Linking loop 19 in the syndrome register remains closed as long as the loop gate 20 is open.
  • the gate circuit 10 in the output of the syndrome register 8 is released via the NOR gate circuit 11 and at the same time the logic loop 19 in the syndrome register is interrupted by blocking the loop gate 20.
  • those bits which subsequently leave the first X-OR stage 5 are linked bit by bit with the bits read from the syndrome register 8 in the second X-OR stage 9.
  • the syndrome calculation already results in the value zero when it is read out for the first time. That is, there is a zero in all cells of the syndrome register and thus also in the first five cells. Then the gate circuit 10 in the output of the syndrome register is already released by the NOR gate circuit 11 at the beginning of the second packet of twenty-six clock pulses and the loop gate 20 is blocked.
  • the clock unit in the control unit 12 is stopped until the start of the next block cycle.
  • the method according to the invention is not limited to the generator frequencies specified in the exemplary embodiment, these can also be used can be chosen much higher if the program of the data processor in the decoder requires it.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

The method decodes data blocks received in an RDS receiver. The bits allocated to the test word in individual data blocks are combined in a first NOR (5) gate with the bits of the offset value belonging to the data block. Then, error free reception of the data block in a syndrome register is tested and, if necessary, an error correction is carried out. For the error correction, the bits allocated to the information word are temporarily stored for output via a second NOR gate (9). All received bits of the data block are first read into a temporary memory (3) connected in front of the first NOR gate (5). After storing a complete data block, the bits are read out from the temporary memory (3) during the last bit period of the data block. The first read out is done via the first NOR gate (5) into the syndrome register (8). On the second read out the input of the syndrome register (8) is locked by a blocking stage (7). The code word released in the first NOR gate (5) from superimposed offset values is output directly to the second NOR gate (9).

Description

Gegenstand des Schutzrechts ist ein Verfahren zur Decodierung von mit einem RDS-Empfänger empfangenen Datenblöcken gemäß dem Oberbegriff des Anspruchs 1 und eine zur Durchführung dieses Verfahrens geeignete Schaltungsanordnung gemäß dem Oberbegriff des Anspruchs 3.The object of the property right is a method for decoding data blocks received with an RDS receiver according to the preamble of claim 1 and a circuit arrangement suitable for carrying out this method according to the preamble of claim 3.

Empfänger für das Radio-Daten-System (RDS) sind in der DIN EN 50 067 definiert. In der Unterlage dieser Norm ist auf Seite 5 im Bild 2 die Struktur eines an den MPX-Ausgang eines üblichen Rundfunkempfängers angeschlossenen RDS-Empfängers als Blockschaltbild gezeigt und auf Seite 34 im Bild B 4 ein Ausführungsbeispiel eines Decoders in dem Datenprozessor des RDS-Empfängers dargestellt und dessen Arbeitsweise erläutert.Receivers for the radio data system (RDS) are defined in DIN EN 50 067. In the document of this standard, the structure of an RDS receiver connected to the MPX output of a conventional radio receiver is shown as a block diagram on page 5 in figure 2 and an embodiment of a decoder in the data processor of the RDS receiver is shown on page 34 in figure B 4 and explains how it works.

Von der Arbeitsweise des bekannten auch fehlerkorrigierenden Decoders, die in dem Oberbegriff des Hauptanspruchs erfaßt ist, unterscheidet sich das erfindungsgemäße Verfahren durch die im Kennzeichen des Hauptanspruchs genannten Merkmale.The method according to the invention differs from the mode of operation of the known also error-correcting decoder, which is covered in the preamble of the main claim, by the features mentioned in the characterizing part of the main claim.

Das neue Verfahren bietet den Vorteil höherer Sicherheit, da bei der Fehlerkorrektur auch die Prüfbits erfaßt werden, d. h. erst ein nicht korrigierbarer Fehler - auch in den Prüfbits - führt zur Verwerfung der Daten.The new method offers the advantage of higher security, since the error bits are also detected during the error correction. H. only an error that cannot be corrected - also in the check bits - leads to the rejection of the data.

Zum besseren Verständnis der Erfindung werden zunächst einige Begriffe aus der DIN EN 50 067 und die Arbeitsweise des bekannten Decoders erläutert und danach anhand der Zeichnung der erfindungsgemäße Verfahrensablauf in dem abgewandelten Decoder dargelegt. In der Zeichnung zeigt

Fig. 1
das Blockschaltbild eines neuen Decoders,
Fig. 2
das Blockschaltbild einer Takteinheit in der Steuereinheit für diesen Decoder.
For a better understanding of the invention, a few terms from DIN EN 50 067 and the mode of operation of the known decoder are first explained and then the process sequence according to the invention is explained in the modified decoder on the basis of the drawing. In the drawing shows
Fig. 1
the block diagram of a new decoder,
Fig. 2
the block diagram of a clock unit in the control unit for this decoder.

Nach der DIN EN 50 067 wird auf der Senderseite dem im Empfänger an sich interessierenden Informationswort, das aus sechzehn Bits besteht, ein Prüfwort angehängt, das aus zehn Bits besteht, und diesem eines von sechs definierten Offsetworten überlagert, das ebenfalls aus zehn Bits besteht. Auf dem Weg vom Sender zum Empfänger können in den zu übertragenen Bits Fehler entstehen.According to DIN EN 50 067, a test word consisting of ten bits is appended to the information word of interest in the receiver, which consists of sixteen bits, and one of six defined offset words, which also consists of ten bits, is superimposed on this. Errors can occur in the bits to be transmitted on the way from the transmitter to the receiver.

Im Empfänger muß der bekannte Decoder aus dem empfangenen unendlichen Bitstrom das Informationswort zurückgewinnen. Er ist dazu derart ausgelegt, daß er das ihm im synchronisierten Zustand bekannte Offsetwort in einer X-OR-Stufe von dem Prüfwort trennt und das Informationswort und das Prüfwort einem Syndromregister zur Fehlerprüfung zuführt und die Bits des Informationswortes derweilen zwischenspeichert. Nach der Fehlerprüfung wird das gegebenenfalls in einer weiteren X-OR-Stufe korrigierte Informationswort ausgegeben.In the receiver, the known decoder has to recover the information word from the received infinite bit stream. For this purpose, it is designed in such a way that it separates the offset word known to it in the synchronized state from the test word in an X-OR stage and feeds the information word and the test word to a syndrome register for error checking and temporarily stores the bits of the information word. After the error check, the information word which may have been corrected in a further X-OR stage is output.

In dem Syndromregister sind die Speicherzellen zur Syndromberechnung derart miteinander verknüpft, daß bei fehlerfreiem Empfang eines Codewortes das Syndrom am Blockende zu Null berechnet wird. Danach werden in der dem letzten Bit des jeweiligen Blocks zugehörigen Periode die sechzehn Informationsbit mit schnellem Takt aus dem Zwischenspeicher ausgelesen. Zugleich wird der Inhalt des Syndromregisters in diesem zum Umlauf gebracht, bei dem die Verknüpfungen zwischen den Speicherzellen wirksam bleiben. Werden dabei in die ersten fünf Zellen des Syndromregisters Nullen eingeschrieben, so wird der Umlauf des Inhalts im Syndromregister unterbrochen und danach der Inhalt des Syndromregisters Bit für Bit ausgelesen und zu dem Datenstrom aus dem Zwischenspeicher addiert. Dabei ergibt sich gegebenenfalls eine Fehlerkorrektur.In the syndrome register, the memory cells for syndrome calculation are linked to one another in such a way that if a code word is received correctly, the syndrome at the end of the block is calculated to be zero. The sixteen information bits are then read from the buffer at a fast clock rate in the period associated with the last bit of the respective block. At the same time, the content of the syndrome register is circulated in it, in which the links between the memory cells remain effective. If zeros are written into the first five cells of the syndrome register, the circulation of the content in the syndrome register is interrupted and then the content of the syndrome register is read out bit by bit and added to the data stream from the buffer. This may result in an error correction.

Wird der Inhalt der ersten fünf Zellen nicht Null bevor der Zwischenspeicher ausgelesen ist, so ist entweder ein nichtkorrigierbarer Fehler aufgetreten oder der Fehler liegt in den Prüfbits. Mit Beginn des nächsten Blocks wird das Syndromregister wieder auf Null gesetzt.If the content of the first five cells does not become zero before the buffer is read, either an uncorrectable error has occurred or the error is in the check bits. At the beginning of the next block, the syndrome register is reset to zero.

Im Unterschied hierzu werden in dem Verfahren nach der Erfindung die von dem RDS-Empfänger 1 über einen Datenumschalter 2 in dessen Stellung I seriell empfangenen Bits in ein 26-Bit-Schieberegister 3 eingelesen. Am Ende eines Blocks, wenn alle sechsundzwanzig Bits, die zu einem durch das Offsetwort verschlüsselten Codewort gehören, im Schieberegister 3 gespeichert sind, wird der Inhalt des Schieberegisters 3, gesteuert von Verschiebetakten V, ausgelesen, nachdem der Datenumschalter 2 in seine Stellung II geschaltet ist, in welcher der Ausgang des Schieberegisters 3 mit seinem Eingang verbunden ist, so daß der Inhalt auch im Schieberegister 3 rotiert.In contrast to this, in the method according to the invention the bits received serially by the RDS receiver 1 via a data switch 2 in its I position are read into a 26-bit shift register 3. At the At the end of a block, when all twenty-six bits belonging to a code word encrypted by the offset word are stored in the shift register 3, the content of the shift register 3, controlled by shift clocks V, is read out after the data switch 2 is switched to its position II, in which the output of the shift register 3 is connected to its input, so that the content also rotates in the shift register 3.

Zur Erkennung eines Blockendes werden die von dem RDS-Empfänger regenerierten Bittakte T in einem Bitzähler 4 gezählt, an dessen Überlauf sich nach sechsundzwanzig Bittakten der Blocktakt B abnehmen läßt. Bei der weiteren Beschreibung des Verfahrens wird von einem synchronisierten Zustand des Decoders ausgegangen.To detect the end of a block, the bit clocks T regenerated by the RDS receiver are counted in a bit counter 4, from whose overflow the block clock B can be removed after twenty-six bit clocks. In the further description of the method, a synchronized state of the decoder is assumed.

Der Ausgang des Schieberegisters 3 ist mit dem ersten Eingang einer ersten X-OR-Stufe 5 verbunden, deren zweiter Eingang an den Ausgang eines Offsetwortgenerators 6 angeschlossen ist. Dieser Offsetwortgenerator 6 erzeugt während der Dauer des Auslesens der letzten zehn Bits des im Schieberegister 3 gespeicherten Blocks die zehn Bits des zu dem Block gehörenden Offsetwortes.The output of the shift register 3 is connected to the first input of a first X-OR stage 5, the second input of which is connected to the output of an offset word generator 6. This offset word generator 6 generates the ten bits of the offset word belonging to the block during the readout of the last ten bits of the block stored in the shift register 3.

Über eine beim ersten Auslesen geöffnete Sperrstufe 7 werden die Bits am Ausgang der ersten X-OR-Stufe 5 in ein Syndromregister 8 eingelesen, in dem das zu dem Codewort gehörende Syndrom berechnet wird. Die genaue Beschaltung des Syndromregisters mit den Elementen einer Verknüpfungsschleife 19 für die Syndromberechnung und für eine eventuelle Fehlerkorrektur ist in der DIN EN 50 067 ausführlich erläutert und begründet, so daß sie hier als bekannt vorausgesetzt wird und daher auf ihre nähere Darlegung verzichtet werden kann.The bits at the output of the first X-OR stage 5 are read into a syndrome register 8 via a blocking stage 7 which is opened during the first reading, in which the syndrome belonging to the code word is calculated. The exact wiring of the syndrome register with the elements of a linking loop 19 for the syndrome calculation and for a possible error correction is explained in detail in DIN EN 50 067 and justified, so that it is assumed to be known here and it is therefore not necessary to explain it in more detail.

Der Ausgang der ersten X-OR-Stufe 5 ist parallel zum Eingang der Sperrstufe 7 mit dem einen Eingang einer zweiten X-OR-Stufe 9 verbunden, deren zweiter Eingang an den Ausgang des Syndromregisters 8 angeschlossen ist, in dem eine Torschaltung 10 liegt, die von einer NOR-Torschaltung 11 freigegeben werden kann. An dem Ausgang der zweiten X-OR-Stufe 9 lassen sich beim zweiten Auslesen des Schieberegisters 3 die Bits des fehlerfreien Informationswortes abnehmen.The output of the first X-OR stage 5 is connected in parallel to the input of the blocking stage 7 to the one input of a second X-OR stage 9, the second input of which is connected to the output of the syndrome register 8, in which a gate circuit 10 is located. which can be released by a NOR gate circuit 11. The bits of the error-free information word can be removed at the output of the second X-OR stage 9 when the shift register 3 is read out a second time.

Bei dem hier beschriebenen Ausführungsbeispiel des erfindungsgemäßen Verfahrens ersetzt das 26-Bit-Schieberegister 3 vor der ersten X-OR-Stufe 5 den im bekannten Decoder hinter der ersten X-OR-Stufe vorgesehenen 16-Bit-Zwischenspeicher für das Informationswort.In the exemplary embodiment of the method according to the invention described here, the 26-bit shift register 3 before the first X-OR stage 5 replaces the 16-bit buffer for the information word provided in the known decoder after the first X-OR stage.

Das zeimalige Auslesen der Bits aus dem Schieberegister 3 und die übrigen Vorgänge, wie die Sperrung der Sperrstufe 7, wird durch eine Steuereinheit 12 bewirkt, für deren Takteinheit ein Ausführungsbeispiel in Figur 2 dargestellt ist. Anhand der Fig. 2 wird die Takteinheit näher erläutert.The readout of the bits from the shift register 3 and the other processes, such as the blocking of the blocking stage 7, is effected by a control unit 12, for the clock unit of which an exemplary embodiment is shown in FIG. The clock unit is explained in more detail with reference to FIG. 2.

Für die Steuerung der Vorgänge werden jeweils zwei Pakete von sechsundzwanzig Takten innerhalb der letzten Bitperiode eines Blocks benötigt, die erkennbar voneinander getrennt sind. Dazu ist an den Eingang der Takteinheit ein 114-kHz-Generator 13 angeschlossen. Seine Impulse takten einen 4-Bit-Zähler 14, dessen Überlauf wiederum einen 2-Bit-Zähler 15 taktet. Beide Zähler werden durch einen am Reset-Eingang angelegten Reset-Impuls eines 2,37-kHz-Generators 16 gelöscht. Die Takteinheit ist derart aufgebaut, daß der 4-Bit-Zähler 14 abwechselnd bis zehn oder bis sechzehn zählt. Die Steuerung der Zählweise erfolgte durch den Ausgang einer dritten X-OR-Stufe 17 im Ausgang des 2-Bit-Zählers 15.To control the processes, two packets of twenty-six clock cycles within the last bit period of a block are required, which are clearly separated from one another. For this purpose, a 114 kHz generator 13 is connected to the input of the clock unit. Its pulses clock a 4-bit counter 14, the overflow of which in turn clocks a 2-bit counter 15. Both counters are cleared by a reset pulse of a 2.37 kHz generator 16 applied to the reset input. The clock unit is constructed such that the 4-bit counter 14 alternately counts to ten or to sixteen. The counting method was controlled by the output of a third X-OR stage 17 in the output of the 2-bit counter 15.

In dem ersten Zustand (0.0) des 2-Bit-Zählers 15 zählt der 4-Bit-Zähler 14 bis zehn. Sein Überlauf schaltet den 2-Bit-Zähler 15 in dessen zweiten Zustand (1.0). In diesem Zustand des 2-Bit-Zählers 15 zählt der 4-Bit-Zähler 14 bis sechzehn. Während dieses Zustands (1.0) und des dritten Zustands (1.1) des 2-Bit-Zählers 15, - in welchem der 4-Bit-Zähler 14 wieder bis zehn zählt - ist eine Torschaltung 18 geöffnet, an der insgesamt sechsundzwanzig Verschiebetakte V (sechzehn plus zehn) mit einer Frequenz von 114 kHz auf der Verschiebetaktleitung V erscheinen. Diese Verschiebetakte V steuern das Auslesen des Schieberegisters 3 und das Syndromregister 8. Die in dem dritten Zustand (1.1) des 2-Bit-Zählers 15 abgegebenen zehn Verschiebetakte V steuern auch die Ausgabe des Offsetwortes aus dem Offsetwortgenerator 6.In the first state (0.0) of the 2-bit counter 15, the 4-bit counter 14 to ten counts. Its overflow switches the 2-bit counter 15 into its second state (1.0). In this state of the 2-bit counter 15, the 4-bit counter 14 to sixteen counts. During this state (1.0) and the third state (1.1) of the 2-bit counter 15, in which the 4-bit counter 14 counts to ten again, a gate circuit 18 is opened, on which a total of twenty-six shift clocks V (sixteen plus ten) appear at a frequency of 114 kHz on the shift clock line V. These shift clocks V control the reading of the shift register 3 and the syndrome register 8. The ten shift clocks V output in the third state (1.1) of the 2-bit counter 15 also control the output of the offset word from the offset word generator 6.

Bei dem zwölften Zählimpuls des 4-Bit-Zählers 14 im vierten Zustand (0.1) des 2-Bit-Zählers 15 ist eine 2,37-kHz-Periode abgelaufen. Damit erscheint ein Reset-Impuls aus dem 2,37-kHz-Generator 16 am Reset-Eingang und beide Zähler 14 und 15 werden gelöscht. Dabei wird ein Impuls auf die Wiederholungsleitung W gegeben. Danach beginnt der zweite Zyklus der Takteinheit.At the twelfth count pulse of the 4-bit counter 14 in the fourth state (0.1) of the 2-bit counter 15, a 2.37 kHz period has expired. A reset pulse from the 2.37 kHz generator 16 thus appears at the reset input and both Counters 14 and 15 are cleared. A pulse is given to the repetition line W. Then the second cycle of the clock unit begins.

Die Torschaltungen 21 und 22 im Eingang und im Reseteingang der Takteinheit werden jeweils erst durch den Blocktakt B geöffnet, den der Bitzähler 4 liefert. Sie vermeiden eine Decodierung vor der letzten Bitperiode eines Blocks.The gate circuits 21 and 22 in the input and in the reset input of the clock unit are only opened by the block clock B, which the bit counter 4 supplies. You avoid decoding before the last bit period of a block.

Die Steuereinheit 12 ist derart programmiert, daß nach dem Einlesen des letzten Bits eines Blocks in das Schieberegister 3, wenn der Blocktakt B erscheint, der Eingang des Schieberegisters 3 von dem RDS-Empfänger 1 getrennt und mit dem Ausgang des Schieberegisters 3 verbunden wird und das Syndrom-Register 8 gelöscht wird; z. B. wenn der 4-Bit-Zähler 14 im ersten Zustand des 2-Bit-Zählers 15 bis vier gezählt hat. Danach wird mit dem ersten Paket von 26 Verschiebetakten V der Inhalt des Schieberegisters 3 erstmals ausgelesen. Zugleich rotiert der Inhalt im Schieberegister 3. Während des Auslesevorganges wird der ausgelesene Block in der ersten X-OR-Stufe 5 mit dem aus dem Offsetwort-Generator 6 taktgleich ausgelesenen Offsetwort verknüpft und dabei das Codewort von dem überlagerten Offsetwort befreit. Das Codewort wird über die offene Sperrstufe 7 in das zuvor gelöschte Syndromregister 8 eingelesen. In dem Syndromregister 8 wird das zugehörige Syndrom durch die Verknüpfung der Zellen in der bekannten Weise errechnet und dabei eine eventuelle Fehlerkorrektur vorbereitet.The control unit 12 is programmed such that after reading the last bit of a block into the shift register 3, when the block clock B appears, the input of the shift register 3 is separated from the RDS receiver 1 and connected to the output of the shift register 3, and that Syndrome register 8 is cleared; e.g. B. when the 4-bit counter 14 has counted 15 to four in the first state of the 2-bit counter. The contents of the shift register 3 are then read out for the first time with the first packet of 26 shift clocks V. At the same time, the content rotates in shift register 3. During the readout process, the block read in the first X-OR stage 5 is linked to the offset word read out from the offset word generator 6 with the same clock, and the code word is freed from the superimposed offset word. The code word is read into the previously deleted syndrome register 8 via the open blocking stage 7. In the syndrome register 8, the associated syndrome is calculated by linking the cells in the known manner, and a possible error correction is prepared in the process.

An den ersten Auslesevorgang schließt sich eine zweiter Auslesevorgang des Schieberegisters während des zweiten Zyklus der Takteinheit an. Zu Beginn des zweiten Zyklus wird, beispielsweise wenn der 4-Bit-Zähler 14 im ersten Zustand des 2-Bit-Zählers 15 bis zwei gezählt hat, die Sperrstufe 7 über die Wiederholungsleitung W gesperrt und die zweite X-OR-Stufe 9 zur Ausgabe des Codewortes freigegeben. Die Löschung des Syndromregisters 8 und eine Umschaltung des Datenumschalters 2 bei dem vierten Zähltakt wird im zweiten Zählzyklus unterdrückt. Die Sperrung der Sperrstufe 7 verhindert, daß bei dem zweiten Paket von sechsundzwanzig Verschiebetakten erneut Bits in das Syndromregister 8 eingelesen werden. Nur die Verknüpfungsschleife 19 in dem Syndromregister bleibt geschlossen, so lange das Schleifentor 20 geöffnet ist.The first readout is followed by a second readout of the shift register during the second cycle of the clock unit. At the beginning of the second cycle, for example when the 4-bit counter 14 has counted 15 to two in the first state of the 2-bit counter, the blocking stage 7 is blocked via the repetition line W and the second X-OR stage 9 is output of the code word released. The deletion of the syndrome register 8 and a switchover of the data switch 2 at the fourth counting cycle are suppressed in the second counting cycle. The blocking of the blocking stage 7 prevents bits from being read into the syndrome register 8 again in the second packet of twenty-six shift clocks. Only that Linking loop 19 in the syndrome register remains closed as long as the loop gate 20 is open.

Sobald in den ersten fünf Zellen des Syndromregisters 8 eine Null steht, wird die Torschaltung 10 im Ausgang des Syndromregisters 8 über die NOR-Torschaltung 11 freigegeben und zugleich die Verknüpfungsschleife 19 im Syndromregister durch Sperrung des Schleifentores 20 unterbrochen. Nach der Freigabe des Syndromregisterausganges werden diejenigen Bits, welche anschließend die erste X-OR-Stufe 5 verlassen, bitweise mit den aus dem Syndromregister 8 ausgelesenen Bits in der zweiten X-OR-Stufe 9 verknüpft.As soon as there is a zero in the first five cells of the syndrome register 8, the gate circuit 10 in the output of the syndrome register 8 is released via the NOR gate circuit 11 and at the same time the logic loop 19 in the syndrome register is interrupted by blocking the loop gate 20. After the release of the syndrome register output, those bits which subsequently leave the first X-OR stage 5 are linked bit by bit with the bits read from the syndrome register 8 in the second X-OR stage 9.

Bei dem fehlerfreien Empfang eines Codewortes ergibt schon die Syndromberechnung bei dem ersten Auslesen den Wert Null, d. h., daß in allen Zellen des Syndromregisters eine Null steht und somit auch in deren ersten fünf Zellen. Dann ist die Torschaltung 10 im Ausgang des Syndromregisters bereits zu Beginn des zweiten Pakets von sechsundzwanzig Taktimpulsen durch die NOR-Torschaltung 11 freigegeben und das Schleifentor 20 gesperrt.If a code word is received correctly, the syndrome calculation already results in the value zero when it is read out for the first time. that is, there is a zero in all cells of the syndrome register and thus also in the first five cells. Then the gate circuit 10 in the output of the syndrome register is already released by the NOR gate circuit 11 at the beginning of the second packet of twenty-six clock pulses and the loop gate 20 is blocked.

Bei fehlerhaftem Empfang eines Codewortes ist eine Korrektur immer dann möglich, wenn spätestens bis zum zweiten Auslesen des fünftletzten Bits aus dem Schieberegister die Torschaltung 10 freigegeben ist.If a code word is received incorrectly, a correction is always possible when the gate circuit 10 is released at the latest by the second reading of the fifth-last bit from the shift register.

Die hier nur angedeuteten Vorgänge zur Fehlerkorrektur sind an sich aus dem Anhang der bereits angezogenen DIN-Norm bekannt. Mit dem erfindungsgemäßen Verfahren wird jedoch im Gegensatz zum Stand der Technik erreicht, daß zur Fehlerkorrektur auch die Prüfbits im Codewort mit herangezogen werden, was zu der eingangs erwähnten höheren Sicherheit führt, weil bei korrigierbaren Fehlern in den Prüfbits die Datenbits nicht verworfen zu werden brauchen.The processes for error correction only indicated here are known per se from the appendix to the DIN standard that has already been drawn up. With the method according to the invention, however, in contrast to the prior art, it is achieved that the test bits in the code word are also used for error correction, which leads to the higher security mentioned at the outset, because in the case of correctable errors in the test bits, the data bits need not be discarded.

Nach der Datenausgabe wird bis zum Beginn des nächsten Blocktakts die Takteinheit in der Steuereinheit 12 stillgesetzt.After the data output, the clock unit in the control unit 12 is stopped until the start of the next block cycle.

Das erfindungsgemäße Verfahren ist nicht auf dem Ausführungsbeispiel angegebene Generatorfrequenzen beschränkt, diese können durchaus auch wesentlich höher gewählt werden, wenn das Programm des Datenprozessors in dem Decoder dies erfordert.The method according to the invention is not limited to the generator frequencies specified in the exemplary embodiment, these can also be used can be chosen much higher if the program of the data processor in the decoder requires it.

Claims (3)

Verfahren zur Decodierung von mit einem RDS-Empfänger empfangenen Datenblöcken, bei dem die dem Prüfwort im einzelnen Datenblock zugeordneten Bits in einer ersten X-OR-Stufe mit den Bits des zu dem Datenblock gehörenden Offsetwort verknüpft werden und danach der fehlerfreie Empfang des Datenblocks in einem Syndromregister geprüft und dabei gegebenenfalls eine Fehlerkorrektur vorbereitet wird, für welche die dem Informationswort zugeordneten Bits zur Ausgabe über eine zweite X-OR-Stufe zwischengespeichert werden,
dadurch gekennzeichnet,
daß alle empfangenen Bits des Datenblocks zunächst in einem der ersten X-OR-Stufe (5) vorgeschalteten Zwischenspeicher (3) eingelesen werden, nach Speicherung eines vollständigen Datenblocks aus dem Zwischenspeicher (3) während der letzten Bitperiode des Datenblocks zweimal ausgelesen werden und bei dem ersten Auslesen über die erste X-OR-Stufe (5) in das Syndromregister (8) eingelesen werden, daß beim zweiten Auslesen der Eingang des Syndromregisters (8) durch eine Sperrstufe (7) gesperrt ist und daß das in der ersten X-OR-Stufe (5) vom überlagerten Offsetwort befreite Codewort über die dem Ausgang der ersten X-OR-Stufe (5) direkt nachgeschaltete zweite X-OR-Stufe (9) ausgegeben wird.Method for decoding data blocks received with an RDS receiver, in which the bits assigned to the test word in the individual data block are linked in a first X-OR stage with the bits of the offset word belonging to the data block and then the error-free reception of the data block in one Syndrome register checked and an error correction prepared if necessary, for which the bits assigned to the information word are buffered for output via a second X-OR stage,
characterized,
that all received bits of the data block are first read in a buffer (3) upstream of the first X-OR stage (5), after storing a complete data block from the buffer (3) during the last bit period of the data block, they are read out twice and in the the first readout via the first X-OR stage (5) can be read into the syndrome register (8), that during the second readout the input of the syndrome register (8) is blocked by a blocking stage (7) and that in the first X-OR -Stage (5) from the superimposed offset word, the codeword via which the second X-OR stage (9) directly downstream of the output of the first X-OR stage (5) is output. Verfahren nach Anspruch 1,
dadurch gekennzeichnet,
daß die empfangenen Bits nacheinander in einem 26-Bit-Schieberegister (3) zwischengespeichert werden und beim ersten Auslesen des Schieberegisters (3) auch zum Eingang des Schieberegisters (3) zurückgeführt werden.Method according to claim 1,
characterized,
that the bits received are buffered one after the other in a 26-bit shift register (3) and, when the shift register (3) is read out for the first time, are also returned to the input of the shift register (3). Schaltungsanordnung zur Durchführung des Verfahrens nach Anspruch 1 oder 2 mit einer dem RDS-Empfänger (1) nachgeschalteten ersten X-OR-Stufe (5), die im Eingang eines Syndromregisters (8) liegt, mit einer zweiten X-OR-Stufe (9), deren zweiter Eingang über eine Torschaltung (10) mit dem Ausgang des Syndromregisters verbunden ist, und mit einer Steuereinheit,
gekennzeichnet
durch ein zwischen dem Ausgang des RDS-Empfängers (1) und der ersten X-OR-Stufe (5) eingefügten 26-Bit-Schieberegister (3), durch eine von der Steuereinheit (12) steuerbare Sperrstufe (7) zwischen dem Ausgang der ersten X-OR-Stufe (5) und dem Eingang des Syndromregisters (8) und durch eine Verbindungsleitung zwischen dem Ausgang der ersten X-OR-Stufe (5) und dem ersten Eingang der zweiten X-OR-Stufe (9).Circuit arrangement for carrying out the method according to claim 1 or 2 with a first X-OR stage (5) connected downstream of the RDS receiver (1) and located in the input of a syndrome register (8) with a second X-OR stage (9 ), the second input of which is connected to the output of the syndrome register via a gate circuit (10), and to a control unit,
featured
by a 26-bit shift register (3) inserted between the output of the RDS receiver (1) and the first X-OR stage (5), by a blocking stage (7) controllable by the control unit (12) between the output of the first X-OR stage (5) and the input of the syndrome register (8) and through a connecting line between the output of the first X-OR stage (5) and the first input of the second X-OR stage (9).
EP96106156A 1995-06-07 1996-04-19 Method for decoding data blocks received by a RDS receiver Expired - Lifetime EP0748055B1 (en)

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DE19520685A DE19520685A1 (en) 1995-06-07 1995-06-07 Method for decoding data blocks received with an RDS receiver
DE19520685 1995-06-07

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Cited By (1)

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Publication number Priority date Publication date Assignee Title
EP1209445A2 (en) * 2000-11-24 2002-05-29 Audi Ag System and method for management of navigational data and data carrier

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19526447A1 (en) 1995-07-20 1997-01-23 Blaupunkt Werke Gmbh Device for synchronizing the block counter in an RDS receiver

Citations (2)

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Publication number Priority date Publication date Assignee Title
US4821270A (en) * 1985-12-13 1989-04-11 U.S. Philips Corporation Method for decoding data transmitted along a data channel and an apparatus for executing the method
EP0567799A1 (en) * 1992-04-29 1993-11-03 Blaupunkt-Werke GmbH Apparatus for data reception

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4821270A (en) * 1985-12-13 1989-04-11 U.S. Philips Corporation Method for decoding data transmitted along a data channel and an apparatus for executing the method
EP0567799A1 (en) * 1992-04-29 1993-11-03 Blaupunkt-Werke GmbH Apparatus for data reception

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1209445A2 (en) * 2000-11-24 2002-05-29 Audi Ag System and method for management of navigational data and data carrier
EP1209445A3 (en) * 2000-11-24 2007-10-17 Audi Ag System and method for management of navigational data and data carrier

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DE19520685A1 (en) 1996-12-12
DE59607920D1 (en) 2001-11-22
EP0748055A3 (en) 1998-06-10

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