EP0747874A1 - Anode switching in a flat panel display - Google Patents

Anode switching in a flat panel display Download PDF

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Publication number
EP0747874A1
EP0747874A1 EP96410066A EP96410066A EP0747874A1 EP 0747874 A1 EP0747874 A1 EP 0747874A1 EP 96410066 A EP96410066 A EP 96410066A EP 96410066 A EP96410066 A EP 96410066A EP 0747874 A1 EP0747874 A1 EP 0747874A1
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EP
European Patent Office
Prior art keywords
potential
cathode
transistor
conductive strips
display screen
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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EP96410066A
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German (de)
French (fr)
Inventor
Bernard Bancal
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pixtech SA
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Commissariat a lEnergie Atomique CEA
Pixtech SA
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources

Definitions

  • the present invention relates to a flat display screen of the type comprising a cathode with microtips for electron bombardment of an anode carrying phosphor elements.
  • the present invention relates to flat display screens, and more particularly to so-called cathodoluminescence screens, the anode of which carries luminescent elements separated from each other by insulating zones and capable of being excited by electronic bombardment.
  • This electronic bombardment requires that the luminescent elements are polarized and can come from microtips, from layers with low extraction potential or from a thermionic source. It applies more particularly to the switching of the anode of a color screen.
  • microtip color screens To simplify the present description, below only the microtip color screens will be considered, but it will be noted that the invention relates generally to the various types of screens mentioned above and the like.
  • Figure 1 shows the functional structure of a microtip flat screen
  • Such a microtip screen essentially consists of a cathode 1 with microtips 2 and a grid 3 provided with holes 4 corresponding to the locations of the microtips 2.
  • the cathode 1 is placed opposite a cathodoluminescent anode 5 of which a glass substrate 6 constitutes the screen surface.
  • the cathode 1 is organized in columns and consists, on a substrate 10 for example of glass, of cathode conductors organized in meshes from a conductive layer.
  • the microtips 2 are produced on a resistive layer 11 deposited on the cathode conductors and are arranged inside the meshes defined by the cathode conductors.
  • FIG. 1 partially represents the interior of a mesh, the cathode conductors do not appear in this figure.
  • the cathode 1 is associated with the grid 3 which is it organized in lines, an insulating layer (not shown) being interposed between the cathode conductors and the grid 3. The intersection of a line of the grid 3 and a column of cathode 1 defines a pixel.
  • This device uses the electric field created between the cathode 1 and the grid 3 so that electrons are extracted from the microtips 2 towards phosphor elements 7 of the anode 5.
  • the anode 5 is provided with alternating bands d 'phosphor elements 7, each corresponding to a color (Blue, Red, Green). The strips are separated from each other by an insulator 8.
  • the phosphor elements 7 are deposited on electrodes 9, consisting of corresponding strips of a transparent conductive layer such as indium tin oxide (ITO) .
  • ITO indium tin oxide
  • the sets of blue, red and green bands are alternately polarized with respect to the cathode 1, so that the electrons extracted from the microtips 2 of a pixel of the cathode / grid are alternately directed towards the phosphor elements 7 opposite each of the colors.
  • the rows of the grid 3 are sequentially polarized at a potential of the order of 80 volts while the strips carrying phosphor elements (for example 7g in FIG. 1) to be excited are polarized under a voltage of the order of 400 volts, the other bands carrying phosphor elements (for example 7r and 7b in FIG. 1) being at zero potential.
  • the columns of cathode 1, the potential of which represents for each row of grid 3 the brightness of the pixel defined by the intersection of the column of cathode and of the row of grid in the color considered, are brought to potentials respective between a maximum emission potential and an absence of emission potential (for example 0 and 30 volts respectively).
  • the choice of the values of the polarization potentials is linked to the characteristics of the phosphor elements 7 and the microtips 2. Conventionally, below a potential difference of 50 volts between the cathode and the grid, there is no emission. electronic and, the maximum emission used corresponds to a potential difference of 80 volts.
  • FIG. 2 represents an example of a conventional device for polarizing, or switching, a set of conductive strips 9 carrying phosphor elements. Such a device is integrated into a control circuit (not shown) of the screen. For a color screen, the control circuit includes three such devices (one for each color).
  • a conventional switching device includes two power MOS transistors, P channel MP and N channel MN respectively.
  • the source of the transistor MP is connected to a positive addressing potential V Ah (for example around 400 volts) while its drain is connected to the drain of the transistor MN whose source is connected to a zero potential (ground M) .
  • the drains of the transistors MP and MN are connected to a first terminal of a resistor R 1 , the other terminal of which constitutes an output terminal 20 of the device connected to the set of conductive strips with which the device is associated.
  • the gates of the transistors MP and MN receive time-shifted control signals, respectively C P and C N , to allow the switching of the output 20 of the device between the potential V Ah and the ground.
  • These control signals C P and C N are two-state signals.
  • the signals C P and C N are in a low state during the frame time of the color with which the device is associated and in a high state during the frame times of the other two colors.
  • the states low and high, respectively, of the signals C P and C N are, for example, 0 and 5 volts.
  • the signals C P and C N are sent to control terminals, respectively 21 and 22.
  • the gate of the transistor MP is connected, via a resistor R 3 connected in series with a capacitor C 1 , to the terminal 21.
  • the gate of transistor MN is connected, via a resistor R 4 , to terminal 22.
  • the gate of transistor MP is also connected to potential V Ah via a Zener diode D Z1 and a resistor R 2 connected in parallel.
  • the switching of the output 20 of the device between the potential V Ah and the ground takes place on the edges of the signals C P and C N.
  • the capacitor C 1 is used to allow switching of the transistor MP from the control signal C P whose potentials are referenced to ground and not to V Ah .
  • the potential of its gate must be brought to a value lower than the potential V Ah .
  • a falling edge of the signal C P is transmitted, in the form of a pulse, by the capacitor C 1 on the gate of the transistor MP which makes it conducting.
  • the appearance of the next (rising) edge of the signal C P causes, conversely, the blocking of the transistor MP by bringing its gate to a potential equal to potential V Ah .
  • the role of the Zener diode D Z1 is to protect the transistor MP by limiting the potential difference between its gate and its source to a value corresponding to the value of the Zener diode, for example 4.7 volts.
  • the role of the Zener diode Z Z1 is also to prevent the gate voltage from substantially exceeding V Ah.
  • a condition must however be met so that the edges of the signal C P can cause the switching of the transistor MP.
  • the time constant, generated by the gate capacitance of the transistor MP associated with the resistor R 2 must be greater than the time constant provided by the association of the resistor R 3 with the capacitor C 1 and the capacitance of gate of the transistor MP.
  • the values of resistors R 2 and R 3 and of capacitor C 1 are chosen so that the condition R 2 C g > R 3 (C 1 + C g ), where C g represents the gate capacity of the MP transistor, be respected.
  • the transistor MN is in turn controlled by the signal C N.
  • the signal C N can be applied to its gate without using a capacitor.
  • the transistor MN is on because the potential of its gate is greater than the potential of its source.
  • the transistor MN is, on the contrary, blocked.
  • a disadvantage of conventional color screens is that, during the polarization of a set of bands of a given color, there is a spurious emission of the other two colors.
  • FIG. 3 shows schematically and in section along a row of the grid 3, a pixel of the screen.
  • FIG. 3 shows schematically and in section along a row of the grid 3, a pixel of the screen.
  • FIG. 3 shows schematically and in section along a row of the grid 3, a pixel of the screen.
  • only a few microtips 2 have been shown for reasons of clarity, although they are, in practice, several thousand per pixel of the screen.
  • the conductive strips 9g carrying the green phosphor elements 7g are addressed by being polarized at a positive potential, for example of 400 volts, while the conductive strips 9r and 9b carrying, respectively, the red phosphor elements 7r and blue 7b are at rest while being at zero potential.
  • phosphor elements can remain polarized at a potential greater than the minimum potential (0 volts) of polarization of the microtips due to these parasitic capacities and the high potential (of the order of 400 volts) of addressing.
  • the parasitic bombardment phenomenon can be increased by a ballistic effect which leads to the fact that certain electrons emitted by the microtips facing the red or blue bands do not have time to be deflected to be collected by the green phosphor elements.
  • the path of the electrons has been represented symbolically by arrows, the path of the parasitic electrons being symbolized by dotted lines.
  • the present invention aims to overcome this drawback by proposing a flat microtip display screen in which the conductive strips of the anode which carry phosphor elements are switched in such a way that the electrons emitted by the microtips are effectively all collected by the phosphor elements of the desired color.
  • Another object of the present invention is to allow such switching by using the supply voltages which are conventionally available within the screen control circuit.
  • the present invention provides a flat display screen of the type comprising an electron bombardment cathode of an anode provided with at least two sets of alternating conductive strips carrying phosphor elements and a control circuit capable of addressing sequentially.
  • each of said assemblies characterized in that said control circuit comprises means for bringing, at least temporarily, each set of conductive strips to a potential lower than a minimum bias potential of the cathode.
  • said means comprise, for each set of conductive strips, a switching device between a positive addressing potential of the assembly associated with the device and a rest potential lower than the minimum bias potential of the cathode.
  • said minimum bias potential of the cathode corresponds to the ground, said quiescent potential of a set of conductive strips being negative.
  • said means comprise, for each set of conductive strips, a device for switching between a positive addressing potential of the set associated with the device and a rest potential equal to the minimum bias potential cathode microtips, said device comprising means for using the transition between the addressing potential and the resting potential of a set of conductive strips to cause an impulse at a potential lower than the potential minimum polarization of the cathode on another set of conductive strips.
  • a switching device comprises two MOS transistors, the respective gates of which receive appropriate control signals, the drain of a first P-channel transistor constituting an output terminal of the device intended to be connected , via a first resistor, to a set of conductive strips carrying phosphor elements, the source of said first transistor being connected to said positive addressing potential and its gate being connected, via a first diode Zener connected in parallel with a second resistor, to said positive addressing potential and, via a third resistor connected in series with a first capacitor, to a first control terminal receiving a first two-state signal.
  • the drain of a second N-channel transistor is connected to the drain of said first transistor, the source of said second transistor being connected to the quiescent potential and its gate being connected, via a fourth resistor connected in series with a second capacitor, to a second control terminal receiving a second two-state signal and, via a second Zener diode connected in parallel with a fifth resistor, to said quiescent potential.
  • the drain of a second N-channel transistor is connected, via a second Zener diode, to the output terminal of the device, the source of said second transistor being connected to the ground and its grid being connected, via a fourth resistor, to a second control terminal receiving a second two-state signal, the maximum amplitude of the negative pulses being fixed by the value of the second Zener diode.
  • a fifth resistor of high value is placed in parallel with said second Zener diode.
  • the flat display screen comprises three sets of alternating conductive strips carrying phosphor elements and each corresponding to a color and three switching devices, and in that the first control signals respectively associated the devices are, successively, in a high state during frame times of the colors with which they are respectively associated and, simultaneously, at ground for a predetermined period between two color frames.
  • the cathode is of the microtip type.
  • the main idea of the present invention is to ensure an inhibition of the faculty of attraction of the phosphor elements carried by conductive bands (9 in FIG. 1) which are not addressed by applying to these bands, at least temporarily, a potential lower than the minimum polarization potential of the cathode microtips and thus remove any residual charge from the phosphor elements carried by these bands.
  • FIG. 4 illustrates a first embodiment of a device for switching an anode according to the invention.
  • the quiescent potential of the strips of phosphor elements is a potential V Al less than the minimum potential of polarization of the cathode microtips.
  • V Al a potential of polarization of the cathode microtips.
  • V Ah a positive addressing potential
  • a switching device comprises two MOS transistors of power MP and MN, the drains of which are connected to a first terminal of a first resistor R 1 , the other terminal of which constitutes an output 20 of the device to which is connected a set of conductive strips carrying phosphor elements.
  • a first P channel transistor MP has, as before, its source connected to the addressing potential V Ah .
  • the gate of the transistor MP is connected, via a first Zener diode D Z1 mounted in parallel with a second resistor R 2 , to the addressing potential V Ah and, via a third resistor R 3 connected in series with a first capacitor C 1 , at a first terminal 21 receiving a first control signal C P.
  • a similar arrangement is reproduced for a second N-channel transistor MN, its source being connected to the quiescent potential V Al .
  • the gate of transistor MN is connected, via a fourth resistor R 4 connected in series with a second capacitor C 2 , to a second control terminal 22 receiving a second control signal C N .
  • the gate of transistor MN is also connected, via a second Zener diode D Z2 connected in parallel with a fifth resistor R 5 , to the quiescent potential V Al .
  • the control signals C P and C N correspond to the signals used for the switching of conventional devices and are therefore signals inverted with respect to each other and in two states (for example 0 and 5 volts).
  • the role of the capacitor C 2 is to allow switching of the transistor MN whose source is at a negative potential by means of the signal C N which is, as before, a signal whose low state is grounded.
  • the potential of its gate must be brought to a value greater than the potential V Al .
  • a rising edge of the signal C N is transmitted, in the form of a pulse, by the capacitor C 2 on the gate of the transistor MN which makes it conducting.
  • the role of the Zener diode D Z2 is to protect the transistor MN by limiting the potential difference between its gate and its source to a value corresponding to the value of the Zener diode, for example 4.7 volts.
  • the appearance of the next (falling) edge of the signal C N causes, conversely, the blocking of the transistor MN by bringing its gate to a potential equal to or slightly lower than the potential V Al .
  • the transistor MP a condition must however be respected so that the edges of the signal C N can cause switching of transistor MN. It will be ensured that the time constant, generated by the gate capacitance of the transistor MN associated with the resistor R 5 , is greater than the time constant provided by the association of the resistor R 4 with the capacitor C 2 and the capacitor gate of transistor MN.
  • the values of resistors R 4 and R 5 and of capacitor C 2 are chosen so that the condition R 5 C g > R 4 (C 2 + C g ), where C g represents the gate capacity of the transistor MN, be respected.
  • a device as shown in FIG. 4 is reproduced for each set of bands of phosphor elements of the anode.
  • the transistor MN of the device associated with it conducts and the conductive strips of this assembly are then at the negative potential V Al .
  • the potential V Al is chosen to be much lower than the minimum potential for polarization of the microtips.
  • the value of the potential V Al is, for example, between -100 and -200 volts.
  • FIG. 5 illustrates a second embodiment of a device for switching an anode according to the invention. This device differs from the device shown in FIG. 4 by the fact that it does not require having a strongly negative supply voltage to serve as the rest potential of the conductive strips which are not addressed.
  • FIG. 6 represents the simplified equivalent electrical diagram of an anode of a color screen, from the capacitive point of view.
  • the resulting capacitors, respectively C GB , C BR and C RG , between the sets of conductive strips of the anode form a triangle network whose vertices correspond to the connection terminals of each of the colors, respectively G, B and R. terminals G, B and R are each connected to an output terminal 20 of a switching device according to the invention.
  • a switching device comprises two MOS transistors of power MP and MN.
  • a device is associated with each set of conductive strips carrying phosphor elements.
  • the terminals R, G and B of FIG. 6 are each connected to a terminal 20 of a device as shown in FIG. 5.
  • the assembly associated with a first P MP channel transistor is similar to that of the first embodiment.
  • a second N-channel transistor MN is connected, by its gate and via a fourth resistor R 4 , to a second control terminal 22 receiving a second control signal C N with two states, shifted in time with respect to the signal C P.
  • the source of transistor MN is connected to ground M which here corresponds to the minimum potential for polarization of the microtips of the cathode.
  • the drain of the transistor MN is connected to the output terminal 20 via a fifth resistor R 5 of high value mounted in parallel with a second Zener diode D Z2 .
  • the role of the diode D Z2 is to allow switching of the terminal 20 between the potential V Ah and the ground M at the end of the addressing of the set of bands with which the device is associated.
  • the diode D Z2 also makes it possible to prevent a set of bands which should not be addressed from being brought to a positive potential by the rising edges of the other two sets under the effect of the capacitive coupling.
  • the role of the resistor R 5 of high value is to limit the absorption of the negative current, due to the capacitive coupling, at the end of the addressing of the set of bands and thus to slow down the damping of the negative pulses on the other two sets of bands.
  • control signals associated with the various devices are produced so that there remains, between each color frame time, a period during which all of the MP transistors are blocked. In other words, there is provided, during the establishment of the control signals, a time interval between two successive color frames during which the negative pulses are favored.
  • An advantage of this second embodiment is that it does not require any additional supply voltage.
  • FIG. 7 illustrates, in the form of timing diagrams, the operation of a color screen anode by means of switching devices as shown in FIG. 6.
  • FIG. 7 represents, for two time intervals Im (i) and Im (i + 1) corresponding to the display time of two images, the shape of the signals present on the terminals R, G and B of interconnection of the conductive strips carrying phosphor elements, respectively, red, green and blue and the shape of the control signals, respectively C PR , C PG and C PB associated with the switching devices of these assemblies.
  • the control signals C N of the devices have not been shown, they correspond to the signals C P with a time offset.
  • the switching of the rows of the grid and of the cathode columns within each image time is carried out in a conventional manner.
  • Each signal C P therefore comprises, within each image time, a level at ground of a duration corresponding to the frame time.
  • the transistor MP of the device associated with terminal R is blocked while the rising edge of signal C N which is associated with it causes its transistor MN to conduct.
  • the Zener diode D Z2 the potential of the terminal R is immediately reduced to ground, the resistor R 5 being short-circuited.
  • the falling edge of the potential of terminal R causes, due to the capacitive coupling, a negative pulse on terminals G and B, therefore on the conductive strips which are associated therewith.
  • the diodes D Z2 of the devices associated with the terminals G and B are then reverse biased. However, by their dimensioning, they limit the amplitude V Al of the negative pulses.
  • the resistors R 5 of the devices associated with the terminals G and B introduce, with the parasitic capacitances, respectively C RG and C BR , a time constant which delays the damping of these negative pulses, the transistors MN of these devices being at passing state. If necessary, the resistance R 5 can be omitted and the leakage resistance of the diode D Z2 then fulfills the role of limiting the negative current.
  • the negative pulses present on the terminals G and B disappear, in any case, at the appearance of the rising edge of the signal C PG which follows and which has the effect of bringing the terminal G to the potential V Ah to address the set of bands green.
  • the potential of the terminal G is immediately brought to the addressing potential V Ah by switching on the transistor MP of the switching device associated with it and which follows the blocking of the transistor MN of this device.
  • the Zener diodes D Z2 of the associated switching devices, respectively at terminals B and R, which are then directly biased (the transistors MN of these devices are in the on state) prevent the appearance of positive pulses on the terminals B and R, linked to the parasitic capacities C GB and C RG .
  • these positive pulses would be damped according to the time constant linked to the association of the resistors R 5 of these devices with the capacitances, respectively C GB and C RG .
  • the duration t between each level is fixed as a function of the desired duration for the negative pulses and of the desired frame times. In fact, the presence of these intervals t during which all of the transistors MP are blocked decreases the image time available for addressing the sets of bands. As a particular example, for image times of 10 ms which correspond to a frequency of 100 Hz, it will be possible to choose intervals t with a duration of between 10 ⁇ s and 1 ms.
  • the frame time which remains available is then at least 7 ms, which is more than sufficient to allow sequential addressing of all the rows of the grid during each frame time.
  • V Al of the negative pulses is fixed by the value of the Zener diode. A value large enough (for example, between 100 and 200 volts) will be chosen to allow sufficient negative pulses.
  • the bands carrying phosphor elements which are not addressed are not permanently at a potential lower than the minimum potential for polarization of the microtips of the cathode, they are temporarily, twice per rest period. This is sufficient to completely discharge the phosphor elements and to prevent parasitic electrons from being collected by the phosphor elements of the unaddressed bands.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)

Abstract

The screen has an anode with luminophores on at least two sets of conductive strips which are bombarded with electrons from microprints of the cathode. Each set in turn is switched by the control circuit to a voltage below the minimum value of the cathode bias. The circuit incorporates two complementary MOSFETs (MP,MN) with gate electrodes addressed by control signals (CP,CN) via series resistors (R3,R4) and capacitors (C1,C2). The source of the n-channel MOSFET is returned to a negative voltage (VAl) below the minimum potential of the cathode microprints. This maximum amplitude of negative pulses is fixed by the value of an additional Zener diode (DZ2).

Description

La présente invention concerne un écran plat de visualisation du type comportant une cathode à micropointes de bombardement électronique d'une anode portant des éléments luminophores.The present invention relates to a flat display screen of the type comprising a cathode with microtips for electron bombardment of an anode carrying phosphor elements.

La présente invention concerne les écrans plats de visualisation, et plus particulièrement des écrans, dits à cathodoluminescence, dont l'anode porte des éléments luminescents séparés les uns des autres par des zones isolantes et susceptibles d'être excités par bombardement électronique. Ce bombardement électronique nécessite que les éléments luminescents soient polarisés et peut provenir de micropointes, de couches à faible potentiel d'extraction ou d'une source thermoionique. Elle s'applique plus particulièrement à la commutation de l'anode d'un écran couleur.The present invention relates to flat display screens, and more particularly to so-called cathodoluminescence screens, the anode of which carries luminescent elements separated from each other by insulating zones and capable of being excited by electronic bombardment. This electronic bombardment requires that the luminescent elements are polarized and can come from microtips, from layers with low extraction potential or from a thermionic source. It applies more particularly to the switching of the anode of a color screen.

Pour simplifier la présente description, on ne considérera ci-après que les écrans couleur à micropointes mais on notera que l'invention concerne de façon générale les divers types d'écrans susmentionnés et analogue.To simplify the present description, below only the microtip color screens will be considered, but it will be noted that the invention relates generally to the various types of screens mentioned above and the like.

La figure 1 représente la structure fonctionnelle d'un écran plat à micropointesFigure 1 shows the functional structure of a microtip flat screen

Un tel écran à micropointes est essentiellement constitué d'une cathode 1 à micropointes 2 et d'une grille 3 pourvue de trous 4 correspondant aux emplacements des micropointes 2. La cathode 1 est placée en regard d'une anode cathodoluminescente 5 dont un substrat de verre 6 constitue la surface d'écran.Such a microtip screen essentially consists of a cathode 1 with microtips 2 and a grid 3 provided with holes 4 corresponding to the locations of the microtips 2. The cathode 1 is placed opposite a cathodoluminescent anode 5 of which a glass substrate 6 constitutes the screen surface.

Le principe de fonctionnement et un exemple de la constitution d'un tel écran à micropointes sont décrits dans le brevet américain numéro 4 940 916 du Commissariat à l'Energie Atomique.The operating principle and an example of the constitution of such a microtip screen are described in American patent number 4 940 916 of the French Atomic Energy Commission.

La cathode 1 est organisée en colonnes et est constituée, sur un substrat 10 par exemple en verre, de conducteurs de cathode organisés en mailles à partir d'une couche conductrice. Les micropointes 2 sont réalisées sur une couche résistive 11 déposée sur les conducteurs de cathode et sont disposées à l'intérieur des mailles définies par les conducteurs de cathode. La figure 1 représentant partiellement l'intérieur d'une maille, les conducteurs de cathode n'apparaissent pas sur cette figure. La cathode 1 est associée à la grille 3 qui est elle organisée en lignes, une couche isolante (non représentée) étant interposée entre les conducteurs de cathode et la grille 3. L'intersection, d'une ligne de la grille 3 et d'une colonne de la cathode 1, définit un pixel.The cathode 1 is organized in columns and consists, on a substrate 10 for example of glass, of cathode conductors organized in meshes from a conductive layer. The microtips 2 are produced on a resistive layer 11 deposited on the cathode conductors and are arranged inside the meshes defined by the cathode conductors. FIG. 1 partially represents the interior of a mesh, the cathode conductors do not appear in this figure. The cathode 1 is associated with the grid 3 which is it organized in lines, an insulating layer (not shown) being interposed between the cathode conductors and the grid 3. The intersection of a line of the grid 3 and a column of cathode 1 defines a pixel.

Ce dispositif utilise le champ électrique créé entre la cathode 1 et la grille 3 pour que des électrons soient extraits des micropointes 2 vers des éléments luminophores 7 de l'anode 5. Pour un écran couleur, l'anode 5 est pourvue de bandes alternées d'éléments luminophores 7, correspondant chacune à une couleur (Bleu, Rouge, Vert). Les bandes sont séparées les unes des autres par un isolant 8. Les éléments luminophores 7 sont déposés sur des électrodes 9, constituées de bandes correspondantes d'une couche conductrice transparente telle que de l'oxyde d'indium et d'étain (ITO). Les ensembles de bandes bleues, rouges, vertes sont alternativement polarisés par rapport à la cathode 1, pour que les électrons extraits des micropointes 2 d'un pixel de la cathode/grille soient alternativement dirigés vers les éléments luminophores 7 en vis à vis de chacune des couleurs.This device uses the electric field created between the cathode 1 and the grid 3 so that electrons are extracted from the microtips 2 towards phosphor elements 7 of the anode 5. For a color screen, the anode 5 is provided with alternating bands d 'phosphor elements 7, each corresponding to a color (Blue, Red, Green). The strips are separated from each other by an insulator 8. The phosphor elements 7 are deposited on electrodes 9, consisting of corresponding strips of a transparent conductive layer such as indium tin oxide (ITO) . The sets of blue, red and green bands are alternately polarized with respect to the cathode 1, so that the electrons extracted from the microtips 2 of a pixel of the cathode / grid are alternately directed towards the phosphor elements 7 opposite each of the colors.

Généralement, les rangées de la grille 3 sont séquentiellement polarisées à un potentiel de l'ordre de 80 volts tandis que les bandes portant des éléments luminophores (par exemple 7g en figure 1) devant être excités sont polarisées sous une tension de l'ordre de 400 volts, les autres bandes portant des éléments luminophores (par exemple 7r et 7b en figure 1) étant à un potentiel nul. Les colonnes de la cathode 1, dont le potentiel représente pour chaque rangée de la grille 3 la brillance du pixel défini par l'intersection de la colonne de la cathode et de la rangée de la grille dans la couleur considérée, sont portées à des potentiels respectifs compris entre un potentiel d'émission maximale et un potentiel d'absence d'émission (par exemple respectivement 0 et 30 volts).Generally, the rows of the grid 3 are sequentially polarized at a potential of the order of 80 volts while the strips carrying phosphor elements (for example 7g in FIG. 1) to be excited are polarized under a voltage of the order of 400 volts, the other bands carrying phosphor elements (for example 7r and 7b in FIG. 1) being at zero potential. The columns of cathode 1, the potential of which represents for each row of grid 3 the brightness of the pixel defined by the intersection of the column of cathode and of the row of grid in the color considered, are brought to potentials respective between a maximum emission potential and an absence of emission potential (for example 0 and 30 volts respectively).

Le choix des valeurs des potentiels de polarisation est lié aux caractéristiques des éléments luminophores 7 et des micropointes 2. Classiquement, en dessous d'une différence de potentiel de 50 volts entre la cathode et la grille, il n'y a pas d'émission électronique et, l'émission maximale utilisée correspond à une différence de potentiel de 80 volts.The choice of the values of the polarization potentials is linked to the characteristics of the phosphor elements 7 and the microtips 2. Conventionally, below a potential difference of 50 volts between the cathode and the grid, there is no emission. electronic and, the maximum emission used corresponds to a potential difference of 80 volts.

La figure 2 représente un exemple de dispositif classique de polarisation, ou de commutation, d'un ensemble de bandes conductrices 9 portant des éléments luminophores. Un tel dispositif est intégré à un circuit de commande (non représenté) de l'écran. Pour un écran couleur, le circuit de commande comporte trois dispositifs de ce type (un pour chaque couleur).FIG. 2 represents an example of a conventional device for polarizing, or switching, a set of conductive strips 9 carrying phosphor elements. Such a device is integrated into a control circuit (not shown) of the screen. For a color screen, the control circuit includes three such devices (one for each color).

Un dispositif de commutation classique comporte deux transistors MOS de puissance, respectivement à canal P MP et à canal N MN. La source du transistor MP est connectée à un potentiel positif d'adressage VAh (par exemple d'environ 400 volts) tandis que son drain est relié au drain du transistor MN dont la source est connectée à un potentiel nul (la masse M). Les drains des transistors MP et MN sont reliés à une première borne d'une résistance R1 dont l'autre borne constitue une borne 20 de sortie du dispositif reliée à l'ensemble de bandes conductrices auquel le dispositif est associé.A conventional switching device includes two power MOS transistors, P channel MP and N channel MN respectively. The source of the transistor MP is connected to a positive addressing potential V Ah (for example around 400 volts) while its drain is connected to the drain of the transistor MN whose source is connected to a zero potential (ground M) . The drains of the transistors MP and MN are connected to a first terminal of a resistor R 1 , the other terminal of which constitutes an output terminal 20 of the device connected to the set of conductive strips with which the device is associated.

Les grilles des transistors MP et MN reçoivent des signaux de commande décalés dans le temps, respectivement CP et CN, pour permettre la commutation de la sortie 20 du dispositif entre le potentiel VAh et la masse. Ces signaux de commande CP et CN sont des signaux à deux états. Les signaux CP et CN sont dans un état bas pendant le temps de trame de la couleur à laquelle le dispositif est associé et dans un état haut pendant les temps de trame des deux autres couleurs. Les états, respectivement bas et haut, des signaux CP et CN sont, par exemple, de 0 et 5 volts.The gates of the transistors MP and MN receive time-shifted control signals, respectively C P and C N , to allow the switching of the output 20 of the device between the potential V Ah and the ground. These control signals C P and C N are two-state signals. The signals C P and C N are in a low state during the frame time of the color with which the device is associated and in a high state during the frame times of the other two colors. The states low and high, respectively, of the signals C P and C N are, for example, 0 and 5 volts.

Les signaux CP et CN sont envoyés sur des bornes de commande, respectivement 21 et 22. La grille du transistor MP est reliée, par l'intermédiaire d'une résistance R3 montée en série avec un condensateur C1, à la borne 21. La grille du transistor MN est reliée, par l'intermédiaire d'une résistance R4, à la borne 22. La grille du transistor MP est de plus connectée au potentiel VAh par l'intermédiaire d'une diode Zener DZ1 et d'une résistance R2 montées en parallèle.The signals C P and C N are sent to control terminals, respectively 21 and 22. The gate of the transistor MP is connected, via a resistor R 3 connected in series with a capacitor C 1 , to the terminal 21. The gate of transistor MN is connected, via a resistor R 4 , to terminal 22. The gate of transistor MP is also connected to potential V Ah via a Zener diode D Z1 and a resistor R 2 connected in parallel.

La commutation de la sortie 20 du dispositif entre le potentiel VAh et la masse s'effectue sur les fronts des signaux CP et CN. Le condensateur C1 sert à permettre une commutation du transistor MP à partir du signal de commande CP dont les potentiels sont référencés à la masse et non à VAh.The switching of the output 20 of the device between the potential V Ah and the ground takes place on the edges of the signals C P and C N. The capacitor C 1 is used to allow switching of the transistor MP from the control signal C P whose potentials are referenced to ground and not to V Ah .

Pour que le transistor MP soit rendu passant, il faut que le potentiel de sa grille soit porté à une valeur inférieure au potentiel VAh. En supposant le transistor MP bloqué, un front descendant du signal CP est transmis, sous la forme d'une impulsion, par le condensateur C1 sur la grille du transistor MP ce qui le rend passant. L'apparition du front suivant (montant) du signal CP provoque, à l'inverse, le blocage du transistor MP en portant sa grille à un potentiel égal au potentiel VAh. La diode Zener DZ1 a pour rôle de protéger le transistor MP en limitant la différence de potentiel entre sa grille et sa source à une valeur correspondant à la valeur de la diode Zener, par exemple 4,7 volts. La diode Zener DZ1 a aussi pour rôle d'éviter que la tension de grille ne dépasse sensiblement VAh. For the transistor MP to be turned on, the potential of its gate must be brought to a value lower than the potential V Ah . Assuming the transistor MP blocked, a falling edge of the signal C P is transmitted, in the form of a pulse, by the capacitor C 1 on the gate of the transistor MP which makes it conducting. The appearance of the next (rising) edge of the signal C P causes, conversely, the blocking of the transistor MP by bringing its gate to a potential equal to potential V Ah . The role of the Zener diode D Z1 is to protect the transistor MP by limiting the potential difference between its gate and its source to a value corresponding to the value of the Zener diode, for example 4.7 volts. The role of the Zener diode Z Z1 is also to prevent the gate voltage from substantially exceeding V Ah.

Une condition doit cependant être respectée pour que les fronts du signal CP puissent provoquer la commutation du transistor MP. Il faut que la constante de temps, engendrée par la capacité de grille du transistor MP associée à la résistance R2, soit supérieure à la constante de temps apportée par l'association de la résistance R3 avec le condensateur C1 et la capacité de grille du transistor MP. En d'autres termes, les valeurs des résistances R2 et R3 et du condensateur C1 sont choisies pour que la condition R2Cg > R3(C1 + Cg), où Cg représente la capacité de grille du transistor MP, soit respectée.A condition must however be met so that the edges of the signal C P can cause the switching of the transistor MP. The time constant, generated by the gate capacitance of the transistor MP associated with the resistor R 2 , must be greater than the time constant provided by the association of the resistor R 3 with the capacitor C 1 and the capacitance of gate of the transistor MP. In other words, the values of resistors R 2 and R 3 and of capacitor C 1 are chosen so that the condition R 2 C g > R 3 (C 1 + C g ), where C g represents the gate capacity of the MP transistor, be respected.

Le transistor MN est quant à lui commandé par le signal CN. Comme le transistor MN est à canal N et que sa source est reliée à la masse, le signal CN peut être appliqué sur sa grille sans recours à un condensateur. Lorsque le signal CN est dans un état haut (par exemple 5 volts), le transistor MN est passant car le potentiel de sa grille est supérieur au potentiel de sa source. Lorsque le signal CN est à la masse, le transistor MN est, à l'inverse, bloqué.The transistor MN is in turn controlled by the signal C N. As the transistor MN is an N channel and its source is connected to ground, the signal C N can be applied to its gate without using a capacitor. When the signal C N is in a high state (for example 5 volts), the transistor MN is on because the potential of its gate is greater than the potential of its source. When the signal C N is at ground, the transistor MN is, on the contrary, blocked.

Un inconvénient des écrans couleurs classiques est que, lors de la polarisation d'un ensemble de bandes d'une couleur donnée, on assiste à une émission parasite des deux autres couleurs.A disadvantage of conventional color screens is that, during the polarization of a set of bands of a given color, there is a spurious emission of the other two colors.

Ce phénomène est illustré par la figure 3 qui représente schématiquement et en coupe le long d'une rangée de la grille 3, un pixel de l'écran. Sur cette figure, seules quelques micropointes 2 ont été représentées pour des raisons de clarté alors qu'elles sont, en pratique, au nombre de plusieurs milliers par pixel de l'écran.This phenomenon is illustrated by FIG. 3 which shows schematically and in section along a row of the grid 3, a pixel of the screen. In this figure, only a few microtips 2 have been shown for reasons of clarity, although they are, in practice, several thousand per pixel of the screen.

On suppose que l'on est dans une trame verte où les bandes conductrices 9g portant les éléments luminophores verts 7g sont adressées en étant polarisées à un potentiel positif, par exemple de 400 volts, tandis que les bandes conductrices 9r et 9b portant, respectivement, les éléments luminophores rouges 7r et bleus 7b sont au repos en étant à un potentiel nul.We suppose that we are in a green frame where the conductive strips 9g carrying the green phosphor elements 7g are addressed by being polarized at a positive potential, for example of 400 volts, while the conductive strips 9r and 9b carrying, respectively, the red phosphor elements 7r and blue 7b are at rest while being at zero potential.

Lors de l'émission électronique par les micropointes 2 d'un pixel donné, on constate que certains électrons parasites ne sont pas collectés par les éléments luminophores verts 7g mais par les éléments luminophores rouges 7r ou bleus 7b de ce pixel, voire des pixels voisins dans la direction des rangées de la grille 3. Ce bombardement parasite est dû à une charge résiduelle des éléments luminophores rouges et bleus alors même que les bandes conductrices, respectivement 9r et 9b, qui les portent sont à un potentiel nul. En effet, il existe des capacités parasites entre les éléments luminophores et la bande conductrice qui les portent. De ce fait, même lorsque la bande conductrice est ramenée à la masse, des éléments luminophores peuvent rester polarisés à un potentiel supérieur au potentiel minimal (0 volts) de polarisation des micropointes en raison de ces capacités parasites et du fort potentiel (de l'ordre de 400 volts) d'adressage. Le phénomène de bombardement parasite peut être accru par un effet balistique qui conduit à ce que certains électrons émis par les micropointes en regard des bandes rouges ou bleues n'ont pas le temps d'être déviés pour être collectés par les éléments luminophores verts. A la figure 3, le trajet des électrons a été représenté symboliquement par des flèches, le trajet des électrons parasites étant symbolisé par des pointillés.During the electronic emission by the microtips 2 of a given pixel, it is noted that certain parasitic electrons are not collected by the green phosphor elements 7g but by the red phosphor elements 7r or blue 7b of this pixel, or even neighboring pixels in the direction of the rows of the grid 3. This parasitic bombardment is due to a residual charge of the red and blue phosphor elements even though the conductive strips, respectively 9r and 9b, which carry them are at zero potential. Indeed, there are parasitic capacitances between the phosphor elements and the conductive strip which carry them. Therefore, even when the conductive strip is brought to ground, phosphor elements can remain polarized at a potential greater than the minimum potential (0 volts) of polarization of the microtips due to these parasitic capacities and the high potential (of the order of 400 volts) of addressing. The parasitic bombardment phenomenon can be increased by a ballistic effect which leads to the fact that certain electrons emitted by the microtips facing the red or blue bands do not have time to be deflected to be collected by the green phosphor elements. In FIG. 3, the path of the electrons has been represented symbolically by arrows, the path of the parasitic electrons being symbolized by dotted lines.

La présente invention vise à pallier cet inconvénient en proposant un écran plat de visualisation à micropointes dans lequel les bandes conductrices de l'anode qui portent des éléments luminophores sont commutées d'une manière telle que les électrons émis par les micropointes sont effectivement tous collectés par les éléments luminophores de la couleur souhaitée.The present invention aims to overcome this drawback by proposing a flat microtip display screen in which the conductive strips of the anode which carry phosphor elements are switched in such a way that the electrons emitted by the microtips are effectively all collected by the phosphor elements of the desired color.

Un autre objet de la présente invention est de permettre une telle commutation en utilisant les tensions d'alimentation qui sont classiquement disponibles au sein du circuit de commande de l'écran.Another object of the present invention is to allow such switching by using the supply voltages which are conventionally available within the screen control circuit.

Pour atteindre ces objets, la présente invention prévoit un écran plat de visualisation du type comportant une cathode de bombardement électronique d'une anode pourvue d'au moins deux ensembles de bandes conductrices alternées portant des éléments luminophores et un circuit de commande propre à adresser séquentiellement chacun desdits ensembles, caractérisé en ce que ledit circuit de commande comporte des moyens pour porter, au moins temporairement, chaque ensemble de bandes conductrices à un potentiel inférieur à un potentiel minimal de polarisation de la cathode.To achieve these objects, the present invention provides a flat display screen of the type comprising an electron bombardment cathode of an anode provided with at least two sets of alternating conductive strips carrying phosphor elements and a control circuit capable of addressing sequentially. each of said assemblies, characterized in that said control circuit comprises means for bringing, at least temporarily, each set of conductive strips to a potential lower than a minimum bias potential of the cathode.

Selon un mode de réalisation de l'invention, lesdits moyens comportent, pour chaque ensemble de bandes conductrices, un dispositif de commutation entre un potentiel positif d'adressage de l'ensemble associé au dispositif et un potentiel de repos inférieur au potentiel minimal de polarisation de la cathode.According to one embodiment of the invention, said means comprise, for each set of conductive strips, a switching device between a positive addressing potential of the assembly associated with the device and a rest potential lower than the minimum bias potential of the cathode.

Selon un mode de réalisation de l'invention, ledit potentiel minimal de polarisation de la cathode correspond à la masse, ledit potentiel de repos d'un ensemble de bandes conductrices étant négatif.According to one embodiment of the invention, said minimum bias potential of the cathode corresponds to the ground, said quiescent potential of a set of conductive strips being negative.

Selon un mode de réalisation de l'invention, lesdits moyens comportent, pour chaque ensemble de bandes conductrices, un dispositif de commutation entre un potentiel positif d'adressage de l'ensemble associé au dispositif et un potentiel de repos égal au potentiel minimal de polarisation des micropointes de la cathode, ledit dispositif comportant des moyens pour utiliser la transition entre le potentiel d'adressage et le potentiel de repos d'un ensemble de bandes conductrices pour provoquer une impulsion à un potentiel inférieur au potentiel minimal de polarisation de la cathode sur un autre ensemble de bandes conductrices.According to one embodiment of the invention, said means comprise, for each set of conductive strips, a device for switching between a positive addressing potential of the set associated with the device and a rest potential equal to the minimum bias potential cathode microtips, said device comprising means for using the transition between the addressing potential and the resting potential of a set of conductive strips to cause an impulse at a potential lower than the potential minimum polarization of the cathode on another set of conductive strips.

Selon un mode de réalisation de l'invention, un dispositif de commutation comporte deux transistors MOS dont les grilles respectives reçoivent des signaux de commande appropriés, le drain d'un premier transistor à canal P constituant une borne de sortie du dispositif destinée à être raccordée, par l'intermédiaire d'une première résistance, à un ensemble de bandes conductrices portant des éléments luminophores, la source dudit premier transistor étant connectée audit potentiel positif d'adressage et sa grille étant reliée, par l'intermédiaire d'une première diode Zener montée en parallèle avec une deuxième résistance, audit potentiel positif d'adressage et, par l'intermédiaire d'une troisième résistance montée en série avec un premier condensateur, à une première borne de commande recevant un premier signal à deux états.According to one embodiment of the invention, a switching device comprises two MOS transistors, the respective gates of which receive appropriate control signals, the drain of a first P-channel transistor constituting an output terminal of the device intended to be connected , via a first resistor, to a set of conductive strips carrying phosphor elements, the source of said first transistor being connected to said positive addressing potential and its gate being connected, via a first diode Zener connected in parallel with a second resistor, to said positive addressing potential and, via a third resistor connected in series with a first capacitor, to a first control terminal receiving a first two-state signal.

Selon un mode de réalisation de l'invention, le drain d'un second transistor à canal N est relié au drain dudit premier transistor, la source dudit second transistor étant connectée au potentiel de repos et sa grille étant reliée, par l'intermédiaire d'une quatrième résistance montée en série avec un second condensateur, à une seconde borne de commande recevant un second signal à deux états et, par l'intermédiaire d'une seconde diode Zener montée en parallèle avec une cinquième résistance, audit potentiel de repos.According to one embodiment of the invention, the drain of a second N-channel transistor is connected to the drain of said first transistor, the source of said second transistor being connected to the quiescent potential and its gate being connected, via a fourth resistor connected in series with a second capacitor, to a second control terminal receiving a second two-state signal and, via a second Zener diode connected in parallel with a fifth resistor, to said quiescent potential.

Selon un mode de réalisation de l'invention, le drain d'un second transistor à canal N est relié, par l'intermédiaire d'une seconde diode Zener, à la borne de sortie du dispositif, la source dudit second transistor étant connectée à la masse et sa grille étant reliée, par l'intermédiaire d'une quatrième résistance, à une seconde borne de commande recevant un second signal à deux états, l'amplitude maximale des impulsions négatives étant fixée par la valeur de la seconde diode Zener.According to one embodiment of the invention, the drain of a second N-channel transistor is connected, via a second Zener diode, to the output terminal of the device, the source of said second transistor being connected to the ground and its grid being connected, via a fourth resistor, to a second control terminal receiving a second two-state signal, the maximum amplitude of the negative pulses being fixed by the value of the second Zener diode.

Selon un mode de réalisation de l'invention, une cinquième résistance de forte valeur est placée en parallèle avec ladite seconde diode Zener.According to an embodiment of the invention, a fifth resistor of high value is placed in parallel with said second Zener diode.

Selon un mode de réalisation de l'invention, l'écran plat de visualisation comporte trois ensembles de bandes conductrices alternées portant des éléments luminophores et correspondant chacun à une couleur et trois dispositifs de commutation, et en ce que les premiers signaux de commande respectivement associés aux dispositifs sont, successivement, dans un état haut pendant des temps de trame des couleurs auxquelles ils sont respectivement associés et, simultanément, à la masse pendant une durée prédéterminée entre deux trames couleur.According to one embodiment of the invention, the flat display screen comprises three sets of alternating conductive strips carrying phosphor elements and each corresponding to a color and three switching devices, and in that the first control signals respectively associated the devices are, successively, in a high state during frame times of the colors with which they are respectively associated and, simultaneously, at ground for a predetermined period between two color frames.

Selon un mode de réalisation de l'invention, la cathode est du type à micropointes.According to one embodiment of the invention, the cathode is of the microtip type.

Ces objets, caractéristiques et avantages, ainsi que d'autres de la présente invention seront exposés en détail dans la description suivante de modes de réalisation particuliers faite à titre non limitatif en relation avec les figures jointes parmi lesquelles :

  • les figures 1 à 3 qui ont été décrites précédemment sont destinées à exposer l'état de la technique et le problème posé ;
  • la figure 4 représente un premier mode de réalisation d'un dispositif de commutation d'une anode d'écran plat de visualisation selon l'invention ;
  • la figure 5 représente un deuxième mode de réalisation d'un dispositif de commutation d'une anode d'écran plat de visualisation selon l'invention ;
  • la figure 6 est un schéma électrique équivalent d'une anode d'écran couleur du point de vue capacitif ; et
  • la figure 7 représente des chronogrammes de différents signaux d'une anode d'écran couleur commutée au moyen de dispositifs tels que représentés à la figure 5.
These objects, characteristics and advantages, as well as others of the present invention will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:
  • Figures 1 to 3 which have been described above are intended to show the state of the art and the problem posed;
  • FIG. 4 shows a first embodiment of a switching device for a flat display screen anode according to the invention;
  • FIG. 5 represents a second embodiment of a switching device for a flat display screen anode according to the invention;
  • FIG. 6 is an equivalent electrical diagram of a color screen anode from the capacitive point of view; and
  • FIG. 7 represents chronograms of different signals of a color screen anode switched by means of devices as shown in FIG. 5.

Pour des raisons de clarté, les représentations des figures ne sont pas à l'échelle et les mêmes éléments ont été désignés par les mêmes références aux différentes figures.For reasons of clarity, the representations of the figures are not to scale and the same elements have been designated by the same references in the different figures.

L'idée mère de la présente invention est d'assurer une inhibition de la faculté d'attraction des éléments luminophores portés par des bandes conductrices (9 en figure 1) qui ne sont pas adressées en appliquant à ces bandes, au moins temporairement, un potentiel inférieur au potentiel minimal de polarisation des micropointes de la cathode et supprimer ainsi toute charge résiduelle des éléments luminophores portés par ces bandes.The main idea of the present invention is to ensure an inhibition of the faculty of attraction of the phosphor elements carried by conductive bands (9 in FIG. 1) which are not addressed by applying to these bands, at least temporarily, a potential lower than the minimum polarization potential of the cathode microtips and thus remove any residual charge from the phosphor elements carried by these bands.

La figure 4 illustre un premier mode de réalisation d'un dispositif de commutation d'une anode selon l'invention.FIG. 4 illustrates a first embodiment of a device for switching an anode according to the invention.

Le potentiel de repos des bandes d'éléments luminophores est un potentiel VAl inférieur au potentiel minimal de polarisation des micropointes de cathode. Dans l'exemple considéré où les colonnes de la cathode sont polarisées entre 0 et 30 volts en fonction de la brillance souhaitée pour le pixel dans la couleur considérée, on choisit un potentiel VAl négatif. Ainsi, seules les éléments luminophores dont les bandes conductrices sont adressées, c'est-à-dire portées à un potentiel d'adressage positif VAh (par exemple de l'ordre de 400 volts) sont susceptibles de recevoir des électrons émis par les micropointes.The quiescent potential of the strips of phosphor elements is a potential V Al less than the minimum potential of polarization of the cathode microtips. In the example considered where the cathode columns are polarized between 0 and 30 volts depending on the desired brightness for the pixel in the color considered, a negative potential V A1 is chosen. Thus, only the phosphor elements whose conductive bands are addressed, that is to say brought to a positive addressing potential V Ah (for example of the order of 400 volts) are capable of receiving electrons emitted by the microtips.

Un dispositif de commutation selon ce premier mode de réalisation comprend deux transistors MOS de puissance MP et MN dont les drains sont reliés à une première borne d'une première résistance R1 dont l'autre borne constitue une sortie 20 du dispositif à laquelle est reliée un ensemble de bandes conductrices portant des éléments luminophores. Un premier transistor à canal P MP a, comme précédemment, sa source connectée au potentiel d'adressage VAh. La grille du transistor MP est connectée, par l'intermédiaire d'une première diode Zener DZ1 montée en parallèle avec une deuxième résistance R2, au potentiel d'adressage VAh et, par l'intermédiaire d'une troisième résistance R3 montée en série avec un premier condensateur C1, à une première borne 21 recevant un premier signal de commande CP.A switching device according to this first embodiment comprises two MOS transistors of power MP and MN, the drains of which are connected to a first terminal of a first resistor R 1 , the other terminal of which constitutes an output 20 of the device to which is connected a set of conductive strips carrying phosphor elements. A first P channel transistor MP has, as before, its source connected to the addressing potential V Ah . The gate of the transistor MP is connected, via a first Zener diode D Z1 mounted in parallel with a second resistor R 2 , to the addressing potential V Ah and, via a third resistor R 3 connected in series with a first capacitor C 1 , at a first terminal 21 receiving a first control signal C P.

Selon l'invention, un montage similaire est reproduit pour un second transistor à canal N MN, sa source étant connectée au potentiel de repos VAl. En d'autres termes, la grille du transistor MN est reliée, par l'intermédiaire d'une quatrième résistance R4 montée en série avec un second condensateur C2, à une seconde borne de commande 22 recevant un second signal de commande CN. La grille du transistor MN est de plus reliée, par l'intermédiaire d'une seconde diode Zener DZ2 montée en parallèle avec une cinquième résistance R5, au potentiel de repos VAl.According to the invention, a similar arrangement is reproduced for a second N-channel transistor MN, its source being connected to the quiescent potential V Al . In other words, the gate of transistor MN is connected, via a fourth resistor R 4 connected in series with a second capacitor C 2 , to a second control terminal 22 receiving a second control signal C N . The gate of transistor MN is also connected, via a second Zener diode D Z2 connected in parallel with a fifth resistor R 5 , to the quiescent potential V Al .

Les signaux de commande CP et CN correspondent aux signaux utilisés pour la commutation des dispositifs classiques et sont donc des signaux inversés l'un par rapport à l'autre et à deux états (par exemple 0 et 5 volts). Le rôle du condensateur C2 est de permettre une commutation du transistor MN dont la source est à un potentiel négatif au moyen du signal CN qui est, comme précédemment, un signal dont l'état bas est à la masse.The control signals C P and C N correspond to the signals used for the switching of conventional devices and are therefore signals inverted with respect to each other and in two states (for example 0 and 5 volts). The role of the capacitor C 2 is to allow switching of the transistor MN whose source is at a negative potential by means of the signal C N which is, as before, a signal whose low state is grounded.

Pour que le transistor MN soit rendu passant, il faut que le potentiel de sa grille soit porté à une valeur supérieure au potentiel VAl. En supposant le transistor MN bloqué, un front montant du signal CN est transmis, sous la forme d'une impulsion, par le condensateur C2 sur la grille du transistor MN ce qui le rend passant. La diode Zener DZ2 a pour rôle de protéger le transistor MN en limitant la différence de potentiel entre sa grille et sa source à une valeur correspondant à la valeur de la diode Zener, par exemple 4,7 volts. L'apparition du front suivant (descendant) du signal CN provoque, à l'inverse, le blocage du transistor MN en portant sa grille à un potentiel égal ou légèrement inférieur au potentiel VAl.For the transistor MN to be turned on, the potential of its gate must be brought to a value greater than the potential V Al . Assuming the transistor MN blocked, a rising edge of the signal C N is transmitted, in the form of a pulse, by the capacitor C 2 on the gate of the transistor MN which makes it conducting. The role of the Zener diode D Z2 is to protect the transistor MN by limiting the potential difference between its gate and its source to a value corresponding to the value of the Zener diode, for example 4.7 volts. The appearance of the next (falling) edge of the signal C N causes, conversely, the blocking of the transistor MN by bringing its gate to a potential equal to or slightly lower than the potential V Al .

Comme pour le transistor MP, une condition doit cependant être respectée pour que les fronts du signal CN puissent provoquer la commutation du transistor MN. On veillera à que la constante de temps, engendrée par la capacité de grille du transistor MN associée à la résistance R5, soit supérieure à la constante de temps apportée par l'association de la résistance R4 avec le condensateur C2 et la capacité de grille du transistor MN. En d'autres termes, les valeurs des résistances R4 et R5 et du condensateur C2 sont choisies pour que la condition R5Cg > R4(C2 + Cg), où Cg représente la capacité de grille du transistor MN, soit respectée.As for the transistor MP, a condition must however be respected so that the edges of the signal C N can cause switching of transistor MN. It will be ensured that the time constant, generated by the gate capacitance of the transistor MN associated with the resistor R 5 , is greater than the time constant provided by the association of the resistor R 4 with the capacitor C 2 and the capacitor gate of transistor MN. In other words, the values of resistors R 4 and R 5 and of capacitor C 2 are chosen so that the condition R 5 C g > R 4 (C 2 + C g ), where C g represents the gate capacity of the transistor MN, be respected.

Un dispositif tel que représenté à la figure 4 est reproduit pour chaque ensemble de bandes d'éléments luminophores de l'anode.A device as shown in FIG. 4 is reproduced for each set of bands of phosphor elements of the anode.

Ainsi, lorsque qu'un ensemble n'est plus adressé, le transistor MN du dispositif qui lui est associé conduit et les bandes conductrices de cet ensemble se trouvent alors au potentiel négatif VAl. On supprime ainsi aux éléments luminophores portés par ces bandes, toute faculté à capter des électrons émis par les micropointes en accélérant la décharge des capacités parasites entre ces éléments luminophores et la bande qui les portent.Thus, when an assembly is no longer addressed, the transistor MN of the device associated with it conducts and the conductive strips of this assembly are then at the negative potential V Al . This eliminates the phosphor elements carried by these bands, any ability to capture electrons emitted by the microtips by accelerating the discharge of stray capacitances between these phosphor elements and the band which carry them.

Selon l'invention, le potentiel VAl est choisi nettement inférieur au potentiel minimal de polarisation des micropointes. La valeur du potentiel VAl est, par exemple, comprise entre -100 et -200 volts.According to the invention, the potential V Al is chosen to be much lower than the minimum potential for polarization of the microtips. The value of the potential V Al is, for example, between -100 and -200 volts.

A titre d'exemple particulier de réalisation, un dispositif de commutation tel que représenté à la figure 4 peut être réalisé avec des composants présentant les valeurs suivantes pour un potentiel d'adressage VAh de l'ordre de 400 volts et un potentiel de repos VAl de l'ordre de -200 volts :

R1, R3, R4 :
1 kΩ ;
R2, R5 :
470 kΩ ;
C1, C2:
10 nF ; et
DZ1, DZ2 :
4,7 volts.
As a specific embodiment, a switching device as shown in FIG. 4 can be produced with components having the following values for an addressing potential V Ah of the order of 400 volts and a resting potential V Al of the order of -200 volts:
R 1 , R 3 , R 4 :
1 kΩ;
R 2 , R 5 :
470 kΩ;
C 1 , C 2 :
10 nF; and
D Z1 , D Z2 :
4.7 volts.

La figure 5 illustre un deuxième mode de réalisation d'un dispositif de commutation d'une anode selon l'invention. Ce dispositif se distingue du dispositif représenté à la figure 4 par le fait qu'il ne requiert pas de disposer d'une tension d'alimentation fortement négative pour servir de potentiel de repos des bandes conductrices qui ne sont pas adressées.FIG. 5 illustrates a second embodiment of a device for switching an anode according to the invention. This device differs from the device shown in FIG. 4 by the fact that it does not require having a strongly negative supply voltage to serve as the rest potential of the conductive strips which are not addressed.

Selon ce deuxième mode de réalisation, on profite de l'existence d'un couplage capacitif entre deux bandes conductrices voisines pour obtenir des impulsions négatives lors des commutations.According to this second embodiment, advantage is taken of the existence of a capacitive coupling between two neighboring conductive strips to obtain negative pulses during the switching operations.

En effet, deux bandes conductrices voisines d'un écran couleur présentent entre elles une capacité. Les capacités regroupées par l'interconnexion des bandes portant des éléments luminophores de même couleur conduisent à ce que, du point de vue du circuit de commande, les ensembles de bandes de l'anode sont reliés deux à deux par une capacité résultante.Indeed, two conductive strips adjacent to a color screen have a capacitance between them. The capacities grouped by the interconnection of the bands carrying phosphor elements of the same color lead to the fact that, from the point of view of the control circuit, the sets of bands of the anode are connected two by two by a resulting capacity.

La figure 6 représente le schéma électrique équivalent simplifié d'une anode d'un écran couleur, du point de vue capacitif. Les capacités résultantes, respectivement CGB, CBR et CRG, entre les ensembles de bandes conductrices de l'anode forment un réseau en triangle dont les sommets correspondent aux bornes de connexion de chacune des couleurs, respectivement G, B et R. Les bornes G, B et R sont chacune connectées à une borne de sortie 20 d'un dispositif de commutation selon l'invention.FIG. 6 represents the simplified equivalent electrical diagram of an anode of a color screen, from the capacitive point of view. The resulting capacitors, respectively C GB , C BR and C RG , between the sets of conductive strips of the anode form a triangle network whose vertices correspond to the connection terminals of each of the colors, respectively G, B and R. terminals G, B and R are each connected to an output terminal 20 of a switching device according to the invention.

En raison du couplage en triangle, une commutation d'un ensemble de bandes conductrices vers un potentiel de repos en fin d'adressage de cet ensemble induit, par le couplage capacitif, une impulsion négative sur les deux autres ensembles de bandes. Dans les dispositifs de commutation classiques, on cherche à minimiser ces impulsions négatives au moyen du transistor à canal N (MN, figure 1) relié à la masse.Because of the triangle coupling, a switching of a set of conductive strips towards a resting potential at the end of addressing of this set induces, by the capacitive coupling, a negative pulse on the two other sets of strips. In conventional switching devices, attempts are made to minimize these negative pulses by means of the N-channel transistor (MN, FIG. 1) connected to ground.

A l'inverse, selon le deuxième mode de réalisation de l'invention, on cherche à favoriser ces impulsions négatives pour provoquer une décharge optimale des éléments luminophores ayant été adressés et éviter ainsi que les éléments luminophores portés par des bandes non adressées collectent des électrons.Conversely, according to the second embodiment of the invention, it is sought to favor these negative pulses to cause an optimal discharge of the phosphor elements having been addressed and thus to avoid the phosphor elements carried by unaddressed bands collect electrons.

Comme le montre la figure 5, un dispositif de commutation selon ce deuxième mode de réalisation comporte deux transistors MOS de puissance MP et MN. Comme précédemment, un dispositif est associé à chaque ensemble de bandes conductrices portant des éléments luminophores. En d'autres termes, les bornes R, G et B de la figure 6 sont chacune raccordées à une borne 20 d'un dispositif tel que représenté à la figure 5.As shown in FIG. 5, a switching device according to this second embodiment comprises two MOS transistors of power MP and MN. As before, a device is associated with each set of conductive strips carrying phosphor elements. In other words, the terminals R, G and B of FIG. 6 are each connected to a terminal 20 of a device as shown in FIG. 5.

Le montage associé à un premier transistor à canal P MP est similaire à celui du premier mode de réalisation.The assembly associated with a first P MP channel transistor is similar to that of the first embodiment.

Selon l'invention, un deuxième transistor à canal N MN est relié, par sa grille et par l'intermédiaire d'une quatrième résistance R4, à une seconde borne de commande 22 recevant un second signal de commande CN à deux états, décalé dans le temps par rapport au signal CP. La source du transistor MN est connectée à la masse M qui correspond ici au potentiel minimal de polarisation des micropointes de la cathode. Le drain du transistor MN est relié à la borne de sortie 20 par l'intermédiaire d'une cinquième résistance R5 de forte valeur montée en parallèle avec une seconde diode Zener DZ2.According to the invention, a second N-channel transistor MN is connected, by its gate and via a fourth resistor R 4 , to a second control terminal 22 receiving a second control signal C N with two states, shifted in time with respect to the signal C P. The source of transistor MN is connected to ground M which here corresponds to the minimum potential for polarization of the microtips of the cathode. The drain of the transistor MN is connected to the output terminal 20 via a fifth resistor R 5 of high value mounted in parallel with a second Zener diode D Z2 .

Le rôle de la diode DZ2 est de permettre une commutation de la borne 20 entre le potentiel VAh et la masse M à la fin de l'adressage de l'ensemble de bandes auquel le dispositif est associé. La diode DZ2 permet également d'empêcher qu'un ensemble de bandes ne devant pas être adressé soit porté à un potentiel positif par les fronts de montée des deux autres ensembles sous l'effet du couplage capacitif.The role of the diode D Z2 is to allow switching of the terminal 20 between the potential V Ah and the ground M at the end of the addressing of the set of bands with which the device is associated. The diode D Z2 also makes it possible to prevent a set of bands which should not be addressed from being brought to a positive potential by the rising edges of the other two sets under the effect of the capacitive coupling.

Le rôle de la résistance R5 de forte valeur est de limiter l'absorption du courant négatif, dû au couplage capacitif, lors de la fin de l'adressage de l'ensemble de bandes et de ralentir ainsi l'amortissement des impulsions négatives sur les deux autres ensembles de bandes.The role of the resistor R 5 of high value is to limit the absorption of the negative current, due to the capacitive coupling, at the end of the addressing of the set of bands and thus to slow down the damping of the negative pulses on the other two sets of bands.

Le fonctionnement du dispositif de commutation sera mieux compris en relation avec la description de la figure 7 qui suit.The operation of the switching device will be better understood in relation to the description of FIG. 7 which follows.

Les signaux de commande associés aux différents dispositifs sont réalisés de manière à ce qu'il subsiste, entre chaque temps de trame couleur, une période pendant laquelle tous les transistors MP sont bloqués. En d'autres termes, on prévoit, lors de l'établissement des signaux de commande, un intervalle de temps entre deux trames couleur successives pendant lequel on favorise les impulsions négatives.The control signals associated with the various devices are produced so that there remains, between each color frame time, a period during which all of the MP transistors are blocked. In other words, there is provided, during the establishment of the control signals, a time interval between two successive color frames during which the negative pulses are favored.

Un avantage de ce deuxième mode de réalisation est qu'il ne nécessite aucune tension d'alimentation supplémentaire.An advantage of this second embodiment is that it does not require any additional supply voltage.

La figure 7 illustre, sous forme de chronogrammes, le fonctionnement d'une anode d'écran couleur au moyen de dispositifs de commutation tels que représentés à la figure 6. La figure 7 représente, pendant deux intervalles de temps Im(i) et Im(i+1) correspondant au temps d'affichage de deux images, la forme des signaux présents sur les bornes R, G et B d'interconnexion des bandes conductrices portant des éléments luminophores, respectivement, rouges, verts et bleus et la forme des signaux de commande, respectivement CPR, CPG et CPB associés aux dispositifs de commutation de ces ensembles. Les signaux de commande CN des dispositifs n'ont pas été représentés, ils correspondent aux signaux CP avec un décalage temporel. La commutation des rangées de la grille et des colonnes de la cathode à l'intérieur de chaque temps d'image est effectuée de manière classique.FIG. 7 illustrates, in the form of timing diagrams, the operation of a color screen anode by means of switching devices as shown in FIG. 6. FIG. 7 represents, for two time intervals Im (i) and Im (i + 1) corresponding to the display time of two images, the shape of the signals present on the terminals R, G and B of interconnection of the conductive strips carrying phosphor elements, respectively, red, green and blue and the shape of the control signals, respectively C PR , C PG and C PB associated with the switching devices of these assemblies. The control signals C N of the devices have not been shown, they correspond to the signals C P with a time offset. The switching of the rows of the grid and of the cathode columns within each image time is carried out in a conventional manner.

Pendant chaque temps d'image, les ensembles de bandes conductrices portant des éléments luminophores sont séquentiellement adressés en étant portés au potentiel VAh sous l'action des signaux de commande. Chaque signal CP comporte donc, à l'intérieur de chaque temps d'image, un palier à la masse d'une durée correspondant au temps de trame.During each image time, the sets of conductive strips carrying phosphor elements are sequentially addressed by being brought to the potential V Ah under the action of the control signals. Each signal C P therefore comprises, within each image time, a level at ground of a duration corresponding to the frame time.

On suppose que l'on se situe pendant un palier du signal CPR, c'est-à-dire pendant un temps de trame rouge. On suppose donc que le transistor MP du dispositif associé à la borne R est à l'état passant et que son transistor MN est bloqué tandis que les transistors MP des dispositifs, respectivement associés aux bornes B et G, sont bloqués et que les transistors MN de ces dispositifs sont à l'état passant.It is assumed that one is located during a plateau of the signal C PR , that is to say during a red frame time. It is therefore assumed that the transistor MP of the device associated with terminal R is in the conducting state and that its transistor MN is blocked while the transistors MP of the devices, respectively associated with terminals B and G, are blocked and that the transistors MN of these devices are in the on state.

Lors du front descendant du palier du signal CPR, le transistor MP du dispositif associé à la borne R se bloque tandis que le front montant du signal CN qui lui est associé provoque la conduction de son transistor MN. Par la présence de la diode Zener DZ2, le potentiel de la borne R est immédiatement ramené à la masse, la résistance R5 étant court-circuitée. Le front descendant du potentiel de la borne R provoque, en raison du couplage capacitif, une impulsion négative sur les bornes G et B, donc sur les bandes conductrices qui y sont associées. Les diodes DZ2 des dispositifs associés aux bornes G et B sont alors polarisées en inverse. Elles limitent cependant, par leur dimensionnement, l'amplitude VAl des impulsions négatives. Les résistances R5 des dispositifs associés aux bornes G et B introduisent, avec les capacités parasites, respectivement CRG et CBR, une constante de temps qui retarde l'amortissement de ces impulsions négatives, les transistors MN de ces dispositifs étant à l'état passant. Le cas échéant, la résistance R5 peut être omise et la résistance de fuite de la diode DZ2 remplit alors le rôle de limitation du courant négatif.During the falling edge of the plateau of signal C PR , the transistor MP of the device associated with terminal R is blocked while the rising edge of signal C N which is associated with it causes its transistor MN to conduce. By the presence of the Zener diode D Z2 , the potential of the terminal R is immediately reduced to ground, the resistor R 5 being short-circuited. The falling edge of the potential of terminal R causes, due to the capacitive coupling, a negative pulse on terminals G and B, therefore on the conductive strips which are associated therewith. The diodes D Z2 of the devices associated with the terminals G and B are then reverse biased. However, by their dimensioning, they limit the amplitude V Al of the negative pulses. The resistors R 5 of the devices associated with the terminals G and B introduce, with the parasitic capacitances, respectively C RG and C BR , a time constant which delays the damping of these negative pulses, the transistors MN of these devices being at passing state. If necessary, the resistance R 5 can be omitted and the leakage resistance of the diode D Z2 then fulfills the role of limiting the negative current.

Les impulsions négatives présentes sur les bornes G et B disparaissent, de toute façon, à l'apparition du front montant du signal CPG qui suit et qui a pour effet de porter la borne G au potentiel VAh pour adresser l'ensemble de bandes vertes.The negative pulses present on the terminals G and B disappear, in any case, at the appearance of the rising edge of the signal C PG which follows and which has the effect of bringing the terminal G to the potential V Ah to address the set of bands green.

A l'apparition du front montant du signal CPG, le potentiel de la borne G est immédiatement porté au potentiel d'adressage VAh par la mise en conduction du transistor MP du dispositif de commutation qui lui est associé et qui suit le blocage du transistor MN de ce dispositif. Les diodes Zener DZ2 des dispositifs de commutation associés, respectivement aux bornes B et R, qui sont alors polarisées en direct (les transistors MN de ces dispositifs sont à l'état passant) évitent l'apparition d'impulsions positives sur les bornes B et R, liées aux capacités parasites CGB et CRG. En l'absence de diodes Zener DZ2, ces impulsions positives s'amortiraient selon la constante de temps liée à l'association des résistances R5 de ces dispositifs avec les capacités, respectivement CGB et CRG.On the appearance of the rising edge of the signal C PG , the potential of the terminal G is immediately brought to the addressing potential V Ah by switching on the transistor MP of the switching device associated with it and which follows the blocking of the transistor MN of this device. The Zener diodes D Z2 of the associated switching devices, respectively at terminals B and R, which are then directly biased (the transistors MN of these devices are in the on state) prevent the appearance of positive pulses on the terminals B and R, linked to the parasitic capacities C GB and C RG . In the absence of Zener diodes D Z2 , these positive pulses would be damped according to the time constant linked to the association of the resistors R 5 of these devices with the capacitances, respectively C GB and C RG .

On est alors dans un temps de trame verte pendant toute la durée du palier positif du signal CPG.We are then in a green frame time throughout the duration of the positive plateau of the signal C PG .

Le fonctionnement qui a été décrit ci-dessus s'applique pour chaque palier d'un des signaux CPR, CPG ou CPB.The operation which has been described above applies for each stage of one of the signals C PR , C PG or C PB .

La durée t entre chaque palier est fixée en fonction de la durée souhaitée pour les impulsions négatives et des temps de trames souhaités. En effet, la présence de ces intervalles t pendant lesquels tous les transistors MP sont bloqués diminue le temps d'image disponible pour l'adressage des ensembles de bandes. A titre d'exemple particulier, pour des temps d'images de 10 ms qui correspondent à une fréquence de 100 Hz, on pourra choisir des intervalles t d'une durée comprise entre 10 µs et 1ms. Le temps de trame qui reste disponible est alors au minimum de 7ms ce qui est largement suffisant pour autoriser un adressage séquentiel de toutes les rangées de la grille pendant chaque temps de trame.The duration t between each level is fixed as a function of the desired duration for the negative pulses and of the desired frame times. In fact, the presence of these intervals t during which all of the transistors MP are blocked decreases the image time available for addressing the sets of bands. As a particular example, for image times of 10 ms which correspond to a frequency of 100 Hz, it will be possible to choose intervals t with a duration of between 10 μs and 1 ms. The frame time which remains available is then at least 7 ms, which is more than sufficient to allow sequential addressing of all the rows of the grid during each frame time.

L'amplitude maximale VAl des impulsions négatives est fixée par la valeur de la diode Zener. On choisira une valeur suffisamment importante (par exemple, comprise entre 100 et 200 volts) pour permettre des impulsions négatives suffisantes.The maximum amplitude V Al of the negative pulses is fixed by the value of the Zener diode. A value large enough (for example, between 100 and 200 volts) will be chosen to allow sufficient negative pulses.

Même si, selon ce mode de réalisation, les bandes portant des éléments luminophores qui ne sont pas adressées ne sont pas en permanence à un potentiel inférieur au potentiel minimal de polarisation des micropointes de la cathode, elles le sont temporairement, deux fois par période de repos. Cela suffit pour décharger complètement les éléments luminophores et pour éviter que des électrons parasites soient collectés par les éléments luminophores des bandes non adressées.Even if, according to this embodiment, the bands carrying phosphor elements which are not addressed are not permanently at a potential lower than the minimum potential for polarization of the microtips of the cathode, they are temporarily, twice per rest period. This is sufficient to completely discharge the phosphor elements and to prevent parasitic electrons from being collected by the phosphor elements of the unaddressed bands.

A titre d'exemple particulier de réalisation, pour un écran d'environ 15 cm de diagonale, avec un pas de pixel de 0,3 mm où les capacités CGB, CBR et CRG présentent des valeurs de l'ordre de 5 nF et pour un potentiel d'adressage VAh d'environ 400 volts, un dispositif de commutation tel que représenté à la figure 5 peut être réalisé avec des composants présentant les valeurs suivantes :

R1, R3, R4 :
1 kΩ ;
R2 :
470 kΩ ;
R5 :
100 kΩ à 1 MΩ ;
C1 :
10 nF ;
DZ1 :
4,7 volts ; et
DZ2 :
200 volts.
As a particular embodiment, for a screen of approximately 15 cm diagonal, with a pixel pitch of 0.3 mm where the capacities C GB , C BR and C RG have values of the order of 5 nF and for an addressing potential V Ah of approximately 400 volts, a switching device as shown in FIG. 5 can be produced with components having the following values:
R 1 , R 3 , R 4 :
1 kΩ;
R 2 :
470 kΩ;
R 5 :
100 kΩ to 1 MΩ;
K 1 :
10 nF;
D Z1 :
4.7 volts; and
D Z2 :
200 volts.

Bien entendu, la présente invention est susceptible de diverses variantes et modifications qui apparaîtront à l'homme de l'art. En particulier, chacun des composants décrits pourra être remplacé par un ou plusieurs éléments remplissant la même fonction. De même, les valeurs numériques données à titre d'exemple pourront être modifiées en fonction des caractéristiques de l'écran et de son circuit de commande. En outre, bien que l'on ait fait référence dans la description qui précède à un écran couleur, l'invention s'applique également à un écran monochrome pourvu de deux ensembles de bandes d'une même couleur.Of course, the present invention is susceptible of various variants and modifications which will appear to those skilled in the art. In particular, each of the components described may be replaced by one or more elements fulfilling the same function. Likewise, the numerical values given by way of example may be modified according to the characteristics of the screen and of its control circuit. In addition, although reference has been made in the preceding description to a color screen, the invention also applies to a monochrome screen provided with two sets of bands of the same color.

Claims (10)

Ecran plat de visualisation du type comportant une cathode (1) de bombardement électronique d'une anode (5) pourvue d'au moins deux ensembles de bandes conductrices alternées (9) portant des éléments luminophores (7) et un circuit de commande propre à adresser séquentiellement chacun desdits ensembles, caractérisé en ce que ledit circuit de commande comporte des moyens pour porter, au moins temporairement, chaque ensemble de bandes conductrices (9) à un potentiel (VAl) inférieur à un potentiel minimal de polarisation de la cathode (1)Flat display screen of the type comprising a cathode (1) for electronically bombarding an anode (5) provided with at least two sets of alternating conductive strips (9) carrying phosphor elements (7) and a control circuit specific to address each of said sets sequentially, characterized in that said control circuit comprises means for bringing, at least temporarily, each set of conductive strips (9) to a potential (V Al ) lower than a minimum bias potential of the cathode ( 1) Ecran plat de visualisation selon la revendication 1, caractérisé en ce lesdits moyens comportent, pour chaque ensemble de bandes conductrices (9), un dispositif de commutation entre un potentiel positif (VAh) d'adressage de l'ensemble associé au dispositif et un potentiel de repos (VAl) inférieur au potentiel minimal de polarisation de la cathode (1).Flat display screen according to claim 1, characterized in that said means comprise, for each set of conductive strips (9), a device for switching between a positive potential (V Ah ) for addressing the set associated with the device and a rest potential (V Al ) lower than the minimum bias potential of the cathode (1). Ecran plat de visualisation selon la revendication 2, caractérisé en ce que ledit potentiel minimal de polarisation de la cathode correspond à la masse (M), ledit potentiel de repos (VAl) d'un ensemble de bandes conductrices (9) étant négatif.Flat display screen according to claim 2, characterized in that said minimum cathode polarization potential corresponds to the mass (M), said rest potential (V Al ) of a set of conductive strips (9) being negative. Ecran plat de visualisation selon la revendication 1, caractérisé en ce que lesdits moyens comportent, pour chaque ensemble de bandes conductrices (9), un dispositif de commutation entre un potentiel positif (VAh) d'adressage de l'ensemble associé au dispositif et un potentiel de repos (M) égal au potentiel minimal de polarisation de micropointes (2) de la cathode (1), ledit dispositif comportant des moyens pour utiliser la transition entre le potentiel d'adressage (VAh) et le potentiel de repos (M) d'un ensemble de bandes conductrices (9) pour provoquer une impulsion à un potentiel (VAl) inférieur au potentiel minimal de polarisation de la cathode (1) sur un autre ensemble de bandes conductrices (9).Flat display screen according to claim 1, characterized in that said means comprise, for each set of conductive strips (9), a device for switching between a positive potential (V Ah ) for addressing the set associated with the device and a resting potential (M) equal to the minimum microdot polarization potential (2) of the cathode (1), said device comprising means for using the transition between the addressing potential (V Ah ) and the resting potential ( M) a set of conductive strips (9) to cause an impulse at a lower potential (V Al ) at the minimum bias potential of the cathode (1) on another set of conductive strips (9). Ecran plat de visualisation selon l'une quelconque des revendications 2 à 4, caractérisé en ce qu'un dispositif de commutation comporte deux transistors MOS (MP, MN) dont les grilles respectives reçoivent des signaux de commande (CP, CN) appropriés, le drain d'un premier transistor (MP) à canal P constituant une borne (20) de sortie du dispositif destinée à être raccordée, par l'intermédiaire d'une première résistance (R1), à un ensemble de bandes conductrices (9) portant des éléments luminophores (7), la source dudit premier transistor (MP) étant connectée audit potentiel positif d'adressage (VAh) et sa grille étant reliée, par l'intermédiaire d'une première diode Zener (DZ1) montée en parallèle avec une deuxième résistance (R2), audit potentiel positif d'adressage (VAh) et, par l'intermédiaire d'une troisième résistance (R3) montée en série avec un premier condensateur (C1), à une première borne de commande (21) recevant un premier signal (CP) à deux états.Flat display screen according to any one of Claims 2 to 4, characterized in that a switching device comprises two MOS transistors (MP, MN), the respective gates of which receive appropriate control signals (C P , C N ) , the drain of a first P-channel transistor (MP) constituting an output terminal (20) of the device intended to be connected, via a first resistor (R 1 ), to a set of conductive strips ( 9) carrying phosphor elements (7), the source of said first transistor (MP) being connected to said positive addressing potential (V Ah ) and its gate being connected, by means of a first Zener diode (D Z1 ) connected in parallel with a second resistor (R 2 ), at said positive addressing potential (V Ah ) and, via a third resistor (R 3 ) connected in series with a first capacitor (C 1 ), at a first control terminal (21) receiving a first s ignal (C P ) with two states. Ecran plat de visualisation selon les revendications 2 ou 3, et 5, caractérisé en ce que le drain d'un second transistor (MN) à canal N est relié au drain dudit premier transistor (MP), la source dudit second transistor (MN) étant connectée au potentiel de repos (VAl) et sa grille étant reliée, par l'intermédiaire d'une quatrième résistance (R4) montée en série avec un second condensateur (C2), à une seconde borne de commande (22) recevant un second signal (CN) à deux états et, par l'intermédiaire d'une seconde diode Zener (DZ2) montée en parallèle avec une cinquième résistance (R5), audit potentiel de repos (VAl).Flat display screen according to claims 2 or 3, and 5, characterized in that the drain of a second N-channel transistor (MN) is connected to the drain of said first transistor (MP), the source of said second transistor (MN) being connected to the rest potential (V Al ) and its grid being connected, via a fourth resistor (R 4 ) connected in series with a second capacitor (C2), to a second control terminal (22) receiving a second two-state signal (C N ) and, via a second Zener diode (DZ2) connected in parallel with a fifth resistor (R 5 ), to said quiescent potential (V Al ). Ecran plat de visualisation selon les revendications 4 et 5, caractérisé en ce que le drain d'un second transistor (MN) à canal N est relié, par l'intermédiaire d'une seconde diode Zener (DZ2), à la borne de sortie (20) du dispositif, la source dudit second transistor (MN) étant connectée à la masse (M) et sa grille étant reliée, par l'intermédiaire d'une quatrième résistance (R4), à une seconde borne de commande (22) recevant un second signal (CN) à deux états, l'amplitude maximale (VAl) des impulsions négatives étant fixée par la valeur de la seconde diode Zener (DZ2).Flat display screen according to Claims 4 and 5, characterized in that the drain of a second N-channel transistor (MN) is connected, via a second Zener diode (D Z2 ), to the terminal of output (20) of the device, the source of said second transistor (MN) being connected to the mass (M) and its grid being connected, via a fourth resistor (R 4 ), to a second control terminal (22) receiving a second signal (C N ) in two states, the maximum amplitude (V Al ) negative pulses being fixed by the value of the second Zener diode (D Z2 ). Ecran plat de visualisation selon la revendication 7, caractérisé en ce qu'une cinquième résistance (R5) de forte valeur est placée en parallèle avec ladite seconde diode Zener (DZ2) .Flat display screen according to claim 7, characterized in that a fifth resistor (R 5 ) of high value is placed in parallel with said second Zener diode (D Z2 ). Ecran plat de visualisation selon la revendication 7 ou 8, caractérisé en ce qu'il comporte trois ensembles de bandes conductrices (9) alternées portant des éléments luminophores (7) et correspondant chacun à une couleur et trois dispositifs de commutation, et en ce que les premiers signaux de commande (CP) respectivement associés aux dispositifs sont, successivement, dans un état haut pendant des temps de trame des couleurs auxquelles ils sont respectivement associés et, simultanément, à la masse (M) pendant une durée prédéterminée (t) entre deux trames couleur.Flat display screen according to claim 7 or 8, characterized in that it comprises three sets of alternating conductive strips (9) carrying phosphor elements (7) and each corresponding to a color and three switching devices, and in that the first control signals (C P ) respectively associated with the devices are, successively, in a high state during frame times of the colors with which they are respectively associated and, simultaneously, at ground (M) for a predetermined duration (t) between two color frames. Ecran plat de visualisation selon l'une quelconque des revendications précédentes, caractérisé en ce que la cathode est du type à micropointes.Flat display screen according to any one of the preceding claims, characterized in that the cathode is of the microtip type.
EP96410066A 1995-06-08 1996-06-04 Anode switching in a flat panel display Withdrawn EP0747874A1 (en)

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FR9507016A FR2735265B1 (en) 1995-06-08 1995-06-08 SWITCHING A FLAT DISPLAY ANODE
FR9507016 1995-06-08

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FR2735265A1 (en) 1996-12-13
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US6028574A (en) 2000-02-22

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