EP0744084A1 - Semiconductor storage component with a plurality of storage chips in a shared casing - Google Patents

Semiconductor storage component with a plurality of storage chips in a shared casing

Info

Publication number
EP0744084A1
EP0744084A1 EP95908875A EP95908875A EP0744084A1 EP 0744084 A1 EP0744084 A1 EP 0744084A1 EP 95908875 A EP95908875 A EP 95908875A EP 95908875 A EP95908875 A EP 95908875A EP 0744084 A1 EP0744084 A1 EP 0744084A1
Authority
EP
European Patent Office
Prior art keywords
carrier
memory chips
memory
module board
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP95908875A
Other languages
German (de)
French (fr)
Inventor
Ewald Michael
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0744084A1 publication Critical patent/EP0744084A1/en
Ceased legal-status Critical Current

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    • H01L23/495—Lead-frames or other flat leads
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
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Definitions

  • the invention relates to semiconductor memory components according to the preambles of claims 1 and 2 and to methods for producing the semiconductor memory components according to the preambles of claims 14 and 15.
  • SIMM Single in line memory module
  • the memory module equipped with memory modules is installed as a whole in the computer (soldered or plugged in) and also, if necessary, replaced or supplemented as a whole.
  • FIG. 1 shows a standard memory module (for example 4Mx9 DRAM) with the module board M, nine memory modules S (instead of DRAMS, SRAMs, E (E) PROM etc. would also be possible) and the module connections 1 to 30.
  • the module connections 1 to 30 are connected via electrical lines (not shown) to contact points to which the external connection points A of the memory modules S are fastened with plug connections or surface contacts (for example soldered).
  • the memory modules S are arranged here in two rows of four and five stones, but other configurations are also possible.
  • Figure 2 shows a typical memory chip.
  • the memory chip C is mounted on a carrier ⁇ (metal spider, foil etc.) by gluing, alloying etc. Between the contact points K of the memory chip C and the outer connection points A of
  • Carrier T-j_ has electrical connections B (e.g. gold wires) attached.
  • memory chip C and carrier T] _ are provided with a sheath U, which usually consists of plastic (alternatively, ceramic is used) and is either pre-molded or cast directly around carrier T] _ and chip C.
  • Carrier T] _ and casing U together with electrical connections B represent the housing of the memory chip C.
  • Figures 3a to 3c show a manufacturing step of the memory module shown in Figure 2, shown here in supervision.
  • FIG. 3a shows the carrier T-j_, which is also referred to as a spider because of its shape.
  • the memory chip C is fastened in the middle of the carrier T1. With A the outer connection points of the carrier T] _ are designated.
  • the memory chip C is connected to the external contact points K by connections which are not shown.
  • FIG. 3b shows the same structure that was provided with an envelope U (shown here only in outline).
  • envelope U shown here only in outline.
  • plastic covering is e.g. has been cast around the carrier T provided with the memory chip C, the outer connection points A of the carrier remaining free.
  • FIG. 3c shows the module after the outer connection points A have been bent downward for fastening and contacting, for example on a module board.
  • the memory modules produced in this way are also subjected to a functional test, automatic test machines being used today which can test several memory modules in parallel (for example T 5363 from ADVANTEST for 16 modules). The memory modules are then attached to the module board.
  • WO-A-81/02367 shows a generic arrangement.
  • a memory module is disclosed in which four identical memory chips are accommodated in a common housing, two being on the top and two on the bottom of a laminate carrier provided with lines. In order to keep the memory component compact, the four memory chips share a plurality of the outer connection points of the carrier, for example the address pins.
  • such memory modules have not been able to establish themselves on the mass market since they do not meet the memory module standards and are too expensive to manufacture due to the complex assembly of the memory chips in the module on a laminate carrier. These modules do not represent any progress for use in memory modules.
  • JP-A-60208851 discloses another semiconductor memory device.
  • the memory chips are attached directly to a memory board, provided with electrical connections and covered with a common cap. This arrangement was also unable to establish itself due to the disadvantages of the production process. Due to the direct mounting of the memory chips on the memory board, special boards have to be used, the testing of the memory chips (which can only be carried out after the chips have been electrically connected to the board) is made more difficult because memory chips that are recognized as defective can be used (since they are on the board soldered) are difficult to replace with functional, and the electrical connections between chips and circuit board are complex and expensive.
  • JP-OS 64-1270 also shows a generic semiconductor memory component.
  • contact points of the individual memory chips which carry the same data signals or potentials during operation, are each connected to a single external connection point.
  • this has the consequence that, viewed from a geometrical point of view, a special encapsulation is necessary which, with the number of connection points remaining approximately the same, is larger than the encapsulation used as standard for a single memory chip, so that the connection points have a geometrical arrangement and also the number (data input and / or data output signals for or from different memory chips cannot be assigned to one connection point at a time) does not correspond to the requirements which standardized boards for SIMM modules have, for example, with regard to the number and arrangement of the connection points.
  • the aim of the present invention is to provide a memory component which can be handled as simply and inexpensively as possible when used together with module boards, and largely standardized components can be used in its manufacture.
  • FIGS. 1 to 3 show a memory module and a memory module according to the prior art
  • FIGS. 4 to 9 show a first embodiment of the
  • FIGS. 10 to 14 show a second embodiment of the invention along with advantageous configurations.
  • FIGS. 4a and 4b show a first advantageous embodiment of the invention.
  • a semiconductor memory component F is shown, which has five memory chips C of the same memory type (DRAM, SRAM, E (E) PROM etc.), which are fastened on a common carrier T.
  • memory chips C of the same type
  • those of different types of memory eg DRAMs, SRAMs and / or EEPROMs, mixed
  • the memory chips C (not shown in FIG. 4a, analogously to those from FIG. 2) have contact points K which are electrical Connections B are connected to the outer connection points A of the carrier T.
  • the shape of the support T corresponds to five supports T] _ of the type shown in FIGS. 2 and 3a to 3c, which are connected to one another.
  • the carrier T thus has five times as many external connection points A as a conventional carrier T-j_.
  • the five memory chips C fastened to the middle parts of the conventional carrier structures and attached to the carrier T are connected in the manner shown in FIG. 2 to the external connection points A of the carrier T.
  • Each contact point K of each memory chip C is thus assigned exactly one external connection point A of the carrier T, the sum of the number of contact points K of the memory chips C is equal to the number of external connection points A of the carrier T.
  • FIG. 4b shows the carrier T with the (not more visible) memory chips * C and their common casing U, which leaves the outer connection points A of the carrier T.
  • the invention can also be implemented in such a way that at least those contact points K of the memory chips C which carry data signals during operation (address signals, control signals, data input and output signals) are each assigned to one of the outer connection points A (wire connection, bonding), while the contact points K which conduct supply potentials during operation (typically VDD and VSS) are not necessarily connected to an external connection point A, but, separated according to the type of supply potential, have fewer external connection points A than correspond to a 1: 1 assignment would.
  • the contact points K of a respective type of supply potential would have to be electrically connected to one another in another way (for example by means of bond wires inside the casing U or by means of short-circuit bridges outside the casing U).
  • the memory component T according to the invention corresponds in structure and function to five of the memory modules shown in FIG. 2. However, it is less expensive to manufacture and use with module boards. The one used in the manufacture of conventional building blocks. The one used in the manufacture of conventional building blocks
  • Carrier T ] _ is generally processed in the form of a band of several identical carrier structures T -] _ arranged in series and interconnected.
  • the same band of carrier structures can be used for the production of the carrier T, the band being separated into individual carriers T] _ after the memory chips C and their electrical connections B have been applied, or there are five carrier structures in pieces.
  • FIG. 5 shows a first advantageous application of the invention.
  • two larger memory components V and F according to the invention are fastened on a module board M, one component V the function of four and the other F the function of five conventional ones Memory modules fulfilled.
  • the number of outer connection points A of the components V and F and the distances between them correspond exactly to those of conventional individual components arranged in rows.
  • a standard module board M such as that shown in FIG. 1, can therefore be used.
  • the band of carrier structures used in the production of the memory components V and F must then have a distance between adjacent individual structures which corresponds to the gap between two individual components placed in series.
  • FIG. 6 shows schematically the production of the common casing U for a component according to the invention, the outer connection points A of which, at a distance from one another, correspond to those of conventional memory modules when the modules are placed in series and at a distance from one another.
  • the band of carrier structures TB provided with memory chips C is surrounded by an injection mold SF which has inlet openings E through which a plastic mass is introduced.
  • a distance d is left between each of two conventional individual components corresponding to injection molds, which is the same as that between individual components attached to standard module boards M in the conventional manner. If a different wrapping material or a different manufacturing process is used (e.g. with pre-molded parts, pre-molded), the process step is adjusted accordingly.
  • FIG. 7 shows a first variant of the first embodiment and its application.
  • a module board M is equipped with two memory components V and F according to the invention, one component V performing the function of four and the other F the function of five conventional memory components.
  • the distances of the outer connection points A Memory components V and F correspond to those of nine conventional memory modules which are set in two rows of four and five modules, respectively, without keeping a distance from one another.
  • Such an arrangement of the outer connection points A of the memory components V and F according to the invention corresponds to the use of a band of carrier structures TB which has conventional individual module carriers T ] _ corresponding individual structures in direct contact one behind the other and without any spacing from one another.
  • FIG. 8 the production of the common envelope U is carried out with an analog injection mold SF.
  • An advantage of this variant is the possibility of reducing the dimensions of the module board M.
  • Figure 9 shows a second variant of the first embodiment and its application. Analogous to FIGS. 5 and 7, a module board M is shown. A memory component N according to the invention, which fulfills the function of nine conventional memory modules, is fastened on this. The arrangement of the outer connection points A corresponds to that of nine conventional memory chips set in two rows.
  • the component N has nine memory chips C, which are fastened to a common carrier T and are surrounded by a common casing U.
  • the memory component N e.g. two carriers, which correspond to those used in components V and F from FIG. 7, are connected to one another to form a carrier T, which is then fitted with nine memory chips C and provided with a common casing U.
  • the simple modular structure of the component means that the component can easily be separated into areas between individual chips.
  • the module board M is then equipped with two or more components.
  • Figure 10 shows a second advantageous embodiment of the invention.
  • two supports TV and TF are attached, which correspond to the supports T used in the manufacture of components V and F from FIG.
  • the brackets TV and TF consist of four or five brackets attached to one another, brackets T ] _ corresponding to individual components, and thus have four or five times as many external connection points A. like individual building blocks.
  • a memory chip C is fastened and electrically connected in such a way that exactly one external connection point A of the carrier TV or TF is assigned to each contact point K of each memory chip.
  • the carriers TV and TF with the memory chips C thereon thus correspond to the components V and F from FIG. 7 without their common casing U.
  • the carriers TV and TF with the memory chips C thereon are both carriers TV and TF and also their outer ones
  • connection points A Surrounding connection points A enveloping envelope U. Since the carriers TV and TF, in contrast to those of the components V and F in FIG. 7, are not provided with a sheath which leaves the outer connection points A and are mounted on a module board M, but, mounted on the module board M, with an outer connection points A envelope U are provided, the module board M is part of the envelope U.
  • the common covering U could also consist of two parts, each covering one of the two carriers TV and TF fastened on the module board M together with its outer connection points A.
  • FIGS. 11 to 14 show different variants of the second embodiment.
  • a carrier T is shown with the memory chips C thereon, the electrical connections B and the outer connection points A, which is surrounded by a casing U common to the memory chips C and which includes the outer connection points A.
  • two or more carriers could also be surrounded by an envelope U.
  • FIGS. 11 to 14 show the component according to the invention in cross section to the longitudinal axis defined by the large extent of the carrier T.
  • FIG. 11 shows an envelope U enveloping carrier T with memory chips C and external connection points A, which is composed of the part of the module board M located under the carrier T and a molded part F covering the side of the carrier T facing away from the module board M.
  • the fitting F consists of, for example
  • the component according to the invention differs significantly from the prior art disclosed in JP-A-60-20 88 51: Since the memory chips C are not fastened directly on a module board M, but on a carrier T, the Production of the component according to the invention does not have any of the disadvantages already mentioned with regard to JP-A-60-20 88 51.
  • FIG. 12 shows an envelope U enveloping carrier T with memory chips C and external connection points A, which is composed of the part of the module board M located under the carrier T and a casing mass H enclosing the side of the carrier T facing away from the module board M.
  • the envelope mass H consists e.g. made of plastic (post-molded).
  • Injection molding analogous to that shown in Figures 6 and 8
  • Injection molds SF are used, these having a correspondingly selected shape.
  • the enveloping mass H could also extend to the rear of the module board M, as shown in FIG. This would e.g. a greater mechanical stability of the component according to the invention.
  • FIG. 14 shows a module board M which is equipped with carriers T-j_ and T2 on both surfaces.
  • the beams T] _ and T2 speak to the carriers T of the first embodiment of the component according to the invention and have a plurality of memory chips C] _ or C2 and their electrical connections B.
  • the carriers T-j_ and T2 provided with the memory chips are surrounded together with a part of the module board and with their outer connection points A by an enveloping mass H, so that they are enveloped by a part of the module board M and the enveloping mass H as a covering.
  • the component according to the invention represented by FIG. 14 has lower costs and simplified manufacture compared to conventional components, since
  • Using a plurality of memory chips C common carriers T and a sheath common to all memory chips C together with carriers T reduces the number of process steps required to produce a module board M equipped with memory elements on both surfaces.
  • the supports T used in the second embodiment of the invention are produced from standardized elements (strips of support structures) and, for connection and for attachment to the module board M, either plug-in connections or surface connections, i.a. soldered, can have.
  • the number of memory chips C used in the semiconductor memory component according to the invention is preferably selected so that the number of n-4 or (n-4) + 1 results for the data input and data output connections of the semiconductor memory component, with n> 0 .
  • the latter case allows the use of a so-called parity bit in the semiconductor memory device.

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Abstract

A semiconductor storage component comprises a plurality of storage chips (C) of the same or different storage types (DRAM, SRAM, E(E)PROM, etc.) which are secured to a shared substrate (T) and connected to its outer terminals (A) via electrical connections (B), in which an outer terminal (A) of the substrate is precisely allocated to each contact point (K) or each storage chip (C). In a first embodiment, the substrate (T) fitted with several storage chips (C) has a casing (U) leaving its outer terminals (A) free and may be secured to a module plate (M). In a second embodiment, the substrate (T) with several storage chips (C) is secured to a module plate (M) and covered with a moulding (F) or a potting compound (H) to the side of the substrate (T) away from the module plate in such a way that the coating (U) on the part of the module plate (M) beneath the substrate (T) and the moulding (F) or potting compound (H) also comprises the outer terminals (A) of the substrate.

Description

Halbleiter-Speicherbauteil mit mehreren Speicherchips in einer gemeinsamen UmhüllungSemiconductor memory component with several memory chips in a common casing
Die Erfindung betrifft Halbleiter-Speicherbauteile nach den Oberbegriffen der Patentansprüche 1 und 2 sowie Verfahren zur Herstellung der Halbleiter-Speicherbauteile nach den Oberbegriffen der Patentansprüche 14 und 15.The invention relates to semiconductor memory components according to the preambles of claims 1 and 2 and to methods for producing the semiconductor memory components according to the preambles of claims 14 and 15.
In ComputerSystemen werden durch den gestiegenen Speicherbedarf seit geraumer Zeit kaum noch Einzelbausteine zur Bestückung des Computers mit Speicherchips einer bestimmten Speicherart wie z.B. DRAM, SRAM, E(E)PROM etc., eingesetzt. Es hat sich viel¬ mehr als Standard ein Speichermodul, SIMM genannt (Single in line memory module), durchgesetzt, bei dem - z.B. neun - Spei¬ cherbausteine von derselben Speicherart auf einer Modulplatine mit Steck- oder - beispielsweise -Lötverbindungen (z.B. surface mounted) befestigt werden. Das mit Speicherbausteinen bestückte Speichermodul wird als Ganzes in den Computer eingebaut (ein¬ gelötet oder gesteckt) und auch als Ganzes gegebenenfalls ersetzt bzw. durch weitere ergänzt.For some time now, in computer systems, the increased memory requirements have made it almost impossible for individual components to populate the computer with memory chips of a certain type of memory, e.g. DRAM, SRAM, E (E) PROM etc. are used. Much more than a standard, a memory module called SIMM (Single in line memory module) has become established, in which - e.g. nine memory modules of the same type of memory are attached to a module board with plug-in or, for example, soldered connections (e.g. surface mounted). The memory module equipped with memory modules is installed as a whole in the computer (soldered or plugged in) and also, if necessary, replaced or supplemented as a whole.
Figur 1 zeigt ein Standard-Speichermodul (z.B. 4Mx9 DRAM) mit der Modulplatine M, neun Speicherbausteinen S (statt DRAMS wären auch SRAMs, E(E)PROM etc. möglich) und den Modulan¬ schlüssen 1 bis 30. Die Modulanschlüsse 1 bis 30 sind über nicht abgebildete elektrische Leitungen mit Kontaktpunkten verbunden, an denen mit Steckverbindungen oder Oberflächen¬ kontakten (z.B. gelötet) die äußeren Anschlußpunkte A der Speicherbausteine S befestigt sind. Die Speicherbausteine S sind hier in zwei Reihen zu vier und fünf Steinen angeordnet, andere Konfigurationen sind jedoch auch möglich. Figur 2 zeigt einen typischen Speicherbaustein. Der Speicher¬ chip C ist auf einen Träger ^ (Metallspinne, Folie etc.) durch Kleben, Legieren etc. montiert. Zwischen den Kontaktpunkten K des Speicherchips C und den äußeren Anschlußpunkten A desFIG. 1 shows a standard memory module (for example 4Mx9 DRAM) with the module board M, nine memory modules S (instead of DRAMS, SRAMs, E (E) PROM etc. would also be possible) and the module connections 1 to 30. The module connections 1 to 30 are connected via electrical lines (not shown) to contact points to which the external connection points A of the memory modules S are fastened with plug connections or surface contacts (for example soldered). The memory modules S are arranged here in two rows of four and five stones, but other configurations are also possible. Figure 2 shows a typical memory chip. The memory chip C is mounted on a carrier ^ (metal spider, foil etc.) by gluing, alloying etc. Between the contact points K of the memory chip C and the outer connection points A of
Trägers T-j_ sind elektrische Verbindungen B (z.B. Golddrähte) angebracht. Außerdem sind Speicherchip C und Träger T]_ mit einer Umhüllung U versehen, die zumeist aus Plastik besteht (alternativ wird Keramik verwendet) und entweder vorgefertigt (pre-molded) ist oder direkt um Träger T]_ und Chip C gegossenCarrier T-j_ has electrical connections B (e.g. gold wires) attached. In addition, memory chip C and carrier T] _ are provided with a sheath U, which usually consists of plastic (alternatively, ceramic is used) and is either pre-molded or cast directly around carrier T] _ and chip C.
(post-molded) ist. Träger T]_ und Umhüllung U nebst elektrischen Verbindungen B stellen das Gehäuse des Speicherchips C dar.(post-molded) is. Carrier T] _ and casing U together with electrical connections B represent the housing of the memory chip C.
Die Figuren 3a bis 3c zeigen einen Herstellungsschritt des in Figur 2 abgebildeten, hier in Aufsicht dargestellten, Speicher¬ bausteins.Figures 3a to 3c show a manufacturing step of the memory module shown in Figure 2, shown here in supervision.
Figur 3a zeigt den Träger T-j_, der der Form wegen auch als Spinne bezeichnet wird. In der Mitte des Trägers Tl ist der Speicherchip C befestigt. Mit A sind die äußeren Anschlußpunkte des Trägers T]_ bezeichnet. Der Speicherchip C ist durch nicht abgebildete Verbindungen mit den äußeren Kontaktpunkten K verbunden.FIG. 3a shows the carrier T-j_, which is also referred to as a spider because of its shape. The memory chip C is fastened in the middle of the carrier T1. With A the outer connection points of the carrier T] _ are designated. The memory chip C is connected to the external contact points K by connections which are not shown.
Figur 3b zeigt dieselbe Struktur, die mit einer (hier nur im Umriß wiedergegebenen) Umhüllung U versehen wurde. Diese z.B. aus Plastik bestehende Umhüllung ist z.B. um den mit dem Speicherchip C versehenen Träger T gegossen worden, wobei die äußeren Anschlußpunkte A des Trägers frei bleiben.FIG. 3b shows the same structure that was provided with an envelope U (shown here only in outline). These e.g. plastic covering is e.g. has been cast around the carrier T provided with the memory chip C, the outer connection points A of the carrier remaining free.
Figur 3c zeigt den Baustein, nachdem die äußeren Anschlußpunkte A zur Befestigung und Kontaktierung auf z.B. einer Modulplatine nach unten gebogen wurden. Die so hergestellten Speicherbausteine werden noch einer Funk¬ tionsprüfung unterzogen, wobei heutzutage Testautomaten ver¬ wendet werden, die mehrere Speicherbausteine parallel testen können (z.B. T 5363 der Firma ADVANTEST für 16 Bausteine). An- schließend werden die Speicherbausteine auf der Modulplatine befestigt.FIG. 3c shows the module after the outer connection points A have been bent downward for fastening and contacting, for example on a module board. The memory modules produced in this way are also subjected to a functional test, automatic test machines being used today which can test several memory modules in parallel (for example T 5363 from ADVANTEST for 16 modules). The memory modules are then attached to the module board.
Die Herstellung solche Module erfordert zahlreiche Proze߬ schritte, von denen einige für alle (z.B. neun) Speicherbau- steine gleich sind. Es wäre von Vorteil, wenn solche Proze߬ schritte für mehrere Speicherbauεteine gleichzeitig durchge¬ führt werden könnten. Auch steigt mit den durch den technischen Fortschritt sinkenden Marktpreisen die Bedeutung der Herstellkosten für Verpackung und Funktionsprüfung der Spei- cherchips. Es wäre erstrebenswert, durch andere Herstellungs¬ methoden der Speicherbausteine, die auf ihre spätere Verwendung in Standardmodulen zugeschnitten sind, Prozeßschritte einzu¬ sparen und Kosten zu senken.The production of such modules requires numerous process steps, some of which are the same for all (e.g. nine) memory modules. It would be advantageous if such process steps could be carried out simultaneously for several memory modules. With market prices falling due to technical progress, the importance of manufacturing costs for packaging and functional testing of the memory chips is also increasing. It would be desirable to save process steps and reduce costs by means of other manufacturing methods of the memory modules, which are tailored for their later use in standard modules.
Zur Erhöhung der Speicherdichte hat es Versuche gegeben, mehr als ein Speicherchip in ein Gehäuse zu packen. WO-A-81/02367 zeigt eine gattungsgemäße Anordnung. Es wird ein Speicherbau¬ stein offenbart, bei dem vier identische Speicherchips in einem gemeinsamen Gehäuse untergebracht sind, wobei zwei sich auf der Oberseite und zwei auf der Unterseite eines mit Leitungen ver¬ sehenen Laminatträgers befinden. Um das Speicherbauteil kompakt zu halten, teilen die vier Speicherchips eine Mehrzahl der äußeren Anschlußpunkte des Trägers, so z.B. die Adresspins. Solche Speicherbausteine konnten sich auf dem Massenmarkt allerdings nicht durchsetzen, da sie den Speicherbaustein- Standards nicht entsprechen und durch die komplexe Montage der Speicherchips im Baustein auf einem Laminatträger zu teuer in der Herstellung sind. Für die Verwendung in Speichermodulen stellen diese Bausteine keinen Fortschritt dar. Die Offenlegungsschrift JP-A-60208851 offenbart ein weiteres Halbleiter-Speicherbauteil. Die Speicherchips sind direkt auf eine Speicherplatine aufgebracht, mit elektrischen Verbindungen versehen und mit einer gemeinsamen Kappe abgedeckt. Auch diese Anordnung konnte sich aufgrund der Nachteile des Herstellungs¬ verfahrens nicht durchsetzen. Durch die direkte Montage der Speicherchips auf die Speicherplatine müssen spezielle Platinen verwendet werden, das Testen der Speicherchips (das ja erst nach der elektrischen Verbindung der Chips mit der Platine durchgeführt werden kann) wird erschwert, als defekt erkannte Speicherchips können (da sie auf der Platine festgelötet sind) nur schwer durch funktionsfähige ersetzt werden, und das Herstellen der elektrischen Verbindungen zwischen Chips und Platine ist aufwendig und teuer.To increase the memory density, attempts have been made to pack more than one memory chip into one housing. WO-A-81/02367 shows a generic arrangement. A memory module is disclosed in which four identical memory chips are accommodated in a common housing, two being on the top and two on the bottom of a laminate carrier provided with lines. In order to keep the memory component compact, the four memory chips share a plurality of the outer connection points of the carrier, for example the address pins. However, such memory modules have not been able to establish themselves on the mass market since they do not meet the memory module standards and are too expensive to manufacture due to the complex assembly of the memory chips in the module on a laminate carrier. These modules do not represent any progress for use in memory modules. JP-A-60208851 discloses another semiconductor memory device. The memory chips are attached directly to a memory board, provided with electrical connections and covered with a common cap. This arrangement was also unable to establish itself due to the disadvantages of the production process. Due to the direct mounting of the memory chips on the memory board, special boards have to be used, the testing of the memory chips (which can only be carried out after the chips have been electrically connected to the board) is made more difficult because memory chips that are recognized as defective can be used (since they are on the board soldered) are difficult to replace with functional, and the electrical connections between chips and circuit board are complex and expensive.
Die JP-OS 64-1270 zeigt ebenfalls ein gattungsgemäßes Halblei¬ ter-Speicherbauteil. Allerdings sind dabei Kontaktpunkte der einzelnen Speicherchips, die im Betrieb dieselben Datensignale beziehungsweise Potentiale führen, mit jeweils einem einzigen äußeren Anschlußpunkt verbunden. Dies hat jedoch zur Folge, daß, aus geometrischer Sicht betrachtet, eine spezielle Umhüllung notwendig ist, die bei in etwa gleichbleibender Anzahl von Anschlußpunkten größer ist als die standardmäßig für einen einzigen Speicherchip verwendete Umhüllung, so daß die Anschlußpunkte von ihrer geometrischen Anordnung her und auch von ihrer Anzahl her (Dateneingangs- und/oder Datenausgangs- signale für beziehungsweise von verschiedenen Speicherchips können nicht jeweils einem Anschlußpunkt gemeinsam zugeordnet werden) nicht mit den Anforderungen übereinstimmen, die zum Beispiel standardisierte Platinen für SIMM-Module bezüglich Anzahl und Anordnung der Anschlußpunkte aufweisen. Ziel der vorliegenden Erfindung ist es, ein Speicherbauteil zu schaffen, welches bei Verwendung zusammen mit Modulplatinen möglichst einfach und kostengünstig handhabbar ist, und bei dessen Herstellung weitgehend standardisierte Bauteile verwend- bar sind.JP-OS 64-1270 also shows a generic semiconductor memory component. However, contact points of the individual memory chips, which carry the same data signals or potentials during operation, are each connected to a single external connection point. However, this has the consequence that, viewed from a geometrical point of view, a special encapsulation is necessary which, with the number of connection points remaining approximately the same, is larger than the encapsulation used as standard for a single memory chip, so that the connection points have a geometrical arrangement and also the number (data input and / or data output signals for or from different memory chips cannot be assigned to one connection point at a time) does not correspond to the requirements which standardized boards for SIMM modules have, for example, with regard to the number and arrangement of the connection points. The aim of the present invention is to provide a memory component which can be handled as simply and inexpensively as possible when used together with module boards, and largely standardized components can be used in its manufacture.
Diese Aufgabe wird gelöst durch gattungsgemäße Halbleiter-Spei¬ cherbauteile mit den kennzeichnenden Merkmalen der Patentansprüche 1 und 2 sowie durch in den Patentansprüchen 14 und 15 gekennzeichnete Verfahren.This object is achieved by generic semiconductor memory components with the characterizing features of claims 1 and 2 and by methods characterized in claims 14 and 15.
Die Erfindung wird nachstehend anhand der Figuren näher erläutert. Es zeigen:The invention is explained in more detail below with reference to the figures. Show it:
Die Figuren 1 bis 3 ein Speichermodul und einen Speicher- baustein nach dem Stand der Technik, die Figuren 4 bis 9 eine erste Ausführungsform derFIGS. 1 to 3 show a memory module and a memory module according to the prior art, FIGS. 4 to 9 show a first embodiment of the
Erfindung nebst vorteilhaften Ausgestaltungen und Anwendungen sowie Schritten des Herstellungsverfahrens, und die Figuren 10 bis 14 eine zweite Ausführungsform der Erfin¬ dung nebst vorteilhaften Ausgestaltun¬ gen.Invention together with advantageous configurations and applications as well as steps in the manufacturing process, and FIGS. 10 to 14 show a second embodiment of the invention along with advantageous configurations.
Die Figuren 4a und 4b zeigen eine erste vorteilhafte Ausfüh¬ rungsform der Erfindung. Abgebildet ist ein Halbleiter-Spei¬ cherbauteil F, das fünf Speicherchips C derselben Speicherart (DRAM, SRAM, E(E)PROM etc.) aufweist, die auf einem gemeinsamen Träger T befestigt sind. Anstelle von Speicherchips C von der- selben Art können erfindungsgemäß auch solche von unterschied¬ licher Speicherart (z. B. DRAM's, SRAM's und/oder EEPROM's, gemischt) auf dem gemeinsamen Träger befestigt sein. Die Spei¬ cherchips C haben (in Figur 4a nicht abgebildete, analog zu denen aus Figur 2) Kontaktpunkte K, die über elektrische Verbindungen B mit den äußeren Anschlußpunkten A des Trägers T verbunden sind. Der Träger T entspricht in seiner Form fünf Trägern T]_ vom in Figur 2 und 3a bis 3c abgebildeten Typ, die miteinander verbunden sind. Der Träger T weist somit fünfmal soviele äußere Anschlußpunkte A auf, wie ein herkömmlicher Träger T-j_. Die fünf auf den Mittelstücken der herkömmlichen Träger-Strukturen entsprechenden Teile des Trägers T befestig¬ ten Speicherchips C sind in der in Figur 2 dargestellten Art mit den äußeren Anschlußpunkten A des Trägers T verbunden. Jedem Kontaktpunkt K jedes Speicherchips C ist somit genau ein äußerer Anschlußpunkt A des Trägers T zugeordnet, die Summe der Zahl der Kontaktpunkte K der Speicherchips C ist gleich der Zahl der äußeren Anschlußpunkte A des Trägers T. Figur 4b zeigt den Träger T mit den (nicht mehr sichtbaren) Speicherchips* C und der ihnen gemeinsamen Umhüllung U, die die äußeren An¬ schlußpunkte A des Trägers T freiläßt.FIGS. 4a and 4b show a first advantageous embodiment of the invention. A semiconductor memory component F is shown, which has five memory chips C of the same memory type (DRAM, SRAM, E (E) PROM etc.), which are fastened on a common carrier T. Instead of memory chips C of the same type, those of different types of memory (eg DRAMs, SRAMs and / or EEPROMs, mixed) can also be attached to the common carrier. The memory chips C (not shown in FIG. 4a, analogously to those from FIG. 2) have contact points K which are electrical Connections B are connected to the outer connection points A of the carrier T. The shape of the support T corresponds to five supports T] _ of the type shown in FIGS. 2 and 3a to 3c, which are connected to one another. The carrier T thus has five times as many external connection points A as a conventional carrier T-j_. The five memory chips C fastened to the middle parts of the conventional carrier structures and attached to the carrier T are connected in the manner shown in FIG. 2 to the external connection points A of the carrier T. Each contact point K of each memory chip C is thus assigned exactly one external connection point A of the carrier T, the sum of the number of contact points K of the memory chips C is equal to the number of external connection points A of the carrier T. FIG. 4b shows the carrier T with the (not more visible) memory chips * C and their common casing U, which leaves the outer connection points A of the carrier T.
Die Erfindung ist jedoch auch dergestalt realisierbar, daß zumindest denjenigen Kontaktpunkten K der Speicherchips C, die im Betrieb Datensignale führen (Adreßsignale, Steuersignale, Datenein- und -ausgangssignale) , jeweils einer der äußeren Anschlußpunkte A zugeordnet ist (Drahtverbindung, Bonding) , während die im Betrieb Versorgungspotentiale (typischerweise VDD und VSS)führenden Kontaktpunkte K nicht notwendigerweise mit jeweils einem äußeren Anschlußpunkt A verbunden sind, sondern, getrennt nach der Art des jeweiligen Versorgungspoten¬ tials, mit weniger äußeren Anschlußpunkten A, als es einer 1:1- Zuordnung entsprechen würde. In diesem Fall müßten die Kontakt¬ punkte K einer jeweiligen Art von Versorgungspotential ander- weitig (zum Beispiel mittels Bonddrähten innerhalb der Umhül¬ lung U oder mittels Kurzschlußbrücken außerhalb der Umhüllung U) elektrisch miteinander verbunden werden. Das erfindungsgemäße Speicherbauteil T entspricht in seinem Aufbau und funktionell somit fünf der in Figur 2 abgebildeten Speicherbausteinen. Es ist jedoch in der Herstellung und in Verwendung mit Modulplatinen kostengünstiger. Der bei der Herstellung herkömmlicher Bausteine verwendeteHowever, the invention can also be implemented in such a way that at least those contact points K of the memory chips C which carry data signals during operation (address signals, control signals, data input and output signals) are each assigned to one of the outer connection points A (wire connection, bonding), while the contact points K which conduct supply potentials during operation (typically VDD and VSS) are not necessarily connected to an external connection point A, but, separated according to the type of supply potential, have fewer external connection points A than correspond to a 1: 1 assignment would. In this case, the contact points K of a respective type of supply potential would have to be electrically connected to one another in another way (for example by means of bond wires inside the casing U or by means of short-circuit bridges outside the casing U). The memory component T according to the invention corresponds in structure and function to five of the memory modules shown in FIG. 2. However, it is less expensive to manufacture and use with module boards. The one used in the manufacture of conventional building blocks
Träger T]_ wird im allgemeinen in Form eines Bandes von mehreren identischen in Reihe geordneten und miteinander verbundenen Trägerstrukturen T-]_ verarbeitet. Beim erfindungsgemäßen Speicherbauteil F kann zur Herstellung des Trägers T dasselbe Band von Trägerstrukturen verwendet werden, wobei die Trennung des Bandes in Einzelträger T]_ nach dem Aufbringen der Speicher¬ chips C und deren elektrischen Verbindungen B unterbleibt bzw. in Stücken ä fünf Trägerstrukturen erfolgt. Durch die Verwen¬ dung standardisierter Trägerstrukturen treten somit keine zu- sätzlichen Kosten auf.Carrier T ] _ is generally processed in the form of a band of several identical carrier structures T -] _ arranged in series and interconnected. In the memory component F according to the invention, the same band of carrier structures can be used for the production of the carrier T, the band being separated into individual carriers T] _ after the memory chips C and their electrical connections B have been applied, or there are five carrier structures in pieces. By using standardized carrier structures, there are no additional costs.
Das Erzeugen der gemeinsamen Umhüllung U, das anschließende Testen der Bauteile F (z.B. die Bestückung der Testautomaten), die Befestigung der Bauteile F auf einer Modulplatine, kurzum das sogenannte "handling" der Speicherbauteile von der Pro¬ duktion des Gehäuses bis zur anschließenden Verwendung bei der Fertigung von Speichermodulen erfährt eine Reduktion der Bau¬ teilzahl, der Prozeßschritte und somit der Kosten.The creation of the common casing U, the subsequent testing of the components F (for example the assembly of the test machines), the fastening of the components F on a module board, in short the so-called "handling" of the memory components from the production of the housing to the subsequent use The production of memory modules is reduced in the number of components, the process steps and thus the costs.
Durch die Verwendung von mehreren Speicherchips C derselben oder verschiedener Speicherart in einem einzigen Speicherbau¬ teil F können Prozeßschritte somit vereinfacht und verbilligt werden.By using a plurality of memory chips C of the same or different types of memory in a single memory component F, process steps can thus be simplified and reduced in cost.
Figur 5 zeigt eine erste vorteilhafte Anwendung der Erfindung. Auf einer Modulplatine M sind anstelle von neun Einzelbaustei¬ nen wie in Figur 1 zwei größere erfindungsgemäße Speicherbau¬ teile V und F befestigt, wobei das eine Bauteil V die Funktion von vier und das andere F die Funktion von fünf herkömmlichen Speicherbausteinen erfüllt. Die Anzahl der äußeren Anschlu߬ punkte A der Bauteile V und F sowie die Abstände dazwischen entsprechen genau denjenigen von herkömmlichen, in Reihen ange¬ ordneten Einzelbausteinen. Deshalb kann eine Standard-Modul- platine M, wie die in Figur 1 abgebildte, verwendet werden.Figure 5 shows a first advantageous application of the invention. Instead of nine individual components, as in FIG. 1, two larger memory components V and F according to the invention are fastened on a module board M, one component V the function of four and the other F the function of five conventional ones Memory modules fulfilled. The number of outer connection points A of the components V and F and the distances between them correspond exactly to those of conventional individual components arranged in rows. A standard module board M, such as that shown in FIG. 1, can therefore be used.
Das bei der Herstellung der Speicherbauteile V und F verwendete Band von Trägerstrukturen muß dann zwischen benachbarten Ein¬ zelstrukturen einen Abstand aufweisen, der der Lücke zwischen zwei in Reihe gesetzten Einzelbausteinen entspricht.The band of carrier structures used in the production of the memory components V and F must then have a distance between adjacent individual structures which corresponds to the gap between two individual components placed in series.
Figur 6 zeigt schematisiert die Herstellung der gemeinsamen Umhüllung U für ein erfindungsgemäßes Bauteil, dessen äußere Anschlußpunkte A im Abstand voneinander denjenigen von her- kömmlichen Speicherbausteinen entsprechen, wenn die Bausteine in Reihe und mit einem Abstand zueinander gesetzt sind. Das mit Speicherchips C versehene Band von Trägerstrukturen TB wird durch eine Spritzform SF umgeben, die Einlaßöffnungen E auf¬ weist, durch welche eine Plastikmasse eingeführt wird. Zwischen je zwei herkömmlichen Einzelbausteinen entsprechenden Spritz¬ formen wird ein Abstand d gelassen, der dem zwischen in her¬ kömmlicher Weise auf Standard-Modulplatinen M befestigten Einzelbausteinen gleich ist. Bei der Verwendung eines anderen Umhüllungsmaterials oder eines anderen Herstellungsverfahrens (z.B. mit vorgefertigten Formstücken, pre-molded) wird der Verfahrensschrit entsprechend angepaßt.FIG. 6 shows schematically the production of the common casing U for a component according to the invention, the outer connection points A of which, at a distance from one another, correspond to those of conventional memory modules when the modules are placed in series and at a distance from one another. The band of carrier structures TB provided with memory chips C is surrounded by an injection mold SF which has inlet openings E through which a plastic mass is introduced. A distance d is left between each of two conventional individual components corresponding to injection molds, which is the same as that between individual components attached to standard module boards M in the conventional manner. If a different wrapping material or a different manufacturing process is used (e.g. with pre-molded parts, pre-molded), the process step is adjusted accordingly.
Figur 7 zeigt eine erste Variante der ersten Ausführungsform und ihre Anwendung. Analog zu der in Figur 5 abgebildeten ersten vorteilhaften Anwendung der Erfindung ist eine Modul¬ platine M mit zwei erfindungsgemäßen Speicherbauteilen V und F bestückt, wobei das eine Bauteil V die Funktion von vier und das andere F die Funktion von fünf herkömmlichen Speicherbau¬ steinen erfüllt. Die Abstände der äußeren Anschlußpunkte A der Speicherbauteile V und F entsprechen denjenigen von neun her¬ kömmlichen Speicherbausteinen, die in zwei Reihen ä vier bzw. fünf Bausteine gesetzt sind, ohne einen Abstand untereinander zu halten.FIG. 7 shows a first variant of the first embodiment and its application. Analogous to the first advantageous application of the invention shown in FIG. 5, a module board M is equipped with two memory components V and F according to the invention, one component V performing the function of four and the other F the function of five conventional memory components. The distances of the outer connection points A Memory components V and F correspond to those of nine conventional memory modules which are set in two rows of four and five modules, respectively, without keeping a distance from one another.
Eine solche Anordnung der äußeren Anschlußpunkte A der erfin¬ dungsgemäßen Speicherbauteile V und F entspricht der Verwendung eines Bandes von Trägerstrukturen TB, das herkömmlichen Einzel¬ bausteinträgern T]_ entsprechende Einzelstrukturen in direktem Kontakt hintereinander und ohne Abstand zueinander aufweist.Such an arrangement of the outer connection points A of the memory components V and F according to the invention corresponds to the use of a band of carrier structures TB which has conventional individual module carriers T ] _ corresponding individual structures in direct contact one behind the other and without any spacing from one another.
Die Herstellung der gemeinsamen Umhüllung U wird, wie in Figur 8 gezeigt, mit einer analog angepaßten Spritzform SF durchge¬ führt. Ein Vorteil dieser Variante ist die Möglichkeit, die Maße der Modulplatine M zu verringern. Figur 9 zeigt eine zweite Variante der ersten Ausführungsform und ihre Anwendung. Analog zu Figur 5 und 7 ist eine Modulpla¬ tine M abgebildet. Auf dieser ist ein erfindungsgemäßes Spei¬ cherbauteil N befestigt, das die Funktion von neun herkömmli¬ chen Speicherbausteinen erfüllt. Die Anordnung der äußeren Anschlußpunkte A entspricht derjenigen von neun in zwei Reihen gesetzten herkömmlichen Speicherbausteinen. Das Bauteil N weist neun Speicherchips C auf, die auf einen gemeinsamen Träger T befestigt sind und von einer gemeinsamen Umhüllung U umgeben sind.As shown in FIG. 8, the production of the common envelope U is carried out with an analog injection mold SF. An advantage of this variant is the possibility of reducing the dimensions of the module board M. Figure 9 shows a second variant of the first embodiment and its application. Analogous to FIGS. 5 and 7, a module board M is shown. A memory component N according to the invention, which fulfills the function of nine conventional memory modules, is fastened on this. The arrangement of the outer connection points A corresponds to that of nine conventional memory chips set in two rows. The component N has nine memory chips C, which are fastened to a common carrier T and are surrounded by a common casing U.
Zur Herstellung des Speicherbauteils N könnten z.B. zwei Träger, die den in den Bauteilen V und F aus Figur 7 verwen¬ deten entsprechen, miteinander verbunden werden zu einem Träger T, der dann mit neun Speicherchips C bestückt und mit einer gemeinsamen Umhüllung U versehen wird.For the production of the memory component N e.g. two carriers, which correspond to those used in components V and F from FIG. 7, are connected to one another to form a carrier T, which is then fitted with nine memory chips C and provided with a common casing U.
Andere Variationen, insbesondere bei der Zahl der Speicherchips C und der Form der resultierenden Speicherbauteile sind für den Fachmann anhand dieser Offenbarung erschließbar und werden hier nicht weiter ausgeführt.Other variations, in particular in the number of memory chips C and the shape of the resulting memory components are for the Those skilled in the art can be inferred from this disclosure and will not be discussed further here.
Zu bemerken ist, daß im Falle, daß bei der Funktionsprüfung eines erfindungsgemäßen Bauteils Defekte bei einzelnen Spei¬ cherchips C des Bausteils festgestellt werden, durch den einfachen modularen Aufbau des Bauteils dieses problemlos in Bereichen zwischen einzelnen Chips aufgetrennt werden kann.It should be noted that in the event that defects are found in individual memory chips C of the component during the functional test of a component according to the invention, the simple modular structure of the component means that the component can easily be separated into areas between individual chips.
Bei dem in Figur 4b abgebildeten Bauteil F wäre ein Trenn¬ schritt quer zur Längsachse des Bauteils an vier in der Figur mit den Strecken SS' gekennzeichneten Stellen möglich. Diese Trennlinien SS' entsprechen den Linien, längs welcher der Träger T in Einzelbaustein-Träger T]_ entsprechende Strukturen zerlegt werden kann. Wird auf diese Weise durch einen oder mehrere Schnitte ein Teil des Bauteils F entfernt, so ent¬ spricht dieser entfernte Teil in Größe und Funktion einem oder mehreren herkömmlichen Einzelbausteinen. Der entfernte Teil kann somit durch herkömmliche Einzelbausteine ersetzt werden.In the case of the component F shown in FIG. 4b, a separation step transversely to the longitudinal axis of the component would be possible at four points marked with the lines SS 'in the figure. These dividing lines SS 'correspond to the lines along which the carrier T can be broken down into individual component carriers T ] _ corresponding structures. If a part of the component F is removed in this way by one or more cuts, this removed part corresponds in size and function to one or more conventional individual components. The removed part can thus be replaced by conventional individual building blocks.
Es wäre auch vorstellbar, Bauteile größeren Ausmaßes (z.B. mit 36 Speicherchips C) herzustellen, zu testen und dem Ergebnis der Funktionsprüfung gemäß in Bauteile von vorzugsweise je vier oder fünf Speicherchips C zu zerteilen. Je nachdem, welche Größen an Bauteilen vorliegen, wird die Modulplatine M sodann mit zwei oder mehr Bauteilen bestückt.It would also be conceivable to manufacture components of a larger size (e.g. with 36 memory chips C), to test them and to divide them into components of preferably four or five memory chips C according to the result of the functional test. Depending on the sizes of the components, the module board M is then equipped with two or more components.
Figur 10 zeigt eine zweite vorteilhafte Ausführungsform der Erfindung. Auf einer Modulplatine M sind zwei Träger TV und TF befestigt, die den bei der Herstellung der Bauteile V und F aus Figur 7 verwendeten Trägern T entsprechen. Die Träger TV und TF bestehen aus vier bzw. fünf aneinander befestigten, Trägern T]_ für Einzelbausteinen entsprechenden, Strukturen und weisen somit vier- bzw. fünfmal soviele äußere Anschlußpunkte A auf wie Einzelbausteine. In der Mitte jeder einem herkömmlichen Träger T-j_ entsprechenden Struktur ist ein Speicherchip C be¬ festigt und derart elektrisch verbunden, daß jedem Kontaktpunkt K jedes Speicherchips genau ein äußerer Anschlußpunkt A des Trägers TV oder TF zugeordnet ist. Die Träger TV und TF mit den darauf befindlichen Speicherchips C entsprechen somit den Bau¬ teilen V und F aus Figur 7 ohne deren gemeinsame Umhüllung U.Figure 10 shows a second advantageous embodiment of the invention. On a module board M, two supports TV and TF are attached, which correspond to the supports T used in the manufacture of components V and F from FIG. The brackets TV and TF consist of four or five brackets attached to one another, brackets T ] _ corresponding to individual components, and thus have four or five times as many external connection points A. like individual building blocks. In the middle of each structure corresponding to a conventional carrier T-j_, a memory chip C is fastened and electrically connected in such a way that exactly one external connection point A of the carrier TV or TF is assigned to each contact point K of each memory chip. The carriers TV and TF with the memory chips C thereon thus correspond to the components V and F from FIG. 7 without their common casing U.
Die Träger TV und TF mit den darauf befindlichen Speicherchips C sind von einer beide Träger TV und TF und auch deren äußereThe carriers TV and TF with the memory chips C thereon are both carriers TV and TF and also their outer ones
Anschlußpunkte A umhüllenden Umhüllung U umgeben. Da die Träger TV und TF im Gegensatz zu denen der Bauteile V und F in Figur 7 nicht von einer die äußeren Anschlußpunkte A freilassenden Umhüllung versehen und auf einer Modulplatine M montiert sind, sondern, auf der Modulplatine M montiert, mit einer die äußeren Anschlußpunkte A umhüllenden Umhüllung U versehen sind, stellt die Modulplatine M einen Teil der Umhüllung U dar.Surrounding connection points A enveloping envelope U. Since the carriers TV and TF, in contrast to those of the components V and F in FIG. 7, are not provided with a sheath which leaves the outer connection points A and are mounted on a module board M, but, mounted on the module board M, with an outer connection points A envelope U are provided, the module board M is part of the envelope U.
Die gemeinsame Umhüllung U könnte auch aus zwei Teilen beste- hen, die jeweils einen der beiden auf der Modulplatine M be¬ festigten Träger TV und TF nebst seinen äußeren Anschlußpunkten A umhüllt.The common covering U could also consist of two parts, each covering one of the two carriers TV and TF fastened on the module board M together with its outer connection points A.
Die Figuren 11 bis 14 zeigen verschiedene Varianten der zweiten Ausführungsform. Zur Vereinfachung ist jeweils ein Träger T mit dem darauf befindlichen Speicherchips C, den elektrischen Ver¬ bindungen B und den äußeren Anschlußpunkten A abgebildet, der von einer den Speicherchips C gemeinsamen Umhüllung U umgeben ist, die die äußeren Anschlußpunkte A miteinschließt. Analog zur Figur 10 könnten auch zwei oder mehr Träger von einer Umhüllung U umgeben sein. Die Figuren 11 bis 14 zeigen das erfindungsgemäße Bauteil im Querschnitt zur durch die große Ausdehnung des Trägers T definierten Längsache. Figur 11 zeigt eine, Träger T mit Speicherchips C und äußere Anschlußpunkte A umhüllende Umhüllung U, die sich aus dem unter dem Träger T befindlichen Teil der Modulplatine M und einem die der Modulplatine M abgewandte Seite des Träger T bedeckenden Formstück F zusammensetzt. Das Formstück F besteht z.B. ausFIGS. 11 to 14 show different variants of the second embodiment. To simplify matters, a carrier T is shown with the memory chips C thereon, the electrical connections B and the outer connection points A, which is surrounded by a casing U common to the memory chips C and which includes the outer connection points A. Analogously to FIG. 10, two or more carriers could also be surrounded by an envelope U. FIGS. 11 to 14 show the component according to the invention in cross section to the longitudinal axis defined by the large extent of the carrier T. FIG. 11 shows an envelope U enveloping carrier T with memory chips C and external connection points A, which is composed of the part of the module board M located under the carrier T and a molded part F covering the side of the carrier T facing away from the module board M. The fitting F consists of, for example
Plastik (pre-molded) . Es ist deutlich, daß das Herstellungsver¬ fahren des erfindungsgemäßen Bauteils der zweiten Ausführungs¬ form der Erfindung sich von dem der ersten Ausführungsform dadurch unterscheidet, daß die Umhüllung erst beim Aufbringen des Trägers T auf die Modulplatine M erzeugt wird, statt zuvor.Plastic (pre-molded). It is clear that the manufacturing method of the component according to the invention of the second embodiment of the invention differs from that of the first embodiment in that the sheath is only produced when the carrier T is applied to the module board M instead of before.
Auch soll betont werden, daß das erfindungsgemäße Bauteil von dem in JP-A-60-20 88 51 offenbarten Stand der Technik deutlich unterscheidet: Da die Speicherchips C nicht direkt auf einer Modulplatine M befestigt sind, sondern auf einem Träger T, treten bei der Herstellung des erfindungsgemäßen Bauteils keine der bezüglich JP-A-60-20 88 51 bereits genannten Nachteile auf.It should also be emphasized that the component according to the invention differs significantly from the prior art disclosed in JP-A-60-20 88 51: Since the memory chips C are not fastened directly on a module board M, but on a carrier T, the Production of the component according to the invention does not have any of the disadvantages already mentioned with regard to JP-A-60-20 88 51.
Figur 12 zeigt eine, Träger T mit Speicherchips C und äußere Anschlußpunkte A umhüllende Umhüllung U, die sich aus dem unter den Träger T befindlichen Teil der Modulplatine M und einer die der Modulplatine M abgewandten Seite des Trägers T umschließen¬ den Hüllmasse H zusammensetzt. Die Hüllmasse H besteht z.B. aus Plastik (post-molded) . Zur Herstellung der Hüllmasse H können z.B. Spritzformen analog der in Figur 6 und 8 abgebildetenFIG. 12 shows an envelope U enveloping carrier T with memory chips C and external connection points A, which is composed of the part of the module board M located under the carrier T and a casing mass H enclosing the side of the carrier T facing away from the module board M. The envelope mass H consists e.g. made of plastic (post-molded). For the production of the envelope H, e.g. Injection molding analogous to that shown in Figures 6 and 8
Spritzformen SF verwendet werden, wobei diese eine dementspre¬ chend gewählte Form aufweisen. Je nach Form der gewählten Spritzform könnte die Hüllmasse H sich auch bis auf die Rück¬ seite der Modulplatine M erstrecken, wie in Figur 13 abgebil- det. Dies hätte z.B. eine größere mechanische Stabiltät des erfindungsgemäßen Bauteils zur Folge.Injection molds SF are used, these having a correspondingly selected shape. Depending on the shape of the selected injection mold, the enveloping mass H could also extend to the rear of the module board M, as shown in FIG. This would e.g. a greater mechanical stability of the component according to the invention.
Figur 14 zeigt eine Modulplatine M, die auf beiden Oberflächen mit Trägern T-j_ und T2 bestückt ist. Die Träger T]_ und T2 ent- sprechen den Trägern T der ersten Ausführungsform des erfin¬ dungsgemäßen Bauteils und weisen mehrere Speicherchips C]_ bzw. C2 sowie deren elektrische Verbindungen B auf. Die mit den Speicherchips versehenen Träger T-j_ und T2 sind zusammen mit einem Teil der Modulplatine und mit ihren äußeren Anschlu߬ punkten A urch eine Hüllmasse H umgeben, so daß sie durch einen Teil der Modulplatine M und die Hüllmasse H als Umhüllung umhüllt sich. Das durch Figur 14 dargestellte erfindungsgemäße Bauteil weist gegenüber herkömmlichen Bauteilen geringere Kosten und eine vereinfachte Herstellung auf, da durch dieFIG. 14 shows a module board M which is equipped with carriers T-j_ and T2 on both surfaces. The beams T] _ and T2 speak to the carriers T of the first embodiment of the component according to the invention and have a plurality of memory chips C] _ or C2 and their electrical connections B. The carriers T-j_ and T2 provided with the memory chips are surrounded together with a part of the module board and with their outer connection points A by an enveloping mass H, so that they are enveloped by a part of the module board M and the enveloping mass H as a covering. The component according to the invention represented by FIG. 14 has lower costs and simplified manufacture compared to conventional components, since
Verwendung von mehreren Speieherchips C gemeinsamen Trägern T und einer allen Speicherchips C nebst Träger T gemeinsamen Umhüllung die Anzahl der zur Herstellung einer auf beiden Oberflächen mit Speicherelementen bestückten Modulplatine M benötigten Prozeßschritte reduziert.Using a plurality of memory chips C common carriers T and a sheath common to all memory chips C together with carriers T reduces the number of process steps required to produce a module board M equipped with memory elements on both surfaces.
Es sei noch erwähnt, daß die bei der zweiten Ausführungsform der Erfindung verwendeten Träger T aus standardisierten Ele¬ menten (Bänder von Trägerstrukturen) hergestellt werden und zum Anschluß und zur Befestigung auf der Modulplatine M wahlweise Steckverbindungen oder Oberflächenverbindungen, i.a. gelötet, aufweisen können.It should also be mentioned that the supports T used in the second embodiment of the invention are produced from standardized elements (strips of support structures) and, for connection and for attachment to the module board M, either plug-in connections or surface connections, i.a. soldered, can have.
Die Anzahl der beim erfindungsgemäßen Halbleiter-Speicherbau- teil verwendeten Speicherchips C ist vorzugsweise so gewählt, daß sich für die Dateneingangs-, Datenausgangsanschlüsse des Halbleiter-Speicherbauteils eine Anzahl von n-4 oder (n-4)+l ergibt, mit n>0. Der letztere Fall erlaubt die Verwendung eines sogenannten Parity-Bits beim Halbleiter-Speicherbauteil. The number of memory chips C used in the semiconductor memory component according to the invention is preferably selected so that the number of n-4 or (n-4) + 1 results for the data input and data output connections of the semiconductor memory component, with n> 0 . The latter case allows the use of a so-called parity bit in the semiconductor memory device.

Claims

Patentansprüche claims
1. Halbleiter-Speicherbauteil mit mehreren Speicherchips (C) , die sich in einer gemeinsamen Umhüllung (U) befinden, wobei die Speicherchips (C) Kontaktpunkte (K) aufweisen, die über elek¬ trische Verbindungen (B) mit äußeren Anschlußpunkten (A) eines Trägers (T) verbunden sind, dadurch gekennzeichnet, daß die Speicherchips (C) alle gemein¬ sam auf den Träger (T) aufgebracht sind, und daß jedem Kontakt- punkt (K) jedes Speicherchips (C) genau ein äußerer Anschlu߬ punkt (A) des Trägers (T) zugeordnet ist, so daß die Summe der Zahl der Kontaktpunkte (K) der Speicherchips (C) gleich der Zahl der äußeren Anschlußpunkte (A) des Trägers (T) ist.1. Semiconductor memory component with a plurality of memory chips (C) which are located in a common casing (U), the memory chips (C) having contact points (K) which are connected to external connection points (A) via electrical connections (B) of a carrier (T), characterized in that the memory chips (C) are all applied together to the carrier (T), and that each contact point (K) of each memory chip (C) has exactly one external connection point (A) of the carrier (T) is assigned so that the sum of the number of contact points (K) of the memory chips (C) is equal to the number of outer connection points (A) of the carrier (T).
2. Halbleiter-Speicherbauteil mit mehreren Speicherchips (C) , die sich in einer gemeinsamen Umhüllung (U) befinden, wobei die Speicherchips (C) Kontaktpunkte (K) aufweisen, die über elek¬ trische Verbindungen (B) mit äußeren Anschlußpunkten' (A) eines Trägers (T) verbunden sind, wobei beim Betrieb der Speicher- chips (C) jeweils einige der Kontaktpunkte (K) und der äußeren Anschlußpunkte (A) Datensignale führen, dadurch gekennzeichnet, daß die Speicherchips (C) alle gemein¬ sam auf den Träger (T) aufgebracht sind, und daß jedem ein solches Datensignal führenden Kontaktpunkt (K) jedes Speicher- chips (C) genau ein äußerer das jeweilige Datensignal führender Anschlußpunkt (A) des Trägers (T) zugeordnet ist, so daß die Summe der Zahl der Datensignale führenden Kontaktpunkte (K) der Speicherchips (C) gleich der Zahl der Datensignale führenden äußeren Anschlußpunkte (A) des Trägers (T) ist.2. The semiconductor memory device having a plurality of memory chips (C) that are located in a common enclosure (U), wherein the memory chip (C) contact points (K) which on elek¬ tric compounds (B) with external connection points' (A ) of a carrier (T) are connected, wherein during operation of the memory chips (C) some of the contact points (K) and the outer connection points (A) each carry data signals, characterized in that the memory chips (C) all together the carrier (T) are applied, and that each contact point (K) carrying such a data signal of each memory chip (C) is assigned exactly one external connection point (A) carrying the respective data signal of the carrier (T), so that the sum of the The number of data points carrying contact points (K) of the memory chips (C) is equal to the number of data connection leading outer connection points (A) of the carrier (T).
3. Halbleiter-Speicherbauteil nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß der Träger (T) auf einer Modul¬ platine (M) aufgebracht und mit dieser über seine äußeren Anschlußpunkte (A) elektrisch verbunden ist, und daß die den Speieherchps (C) gemeinsame Umhüllung (U) auch die äußeren Anschlußpunkte (A) des Trägers umhüllt.3. A semiconductor memory device according to claim 1 or 2, characterized in that the carrier (T) is applied to a module board (M) and is electrically connected to it via its outer connection points (A), and that the Speieherchps (C) common sheath (U) also sheathed the outer connection points (A) of the carrier.
4. Halbleiter-Speicherbauteil nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß der Träger (T) auf einer Modul¬ platine (M) aufgebracht und mit dieser über seine äußeren Anschlußpunkte (A) elektrisch verbunden ist, und daß die den Speicherchps (C) gemeinsame Umhüllung (U) die äußeren Anschlußpunkte (A) des Trägers (T) freiläßt.4. A semiconductor memory device according to claim 1 or 2, characterized in that the carrier (T) is applied to a module board (M) and is electrically connected to it via its outer connection points (A), and that the memory chips (C ) common covering (U) leaves the outer connection points (A) of the carrier (T) free.
5. Halbleiter-Speicherbauteil nach Anspruch 3 oder 4, dadurch gekennzeichnet, daß sich mehrere Träger (T) auf der Modulplatine (M) befinden.5. Semiconductor memory component according to claim 3 or 4, characterized in that there are a plurality of carriers (T) on the module board (M).
6. Halbleiter-Speicherbauteil nach Anspruch 5, dadurch gekennzeichnet, daß sich die Träger (T) auf beiden Oberflächen der Modulplatine (M) befinden.6. A semiconductor memory device according to claim 5, characterized in that the carriers (T) are on both surfaces of the module board (M).
7. Halbleiter-Speicherbauteil nach einem der Ansprüche 1 bis 6, dadurch gekennzeichnet, daß die Gesamtzahl der mittels eines oder mehrerer Träger (T) auf der Modulplatine (M) aufgebrachten und mit ihr elektrisch verbundenen Speicherchips (C) so gewählt ist, daß sich für Dateneingangs/-ausgangsanschlüsse des Halbleiter-Speicherbauteils eine Anzahl von n-4 ergibt mit n>0.7. Semiconductor memory component according to one of claims 1 to 6, characterized in that the total number of the by means of one or more carriers (T) on the module board (M) and electrically connected to it memory chips (C) is chosen so that for data input / output connections of the semiconductor memory component, a number of n-4 results with n> 0.
8. Halbleiter-Speicherbauteil nach einem der Ansprüche 1 bis 6, dadurch gekennzeichnet, daß die Gesamtzahl der mittels eines oder mehrerer Träger (T) auf der Modulplatine (M) aufgebrachten und mit ihr elektrisch verbundenen Speicherchips (C) so gewählt ist, daß sich für Dateneingangs/-ausgangsanschlüsse des Halb¬ leiter-Speicherbauteils eine Anzahl von (n-4)+l ergibt mit n>0. 8. Semiconductor memory component according to one of claims 1 to 6, characterized in that the total number of the by means of one or more carriers (T) on the module board (M) and electrically connected to it memory chips (C) is chosen so that for data input / output connections of the semiconductor memory component, a number of (n-4) + 1 results in n> 0.
9. Halbleiter-Speicherbauteil nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die Umhüllung (U) aus Plastikmasse ist.9. Semiconductor memory component according to one of the preceding claims, characterized in that the envelope (U) is made of plastic mass.
10. Halbleiter-Speicherbauteil nach einem der vorhergehenden10. Semiconductor memory component according to one of the preceding
Ansprüche, dadurch gekennzeichnet, daß die gemeinsame Umhüllung (U) in direkter Berührung mit den Speicherchips (C) und deren elektrischen Verbindungen (B) angeordnet ist.Claims, characterized in that the common casing (U) is arranged in direct contact with the memory chips (C) and their electrical connections (B).
11. Halbleiter-Speicherbauteil nach einem der Ansprüche 1 bis 9, dadurch gekennzeichnet, daß die gemeinsame Umhüllung (U) berührungsfrei bezüglich der Speicherchips (C) und deren elek¬ trische Verbindungen (B) angeordnet ist.11. A semiconductor memory component according to one of claims 1 to 9, characterized in that the common casing (U) is arranged in a contact-free manner with respect to the memory chips (C) and their electrical connections (B).
12. Halbleiter-Speicherbauteil nach einem der Ansprüche 1 bis 11, dadurch gekennzeichnet, daß die Speicherchips (C) von derselben Speicherart sind.12. Semiconductor memory component according to one of claims 1 to 11, characterized in that the memory chips (C) are of the same type of memory.
13. Halbleiter-Speicherbauteil nach einem der Ansprüche 1 bis 11, dadurch gekennzeichnet, daß die Speicherchips (C) von verschiedener Speicherart sind.13. Semiconductor memory component according to one of claims 1 to 11, characterized in that the memory chips (C) are of different types of memory.
14. Verfahren zur Herstellung eines Halbleiter-Speicherbauteils mit mehreren Speicherchips (C) , die sich in einer gemeinsamen Umhüllung (U) befinden, dadurch gekennzeichnet, daß die Speicherchips (C) auf einem gemeinsamen Träger (T) aufgebracht und mit elektrischen Ver¬ bindungen (B) versehen werden, wobei jedem Kontaktpunkt (K) jedes Speicherchips (C) genau ein äußerer Anschlußpunkt (A) des Trägers (T) zugeordnet wird, so daß die Summe der Zahl der Kontaktpunkte (K) der Speicherchips (C) gleich der Zahl der äußeren Anschlußpunkte (A) des Trägers (T) wird, und daß der Träger (T) mit den darauf befindlichen Speicherchips (C) mit der gemeinsamen Umhüllung (U) versehen wird. 15. Verfahren zur Herstellung eines Halbleiter-Speicherbauteils mit mehreren Speicherchips (C) , die sich in einer gemeinsamen Umhüllung (U) befinden,14. A method for producing a semiconductor memory component with a plurality of memory chips (C), which are located in a common casing (U), characterized in that the memory chips (C) are applied to a common carrier (T) and with electrical connections (B) are provided, each contact point (K) of each memory chip (C) being assigned exactly one external connection point (A) of the carrier (T), so that the sum of the number of contact points (K) of the memory chips (C) is equal to that Number of outer connection points (A) of the carrier (T), and that the carrier (T) with the memory chips (C) located thereon is provided with the common casing (U). 15. Method for producing a semiconductor memory component with a plurality of memory chips (C) which are located in a common casing (U),
" 5 dadurch gekennzeichnet, daß die Speicherchips (C) auf einem gemeinsamen Träger (T) aufgebracht und mit elektrischen Ver¬ bindungen (B) versehen werden, wobei jedem beim Betrieb der Speicherchips (C) ein Datensignal führenden Kontaktpunkt (K) jedes Speicherchips (C) genau ein äußerer Anschlußpunkt (A) des"5 characterized in that the memory chips (C) are applied to a common carrier (T) and provided with electrical connections (B), each contact point (K) of each memory chip carrying a data signal during operation of the memory chips (C). C) exactly one external connection point (A) of the
10 Trägers (T) zugeordnet wird, so daß die Summe der Zahl der die Datensignale führenden Kontaktpunkte (K) der Speicherchips (C) gleich der Zahl der zugeordneten, äußeren Anschlußpunkte (A) des Trägers (T) wird, und daß der Träger (T) mit den darauf befindlichen Speicherchips (C) mit der gemeinsamen Umhüllung10 carrier (T) is assigned so that the sum of the number of contact points (K) carrying the data signals of the memory chips (C) is equal to the number of assigned external connection points (A) of the carrier (T), and that the carrier ( T) with the memory chips (C) on it with the common casing
15 (U) versehen wird.15 (U) is provided.
16. Verfahren zur Herstellung eines Halbleiter-Speicherbauteils nach Anspruch 14 oder 15, dadurch gekennzeichnet, daß der Träger (T) mit den darauf 20 befindlichen Speicherchips (C) beim Aufbringen der gemeinsamen Umhüllung (U) auf einer Modulplatine (M) befestigt und mit dieser über seine äußeren Anschlußpunkte (A) elektrisch verbun¬ den wird, und daß der Träger (T) anschließend mit einem, die der Modulplatine (M) abgewandte Seite des Trägers (T) bedecken- 25 den Formstück (F) versehen wird, so daß die gemeinsame Umhül¬ lung (U) das Formstück (F) und den unter dem Träger (T) befind¬ lichen Teil der Modulplatine (M) umfaßt.16. A method for producing a semiconductor memory device according to claim 14 or 15, characterized in that the carrier (T) with the memory chips (C) located thereon 20 is attached to the module board (M) when the common casing (U) is applied and with this is electrically connected via its outer connection points (A), and that the support (T) is then provided with a shaped piece (F) covering the side of the support (T) facing away from the module board (M), so that the common covering (U) comprises the shaped piece (F) and the part of the module board (M) located under the carrier (T).
17. Verfahren zur Herstellung eines Halbleiter-Speicherbauteils 30 nach Anspruch 14 oder 15, dadurch gekennzeichnet, daß der Träger (T) mit den darauf befindlichen Speicherchips (C) beim Aufbringen der gemeinsamen Umhüllung (U) auf einer Modulplatine (M) befestigt und mit die¬ ser über seine äußeren Anschlußpunkte (A) elektrisch verbunden wird, und daß der Träger (T) anschließend mit einer, die der Modulplatine (M) abgewandten Seite des Trägers (T) umschließen¬ de Hüllmasse (H) versehen wird, so daß die gemeinsame Umhüllung (U) , die Hüllmasse (H) und den unter dem Träger (T) befindli- chen Teil der Modulplatine (M) umfaßt.17. A method for producing a semiconductor memory component 30 according to claim 14 or 15, characterized in that the carrier (T) with the memory chips (C) located thereon when the common casing (U) is attached to a module board (M) and with this electrically connected via its outer connection points (A) and that the carrier (T) is then provided with a shell (H) enclosing the side of the carrier (T) facing away from the module board (M), so that the common shell (U), the shell mass (H) and the part of the module board (M) located under the carrier (T).
18. Verfahren zur Herstellung eines Halbleiter-Speicherbauteils nach Anspruch 14 oder 15, dadurch gekennzeichnet, daß der Träger (T) mit den darauf befindlichen Speicherchips (C) nach dem Aufbringen der gemein¬ samen Umhüllung (U) auf einer Modulplatine (M) befestigt und mit dieser über seine äußeren Anschlußpunkte (A) verbunden wird.18. A method for producing a semiconductor memory device according to claim 14 or 15, characterized in that the carrier (T) with the memory chips (C) located thereon, after the application of the common casing (U), is attached to a module board (M) and is connected to it via its outer connection points (A).
19. Verfahren nach einem der Ansprüche 15 bis 18, dadurch gekennzeichnet, daß der Träger (T) mit der Modulplatine (M) mittels Steckverbindungen elektrisch verbunden wird.19. The method according to any one of claims 15 to 18, characterized in that the carrier (T) is electrically connected to the module board (M) by means of plug connections.
20. Verfahren nach einem der Ansprüche 15 bis 18, dadurch gekennzeichnet, daß der Träger (T) mit der Modulplatine (M) mittels Oberflächenkontakten ("surface mounted") elektrisch verbunden wird.20. The method according to any one of claims 15 to 18, characterized in that the carrier (T) with the module board (M) by means of surface contacts ("surface mounted") is electrically connected.
21. Verfahren nach einem der Ansprüche 15 bis 18, dadurch gekennzeichnet, daß der Träger (T) mit der Modulplatine (M) mittels gelöteter Kontakte elektrisch verbunden wird.21. The method according to any one of claims 15 to 18, characterized in that the carrier (T) with the module board (M) is electrically connected by means of soldered contacts.
22. Verfahren nach Anspruch 18, dadurch gekennzeichnet, daß die gemeinsame Umhüllung (U) mittels eines Spritzverfahrens (post-molded) erzeugt wird.22. The method according to claim 18, characterized in that the common envelope (U) is produced by means of an injection molding process (post-molded).
23. Verfahren nach Anspruch 18, dadurch gekennzeichnet, daß die gemeinsame Umhüllung (U) aus vorgefertigten Bauteilen (pre-molded) erzeugt wird. 23. The method according to claim 18, characterized in that the common envelope (U) is produced from prefabricated components (pre-molded).
EP95908875A 1994-02-07 1995-02-06 Semiconductor storage component with a plurality of storage chips in a shared casing Ceased EP0744084A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE4403733 1994-02-07
DE4403733 1994-02-07
PCT/DE1995/000155 WO1995021459A1 (en) 1994-02-07 1995-02-06 Semiconductor storage component with a plurality of storage chips in a shared casing

Publications (1)

Publication Number Publication Date
EP0744084A1 true EP0744084A1 (en) 1996-11-27

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JP (1) JPH09508496A (en)
KR (1) KR970700940A (en)
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WO (1) WO1995021459A1 (en)

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JP3955712B2 (en) 2000-03-03 2007-08-08 株式会社ルネサステクノロジ Semiconductor device
US20040178514A1 (en) * 2003-03-12 2004-09-16 Lee Sang-Hyeop Method of encapsulating semiconductor devices on a printed circuit board, and a printed circuit board for use in the method

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US3341649A (en) * 1964-01-17 1967-09-12 Signetics Corp Modular package for semiconductor devices
US4642419A (en) * 1981-04-06 1987-02-10 International Rectifier Corporation Four-leaded dual in-line package module for semiconductor devices
JP3125891B2 (en) * 1991-08-20 2001-01-22 日立電線株式会社 Semiconductor device
US5280193A (en) * 1992-05-04 1994-01-18 Lin Paul T Repairable semiconductor multi-package module having individualized package bodies on a PC board substrate
US5337216A (en) * 1992-05-18 1994-08-09 Square D Company Multichip semiconductor small outline integrated circuit package structure

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JPH09508496A (en) 1997-08-26
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TW354859B (en) 1999-03-21

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