EP0734631A1 - Chrominance demodulation with sampling of the input signal at three times the colour subcarrier frequency - Google Patents

Abstract

In a method of demodulating chrominance signals, input signals (CVBS) are sampled at three times the color subcarrier frequency to obtain sampled signals. The sampled signals are demodulated (Du, Dv) at demodulation angles with respect to the color subcarrier phase which demodulation angles differ by 360°/(3*2n), with n being 0, 1 or 2, preferably at demodulation angles of 0° and 120° with respect to the color subcarrier phase, to obtain demodulator output signals (2U/X3; -U/X3 + V). The demodulator output signals (2U/X3; -U/X3 + V) are matrixed (Mx) to obtain demodulated chrominance signals (U, V).

Description

Chrominance demodulation with sampling of the input signal at three times the colour subcarrier frequency

The invention relates to a method and an apparatus for demodulating time- discrete chrominance signals.

Sampled color decoder systems operating at four times the color subcarrier frequency (4Fsc) are well known. This choice of sampling frequency yields the advantage that simple demodulation coefficients can be used, as a multiplication of the chrominance signal by successively 1, 1, -1, -1 yields the demodulated U signal, and a multiplication of the chrominance signal by successively 1, -1, -1, 1 yields the demodulated V signal.

It is, inter alia, an object of the invention to provide a method and an apparatus for demodulating time-discrete chrominance signals which allow for a cheaper implementation in silicon. To this end, a first aspect of the invention provides a method as defined in claim 1. A second aspect of the invention provides an apparatus as defined in claim 2. A third aspect of the invention provides a video signal receiver as defined in claim 8. Advantageous embodiments are defined in the sub-claims.

In the method of demodulating chrominance signals according to the present invention, input signals are sampled at three times the color subcarrier frequency to obtain sampled signals. The sampled signals are demodulated at demodulation angles with respect to the color subcarrier phase which demodulation angles differ by 360°/(3*2ⁿ), with n being 0, 1 or 2, preferably at demodulation angles of 0° and 120° with respect to the color subcarrier phase, to obtain demodulator output signals. The demodulator output signals are matrixed to obtain demodulated chrominance signals.

Sampling at three times the color subcarrier frequency (3Fsc) yields the following advantages. The relative transition bandwidth of FIR filters used in an overall television set architecture including the color decoder is larger for 3Fsc sampling compared to 4Fsc sampling, which results in a smaller number of FIR filter coefficients for the same 2 filter specification. Delay lines can be made shoπer at 3Fsc sampling compared to 4Fsc sampling, also resulting in a smaller silicon surface area.

The disadvantages of sampling at three times the color subcarrier frequency (3Fsc) are that in a straightforward implementation not according to the present invention, the input CNBS signal is demodulated with 0° and 90° Fsc locked oscillator signals, which results in that the successive coefficients for the U channel demodulator are [0, 0.-5V3, -0.5V/3], which differ from the mutually different successive V channel demodulator coefficients [1, -0.5, -0.5]. In a switched capacitor implementation, the dynamic range of this demodulator is reduced due to the fact that matching capacitors are required for the realisation of the multipliers, as the use of mutually different coefficients requires mutually different capacitors whereas matching of two equivalent capacitors in a switched capacitor implementation to better than 0.2% cannot be expected. With not-exactly matched capacitors and hence inaccurate demodulation coefficients, intermodulation distortion can occur in this decoder. As the luminance bandwidth extends from 0 to 5 MHz for PAL, which is rather broad in comparison to me chrominance bandwiddi which is less than 1 MHz, intermodulation between luminance components can easily result into visible chrominance artifacts. The luminance components can be 20 dB higher than the chrominance components because of fall-off due to intermediate frequency LF filtering in the front-end of the television receiver, so that even a small luminance intermodulation error component can result into a visible chrominance artifact. Good bandpass filtering must be used at the input for bandwidth limitation together with careful matching of large capacitor values for an acceptable performance of this demodulator operating at demodulation angles of 0° and 90°. To solve these disadvantages, it is a further characterizing feature of the present invention that demodulation is not carried out at angles of 0° and 90° with respect to the color subcarrier phase, but at demodulation angles which differ by 360°/(3*2ⁿ), with n being 0, 1 or 2. Preferred demodulation angles are 0° and 120°. This latter demodulation at 120° yields the advantage that again, very simple demodulation coefficients can be used just like when a sampling frequency of 4Fsc is used. A slight disadvantage of demodulating at 120° is that some crosstalk of the U channel into the V channel is obtained, which can easily removed by the still further characterizing feature of a matrixing operation. The overall balance of the invention is that a lower sampling frequency is used (3 Fsc rather than 4 Fsc) so that a smaller silicon area is sufficient, while the demodulation coefficients remain very simple thanks to the use of another demodulation angle and a simple matrixing operation. These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

In the drawings:

Fig. 1 shows a first embodiment of a demodulator circuit in accordance with the present invention;

Fig. 2 shows sampling moments and demodulation coefficients; Fig. 3 shows sampling clock pulses used in a second embodiment of a demodulator circuit for NTSC and PAL in accordance with the present invention which is preceded by a comb filter also operating at 3Fsc; Fig. 4 shows sampling moments for NTSC color subcarrier multiplier signals with line to line changes;

Fig. 5 shows sampling moments for PAL color subcarrier multiplier signals with line to line changes;

Fig. 6 shows four states of the second PAL embodiment of a demodulator circuit in accordance with the present invention;

Fig. 7 shows an NTSC demodulator embodiment for line 1, or a PAL demodulator embodiment for lines 1 and 2;

Fig. 8 shows an NTSC demodulator embodiment for line 2, or a PAL demodulator embodiment for lines 3 and 4; Fig. 9 shows a PAL/NTSC demodulator switch control for a single switched capacitor branch of the demodulator embodiment of Fig. 7;

Fig. 10 shows a circuit diagram illustrating the principle for realisation of the matrix stage;

Fig. 11 shows an embodiment of a video signal receiver incorporating the chrominance demodulator embodiment of Fig. 6;

Fig. 12 shows another embodiment of input multipliers for U and V channels;

Fig. 13 shows another realization of an input demodulator stage for 3Fsc sampling; and Fig. 14 shows another switched capacitor realization of a matrixing stage.

In the direct conversion demodulator circuit embodiment of Fig. 1 , the input video signal CVBS is applied to demodulation multipliers Du and Dv through input capacitors Cu and Cv, respectively. The successive demodulation coefficients of the demodulation multiplier Du for the U chrominance signal are [0, 1, -1], which corresponds to a demodulation of the chrominance signal under an angle of 0°, see Fig. 2a. An output of the demodulation multiplier Du is coupled to a U signal input of a matrix circuit Mx through a low-pass filter LPFu which removes the luminance signal components from the output signal of the demodulation multiplier Du. The low-pass filter LPFu supplies a signal 2U/V^/3. The successive demodulation coefficients of the demodulation multiplier Dv for the V chrominance signal are [1 , -1 , 0], which corresponds to a demodulation of the chrominance signal under an angle of 120°, see Fig. 2c. An output of the demodulation multiplier Dv is coupled to a V signal input of a matrix circuit Mx through a low-pass filter LPFv which removes the luminance signal components from the output signal of the demodulation multiplier Dv. The low-pass filter LPFv supplies a signal V - U/V3. The crosstalk component U/V3 is caused by the demodulation angle of 120° instead of 90°. The crosstalk component can easily be removed by the simple matrix circuit Mx. In the matrix circuit Mx, the U signal input is connected to a U signal output of the matrix circuit Mx through a multiplier Ml multiplying by 0.5V/3, and to a first input of an adder A through a multiplier M2 multiplying by 0.5. The V signal input is connected to a second input of the adder A through a multiplier M3 multiplying by 1. An output of the adder A is connected to a V signal output of the matrix circuit Mx.

Fig. 2 shows sampling moments and demodulation coefficients. In Fig. 2a, the waveform sin(w_scnT) is sampled at 0, Ts and 2Ts, where Ts is the sample period l/3Fsc. This corresponds to demodulation coefficients 0, 0.5\/3 and -0.5^3. These coefficients can be implemented by simple multiplications by 0, + 1 and -1 (see demodulation multiplier Du), respectively, followed by a multiplication by Q.S/2 in multiplier Ml of the matrix circuit Mx. As the sign is no problem, the same capacitor can be used for both coefficients + 1 and - 1.

In Fig. 2b, the waveform cos(w_scnT), which is sin(w_scnT) turned over 90°, is sampled at 0, Ts and 2Ts. This corresponds to mutually differing demodulation coefficients + 1 , -0.5 and -0.5, a switched capacitor implementation of which needs at least two very well mutually matching capacitors. Consequently, in accordance with an aspect of the present invention illustrated by means of Fig. 2c, a demodulation angle different from 90° is used.

In Fig. 2c, the waveform cos(w_scnT + τ/6), which is sin(w_scnT) turned over 120°, is sampled at 0, Ts and 2Ts. This corresponds to demodulation coefficients +0.5^3, -0.5^3 and 0. These coefficients can be implemented by simple multiplications by + 1, -1 and 0 (see demodulation multiplier Dv), respectively, and one capacitor suffices in a switched capacitor implementation so that no capacitor matching problems occur.

The chrominance demodulation is in accordance with a further aspect of the invention preferably used in a video input processor arrangement which contains a multi- standard color decoder which is preceded by a PAL/NTSC Y/C logical video comb filter (like Philips IC SAA4960) and followed by baseband U V comb filters (like Philips IC TDA4661). A color subcarrier locked clock has been chosen for the Y/C comb filter because it is more stable and less noisy than a line referenced clock and to avoid any aliasing that may occur when the chrominance is subsequently demodulated in the color decoder with a color subcarrier locked clock. The 3Fsc sampling clock is reset at the beginning of each subsequent line which ensures that (for standard PAL/NTSC) pixels from line to line fall exactly under one another for proper combing (although in PAL there is the effect of the 25 Hz offset with regard to the line frequency, which is negligible).

For standard NTSC signals, there are exactly 227.5 color subcarrier cycles per line period. Thus, the 3Fsc sampling clock is realised in such a way that there are 682 pixels per line period, the clock being reset at the start of each line. This implies that the sampling instants for the NTSC color subcarrier shift by 60° each consecutive line. The 2 line 3Fsc modified NTSC clock is illustrated in Fig. 3a. The first line (Fsc) of Fig. 3a shows a clock signal with frequency Fsc, the second line shows a clock signal with frequency 3Fsc, and the third line (NTSC 3Fsc) shows the clock signal of the second line but with a reset at the start of each video line N, N+ l, N+2, .. in accordance with the present aspect of the invention.

On the other hand, for standard PAL signals, there are 283.75 + 1/625 color subcarrier cycles per line period. The 3Fsc sampling clock is such that there are 851 pixels per line, with a reset at the start of each line. This 4 line modified 3Fsc PAL clock is illustrated in the third line of Fig. 3b. The sampling instants for the PAL color subcarrier advance by 30° each consecutive line. The PAL offset 3/625 * l/(3Fsc) is not included in the sampling clock. This has negligible effect for PAL combing over 4 lines. Effectively, all that happens is that the starting point for the video is slightly delayed each line compared to the previous line, giving a net delay of exactly 1.5 3Fsc clock periods over one field - this is reset at the start of the next field. This shift of video from line to line is not noticeable on the screen.

The need for pixels to fall exactly under each other is less critical for the U/V baseband comb filters (as they have baseband delay lines) than for the Y/C comb filter. In the Philips IC TDA4661, the sampling clock (3 MHz) is directly locked to the line frequency. When combined with the color decoder, however, the sampling clock for the delay lines must be directly related to the Fsc sampling clock used in the color decoder with Y/C comb filter arrangement (otherwise pre-filtering would be required but even still a low frequency beat would arise which could not be eliminated and so this method could not be used). At least 26 dB suppression is required of the cross-chrominance in the case of PAL. Considering a 1 % amplitude error in the delay lines themselves, a maximum delay error of +_ 12 ns is acceptable from one line to the next. For standard PAL/NTSC with the modified 3Fsc clocks of Fig. 3, it is possible to use a modified Fsc clock for the U/V delay lines. For PAL, this would mean a clock having 283.75 color subcarrier cycles per line period with a reset at the start of each line. For NTSC, there would be exactly 227.5 clock cycles per line. The choice of sampling frequency for the SECAM decoder is in principle free but 1645 times the line frequency is a good choice since a nominally correct one line delay can be generated in the U/V comb filters.

Fig. 4 shows sampling moments for NTSC color subcarrier multiplier signals with line to line changes. As described above, the sampling instants with reference to the color subcarrier shift by 60° each line for NTSC.

In Fig. 4a, the waveform sin(w_scnT) is sampled at 0, Ts and 2Ts (interrupted lines) during odd lines 1 ..., and at 0.5Ts, 1.5Ts and 2.5Ts (dotted lines) during even lines 2 ..., where Ts is the sample period l/3Fsc. This corresponds to successive demodulation coefficients 0, 0.5V3 and -0.5^3 during the odd lines, and 0.5^3, 0, -0.5^3 during the even lines.

In Fig. 4b, the waveform cos(w_scnT), which is sin(w_scnT) advanced by 90° , is sampled at 0, Ts and 2Ts (interrupted lines) during odd lines 1 ... , and at 0.5Ts, 1.5Ts and 2.5Ts (dotted lines) during even lines 2 .... This corresponds to mutually differing successive demodulation coefficients + 1, -0.5 and -0.5 during the odd lines, and 0.5, -1 and 0.5 during the even lines. Two different sets of coefficients must be used from line to line in order to reconstitute the 0° and 90° U and V channel multiplier waveforms for a straightforward demodulation not in accordance with the present invention. A different switched capacitor circuit configuration would be required from line to line in order to realise these coefficients. The demodulated U and V signals would show a line to line variation as a result of this change of architecture from line to line.

To solve this problem, the same type of demodulating scheme can be adopted, as described with reference to Figs. 1, 2, whereby the chrominance is demodulated at 0° and 120° with reference to the color subcarrier in the U and V channels, respectively. The coefficients required for demodulation are shown in Fig. 4a,c for the U, V color subcarrier demodulation signals. In Fig. 4c, the waveform cos(w_scnT + τr/6), which is sin(w_scnT) advanced by 120°, is sampled at 0, Ts and 2Ts (interrupted lines) during odd lines 1 ..., and at 0.5Ts, 1.5Ts and 2.5Ts (dotted lines) during even lines 2 .... This corresponds to demodulation coefficients +0.5^3, -0.5V3 and 0 during the odd lines, and 0, -0.5\/3 and 0.5\ 3 during the even lines. These coefficients can be implemented by simple multiplications by + 1 , -1 and 0 (see demodulation multiplier Dv), respectively, and one capacitor suffices in a switched capacitor implementation so that no capacitor matching problems occur.

Demodulation, in fact, takes place with successive coefficients [0, 1, -1] in 2 different sequences for the U and V channels, followed by a fixed matrix. The block diagram of the proposed realisation is the same as that shown in Fig. 1 , with the difference that during odd lines (1), the demodulation coefficients are as shown in Fig. 1, while during even lines (2), the demodulation coefficients are [1, 0, -1] for U and [0, -1 , 1] for V. The architecture thus remains the same from line to line, in spite of the rotation of coefficients (controlled by the horizontal sync frequency clock H). All that change are the clocks that control the sequence in which the coefficients [0, 1, -1] are used for multiplication with the chrominance signal - the physical architecture remains the same, reducing the chance of line to line disturbances.

A similar scheme can be used for PAL demodulation. There is now, however, a 30° advance in the phase of the 3Fsc sampling clock with respect to the regenerated color subcarrier signals. Fig. 5 illustrates the coefficients required for regeneration of the color subcarrier multiplier signals U (Fig. 5a), U phase shifted by -JΓ/6 (Fig. 5b), V (Fig. 5c), and V phase shifted by τr/6 (Fig. 5d) for 4 consecutive lines, with each sequence of coefficients being repeated every 4 lines. If a direct realisation of the PAL decoder were envisaged, with 0° and 90° demodulation of the input chrominance, then it is clear that because of inaccuracies in the generation of the absolute values of these coefficients and the mutual matching required of these coefficients in a switched capacitor solution, a visible line to line distortion would occur in the demodulated chrominance which would be unacceptable.

The solution presented here is based on the simple multiplication of the input chrominance with coefficients [0, 1, -1] from line to line, followed by a fixed matrix for reconstituting the demodulated U and V signals. The way in which to achieve this can be ascertained with the help of Fig. 5. Fig. 5 shows sampling moments for PAL color subcarrier multiplier signals with line to line changes.

On the first video line 1, the chrominance is multiplied by 0° and 120° phase shifted color subcarrier locked signals, i.e. U (Fig. 5a) and V phase shifted by τ/6 (Fig. 5d), as indicated by interrupted lines. This is equivalent to [0, 1, -1] in the U channel and [1 , -1 , 0] in the V channel. On the second video line 2, the chrominance is multiplied by -30° and

90° phase shifted color subcarrier locked signals, i.e. U phase shifted by -JΓ/6 (Fig. 5b) and V (Fig. 5c), as indicated by thin continuous lines. Again, the coefficients [0, 1 , -1] and [1, - 1 , 0] are used for the U channel and V channel respectively.

For die third video line 3, color subcarrier signals U (Fig. 5a) and V phase shifted by τ/6 (Fig. 5d) are used again, corresponding to coefficients [1, 0, -1] and [0, -1 , 1], respectively. Dotted lines indicate the sampling instants.

Finally, for the fourth consecutive video line 4, color subcarrier signals U phase shifted by -x/6 (Fig. 5b) and V (Fig. 5c), corresponding to respective coefficients [1 , 0, -1] and [0, -1, 1], are used. Fat continuous lines indicate the sampling instants. The demodulation sequence repeats itself beginning with the fifth line.

The block diagram illustrating the above algorithm is given in Fig. 6. Fig. 6 shows four states of the second PAL embodiment of a demodulator circuit in accordance with the present invention. Video lines 1 +4k (k integer) are handled according to Fig. 6a, video lines 2+4k are handled according to Fig. 6b, video lines 3+4k are handled according to Fig. 6c, and video lines 4+4k are handled according to Fig. 6d. Each of the shown circuits largely corresponds to that of Fig. 1 , with the following modifications. The coefficients applied to the demodulation multipliers Du, Dv are as described wid reference to Figs. 5a-5d. The demodulation multipliers Du, Dv are controlled by a H/2 frequency clock signal. The inputs and outputs of the matrix circuit Mx are preceded and followed, respectively, by cross-switches XS1, XS2 controlled by a H frequency clock signal. The cross-switch XS 1 applies the output of the demodulation multiplier Du to the upper or the lower input of the matrix circuit Mx, and applies the output of the demodulation multiplier Dv to the other input of the matrix circuit Mx. The cross-switch XS2 applies the upper or lower output of the matrix circuit Mx to the U output terminal, and applies the other output of the matrix circuit Mx to the V output terminal.

The major advantage again in this PAL demodulator, is that there is no fundamental change in architecture from line to line, in spite of the advance by 30° of the phase of the modified 3Fsc sampling clock with respect to the actual color subcarrier. This reduces the chance of a four line pattern appearing after the demodulation of say a uniform color covering a large area of the TV screen. The angle between the U and V channel regenerated color subcarrier signals remains + 120° from line to line, so that the same matrix circuit can be used for each line. This does involve multiplexing from line to line (controlled by the H clock). The same order of coefficients [0, 1, -1] is used every two lines and these coefficients are the same as for those for NTSC from line to line. The only difference is that a H/2 clock is used to change the order of the [0, 1, -1] coefficients for PAL, whereas a H clock is used for NTSC.

Correction for the alternating V channel signal in PAL must occur after the matrix circuit Mx when the U and V signals are completely separated from one another. Similarly, multiplication of the U and V channel signals by a factor of 2 can occur after the matrix.

In a practical realisation, the input demodulator stage can be designed in such a way that AC coupling can be incorporated at the input without any extra complexity in the hardware being required. The algorithm depicted in the following table illustrates the principle involved in the U and V demodulation and AC coupling. a) for the odd lines 1 +2k for the NTSC decoder or for lines l +4k and 2+4k for the PAL decoder

Input sample: A B C D E F Sample clock phase: 1 2 3 1 2 3

After AC coupling: B-A C-B D-C E-D F-E

Demodulated U: 0 C-B -D+C 0

Demodulated V: B-A -C+B 0 E-D nT (n+ l)T (n+2)T

b) for the even lines 1 +2k for the NTSC decoder or for lines 1 +4k and 2+4k for the PAL decoder

Input sample: A B C D E F

Sample clock phase: 1 2 3 1 2 3

After AC coupling: B-A C-B D-C E-D F-E

Demodulated U: B-A 0 -D+C E-D

Demodulated V: 0 -C+B D-C 0 nT (n+ l)T (n+2)T

AC coupling is combined in a single stage together with multiplication with various orders of the coefficients [0, 1, -1]. The hardware realisation for PAL or NTSC is exactly the same - only the line control clocks change. For NTSC, a H clock is used to ensure that the switching order changes from line to line. For PAL, a H/2 clock ensures that the switching order only changes every 2 lines.

An actual realisation for a single-ended version of the switched capacitor demodulator input stage is illustrated in Figs. 7 and 8, for the two different switching orders that can occur for PAL/NTSC. There are of course other realisations possible, especially differential, since it is very easy to multiply by 1 and -1 with a differential circuit. Fig. 7 shows an NTSC demodulator for line 1, or a PAL demodulator for video lines 1 and 2. Fig. 8 shows an NTSC demodulator for line 2, or a PAL demodulator for video lines 3 and 4. In the upper half of Figs. 7 and 8, the chrominance input signal is applied to the inverting input of a first amplifier OTA1 through a first series connection of a switch S2, a capacitor Cl and a switch S7, and through a second series connection of a switch S4, a capacitor C2 and a switch S9. An output signal of the amplifier OTA1 is fed back to the interconnection of the switch S2 and the capacitor Cl through a switch SI, and to the interconnection of the switch S4 and the capacitor C2 through a switch S3. The interconnection between the capacitor Cl and the switch S7 is connected to ground through a switch S8. The interconnection between the capacitor C2 and the switch S9 is connected to ground through a switch S10. In this connection, "ground" can be any suitably chosen fixed reference voltage.

The chrominance input signal is also applied to me non-inverting input of the first amplifier OTA1 through a first series connection of a switch S5, a capacitor C3 and a switch S13, and through a second series connection of a switch S6, a capacitor C4 and a switch S16. The interconnection between the capacitor C3 and the switch S5 is connected to ground through a switch Sl l. The interconnection between the capacitor C3 and the switch S13 is connected to ground through a switch S12. The interconnection between the capacitor C4 and the switch S6 is connected to ground through a switch S14. The interconnection between the capacitor C4 and the switch S16 is connected to ground through a switch S15. The output of the first amplifier OTA1 is connected to a first output thru a parallel arrangement of two switches S17 and S18 for furnishing a multiplied U signal at 0°.

In the lower half of Figs. 7 and 8, the chrominance input signal is applied to the inverting input of a second amplifier OTA2 through a first series connection of a switch S22, a capacitor C5 and a switch S27, and through a second series connection of a switch S24, a capacitor C6 and a switch S29. An output signal of the amplifier OTA2 is fed back to me interconnection of the switch S22 and the capacitor C5 through a switch S21, and to the interconnection of the switch S24 and the capacitor C6 through a switch S23. The interconnection between the capacitor C5 and the switch S27 is connected to ground through a switch S28. The interconnection between the capacitor C6 and the switch S29 is connected to ground through a switch S30.

The chrominance input signal is also applied to the non-inverting input of the second amplifier OTA2 through a first series connection of a switch S25, a capacitor C7 and a switch S33, and through a second series connection of a switch S26, a capacitor C8 and a switch S36. The interconnection between the capacitor C7 and the switch S25 is connected to ground through a switch S31. The interconnection between the capacitor C7 and the switch S33 is connected to ground through a switch S32. The interconnection between the capacitor C8 and the switch S26 is connected to ground through a switch S34. The interconnection between the capacitor C8 and the switch S36 is connected to ground through a switch S35. The ouφut of the second amplifier OTAl is connected to a second output thru a parallel arrangement of two switches S37 and S38 for furnishing a multiplied V signal at 120°.

Figs. 7 and 8 differ in the switching phases of the switches and in the samples stored on the capacitors, as shown in the tables below.

Samples stored on capacitors.

Cl C2 C3 C4 C5 C6 C7 C8

Fig 7 +C +C -B -D +B +B -A -C

Fig 8 +B +C -A -D +B +D -C -C

Switch phases.

F S S S S S s s S S S S s S S S s s S i 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 g 0 1 2 3 4 5 6 7 8

7 1 3 2 3 2 1 1 3 2 3 1 2 1 2 1 2 1 2

8 3 2 2 3 1 1 3 2 2 3 3 1 3 2 1 2 2 3

F S s S S S S S S S S S S S S S S S S i 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 g 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8

7 1 2 3 2 1 3 1 2 3 2 3 1 3 1 3 1 1 3

8 1 2 2 1 3 3 1 2 2 1 2 3 2 1 3 1 1 2 The circuit shown is based on a very fast inverting and non-inverting sample- and-hold stage for the realisation of coefficients [0, 1 , -1]. The capacitors marked with (AC) have a triple purpose in the circuit shown, namely i) removal of the attenuation that would otherwise occur because of the parasitic input capacitors of the OTA's. This occurs by virtue of the exactly balanced impedances at both inputs of each OTA. There is thus a very high loop gain, ii) exact compensation of DC offsets arising from clock feedthrough errors iii) AC coupling.

It is only the clocking order of the capacitors marked (AC) which determines that they be also used for AC coupling. These capacitors are required in any case for reasons i) and ii) mentioned above and thus there is no extra hardware involved.

Fig. 9 shows how the switching order can be controlled by the horizontal sync frequency (H) clock for NTSC or the H/2 clock for PAL. For simplicity, only "H" is indicated in Fig. 9; for PAL, "H/2" should be read where "H" is shown. The architecture is such that there are only two different sequences of coefficients that have to be used on consecutive lines for NTSC or every second line for PAL. The diagram illustrates how a simple modular approach can be adopted in the layout of each capacitor stage of the demodulator - only simple CMOS switches are used for H (or H/2) control of the switching order. The construction is greatly simplified compared to say if a different valued capacitor had to be used to create a different valued coefficient each line for PAL/NTSC as would be the case in a direct realisation of the demodulator operating at demodulation angles 0° and 90° unlike the present invention. Fig. 9 illustrates how the switches S5, Sl l, S12 and S13 of the branch containing the switches S5, Sl l, the capacitor C3, and the switches S 12 and S13 of Fig. 7 are controlled. Fig. 9a shows the circuit diagram, Fig. 9b shows three phase control signals l, 2 and Φ3 in relation to a color subcarrier frequency signal with period 1/Fsc. The phase control signals Φl, Φ2 and Φ3 are mutually shifted in phase by 120° .

Switch S5 (implemented as an NFET) is controlled by the following arrangement. Main terminals of an NFET (=NMOSFET) Tl are connected to corresponding main terminals of a PFET (=PMOSFET) T3. One connected pair of the main terminals is connected to a gate of the switch S5, while the other pair receives the Φ2 phase control signal. A gate of the NFET Tl receives a H frequency signal, while a gate of the PFET T3 receives an inverted H frequency signal. Main terminals of an NFET T5 are connected to corresponding main terminals of a PFET T7. One connected pair of the main terminals is connected to d e gate of the switch S5, while the other pair receives the Φl phase control signal. A gate of the PFET T7 receives a H frequency signal, while a gate of the NFET T5 receives an inverted H frequency signal.

Switch Sl l (implemented as an NFET) is controlled by the following arrangement. Main terminals of an NFET Tl 1 are connected to corresponding main terminals of a PFET T13. One connected pair of the main terminals is connected to a gate of the switch Sl l , while the other pair receives the Φl phase control signal. A gate of the NFET Ti l receives a H frequency signal, while a gate of the PFET T13 receives an inverted H frequency signal. Main terminals of an NFET T15 are connected to corresponding main terminals of a PFET T17. One connected pair of the main terminals is connected to the gate of the switch Sl l , while the other pair receives the Φ3 phase control signal. A gate of the PFET T17 receives a H frequency signal, while a gate of the NFET T15 receives an inverted H frequency signal.

Switch S12 (implemented as an NFET) is controlled by the following arrangement. Main terminals of an NFET T21 are connected to corresponding main terminals of a PFET T23. One connected pair of the main terminals is connected to a gate of the switch S12, while the other pair receives the Φ2 phase control signal. A gate of the NFET T21 receives a H frequency signal, while a gate of the PFET T23 receives an inverted H frequency signal. Main terminals of a NFET T25 are connected to corresponding main terminals of a PFET T27. One connected pair of the main terminals is connected to the gate of the switch S12, while the other pair receives the Φl phase control signal. A gate of the PFET T27 receives a H frequency signal, while a gate of the NFET T25 receives an inverted H frequency signal.

Switch S13 (implemented as an NFET) is controlled by the following arrangement. Main terminals of an NFET T31 are connected to corresponding main terminals of a PFET T33. One connected pair of the main terminals is connected to a gate of the switch S13, while the other pair receives the Φl phase control signal. A gate of the NFET T31 receives a H frequency signal, while a gate of the PFET T33 receives an inverted H frequency signal. Main terminals of an NFET T35 are connected to corresponding main terminals of a PFET T37. One connected pair of the main terminals is connected to the gate of the switch S13, while the other pair receives the Φ3 phase control signal. A gate of the PFET T37 receives a H frequency signal, while a gate of the NFET T35 receives an inverted H frequency signal. In Fig. 10, a method for realisation of the output matrix stage Mx is given. This circuit appears after the U and V channel low-pass filters which bandlimit the chrominance signals to < 0.5 MHz (from > 5 MHz, in principle). The matrix is such that for say NTSC, half the U channel signal is added to the V channel signal, while the U channel signal itself is multiplied by O.Sv/3. Good matching can be obtained for similar valued capacitors in the matrix. No matching is required for the V3 capacitor with the V channel. An error in the absolute value of this capacitor only produces a gain error in the U channel.

In Fig. 10, the demodulated signal -2U(nT)Λ/3 is applied to an inverting input of an amplifier OTA10 thru a first series arrangement of a switch 1001, a capacitor 1003 and a switch 1005, and thru a second series arrangement of a switch 1007, a capacitor 1009 and a switch 1011. A non-inverting input of the amplifier OTA10 is connected to ground. An ouφut of the amplifier OTA10 is fed back to its inverting input thru a first series arrangement of a switch 1013, a capacitor 1015 connected in parallel to a capacitor 1016, and a switch 1017, and thru a second series arrangement of a switch 1019, a capacitor 1021 connected in parallel to a capacitor 1022, and a switch 1023. The output of the amplifier OTA10 furnishes the output chrominance signal U(nT).

The demodulated signal -2U(nT) v 3 is also applied to an inverting input of an amplifier OTA20 thru a first series arrangement of a switch 1031, a capacitor 1033 and a switch 1035, and thru a second series arrangement of a switch 1037, a capacitor 1039 and a switch 1041. A non-inverting input of the amplifier OTA20 is connected to ground. An output of the amplifier OTA20 is fed back to its inverting input thru a first series arrangement of a switch 1043, a capacitor 1045 connected in parallel to a capacitor 1046, and a switch 1047, and thru a second series arrangement of a switch 1049, a capacitor 1051 connected in parallel to a capacitor 1052, and a switch 1053. The ouφut of the amplifier OTA20 furnishes the ouφut chrominance signal V(nT).

The inverted demodulated signal U(nT) v 3 - V(nT) is applied to the inverting input of the amplifier OTA20 thru a first series arrangement of a switch 1061, a capacitor 1063 connected in parallel to a capacitor 1064, and a switch 1065, and thru a second series arrangement of a switch 1067, a capacitor 1069 connected in parallel to a capacitor 1070, and a switch 1071.

The capacitors 1003 and 1009 have a weight of 3, while all other capacitors have a weight of 1. In all such switch-capacitor-switch series arrangements shown in Fig. 10, the switches are connected such that they either discharge the capacitor(s) between them (as shown with reference to the capacitors 1009, 1021, 1039, 1051, 1069, 1070) or allow the signal to go thru the capacitor (as shown with reference to die capacitors 1003, 1015, 1033, 1045, 1063, 1064). Each time when two switch-capacitor-switch series arrangements are connected in parallel, the series arrangements are alternatingly controlled by the 3Fsc clock signal such that the capacitor is discharged in one of the series arrangements while the signal is allowed to go diru the capacitor in the other series arrangement. Thus, a double sampling arrangement is formed.

Fig. 11 shows an embodiment of a video signal receiver incorporating the chrominance demodulator embodiment of Fig. 6. The input video signal CVBS is applied to a clock signal generator 111 for generating a sampling clock at three times the color subcarrier frequency (3Fsc) which is reset at the start of each video line. The sampling clock signal is applied to a sampling switch S. The sampled signals are applied to a comb filter 113 for separating the luminance signal components Y and the chrominance signal components C modulated on me color subcarrier, from the sampled signals to obtain luminance signal samples Y and chrominance signal samples C. The chrominance signal samples C are applied to me demodulator embodiment 115 as shown in more detail in Fig. 6. The luminance signal samples Y from the comb filter 113 and the demodulated chrominance samples U, V from the demodulator 115 are processed in some known or yet unknown way by a processor 117 to obtain color signals R, G, B which are displayed by a display unit 119.

Hereinafter another practical realisation of a 3*Fsc sampling color demodulator will be described. Widi the simple use of the coefficients (0, 1 , -1) for multiplication in each of the U and V channels, the same switching capacitor can be used in each channel for the generation of the coefficients (1, -1). The simple addition of the AC coupling at the input of each channel, in the way to be described, can further improve the dynamic range.

Fig. 12 shows input multipliers for U and V channels. Corresponding clock phases are shown in Fig. 13b. The circuit diagram in Fig. 12a shows how simple it is to realise the U and V channel multipliers. The operation sequence of the multiplier for the U channel of Fig. 12a for the successive switch phases Φl (multiplication by 0), Φ2 (multiplication by 1), and Φ3 (multiplication by -1), is indicated in Fig. 12b. Since matching is no longer a consideration in the multipliers, a dynamic range of > 70 dB is possible for the U and V multipliers.

The input video signal CVBS is applied to a U signal branch 121-157 and to a V signal branch 221-257. In the U signal branch, the video signal CVBS is applied to a non- inverting input of an amplifier 125 thru a MOS transistor 121 (conductive at switch phases Φl and Φ2) and a MOS transistor 123 (conductive at switch phases Φl and Φ3). A capacitor Chold J is connected between ground and the junction of die transistors 121 and 123. An ouφut of the amplifier 125 is connected to its inverting input, and to an inverting input of an amplifier OTAl thru a MOS transistor 127 (conductive at switch phases Φl and Φ3), a capacitor Cmult-U having a relative capacitance of 2, and a MOS transistor 131 (conductive at switch phases Φ2 and Φ3). A MOS transistor 129 (conductive at switch phase Φ2) is connected between ground and the junction of the transistor 127 and the capacitor Cmult_U. A MOS transistor 133 (conductive at switch phase Φl) is connected between ground and the junction of the transistor 131 and the capacitor Cmult J.

The non-inverting input of the amplifier OTAl is connected to ground. An ouφut of me amplifier OTAl furnishes ouφut signals thru MOS transistors 135 (conductive at switch phase Φ) and 137 (conductive at switch phase Φ). The ouφut of the amplifier OTAl is coupled to its inverting input thru a MOS transistor 139 (conductive at switch phase Φ), a capacitor 143 having a relative capacitance of 1, and a MOS transistor 147 (conductive at switch phase Φ), and thru MOS transistor 149 (conductive at switch phase Φ), a capacitor 153 having a relative capacitance of 1 , and a MOS transistor 157 (conductive at switch phase Φ). A MOS transistor 141 (conductive at switch phase Φ) is connected between ground and die junction of the MOS transistor 139 and the capacitor 143. A MOS transistor 145 (conductive at switch phase Φ) is connected between ground and the junction of the MOS transistor 147 and the capacitor 143. A MOS transistor 151 (conductive at switch phase Φ) is connected between ground and die junction of the MOS transistor 149 and the capacitor 153. A MOS transistor 155 (conductive at switch phase Φ) is connected between ground and the junction of the MOS transistor 157 and the capacitor 153.

In the V signal branch, the video signal CVBS is applied to a non-inverting input of an amplifier 225 thru a MOS transistor 221 (conductive at switch phases Φ3 and Φl) and a MOS transistor 223 (conductive at switch phases Φ3 and Φ2). A capacitor Chold_V is connected between ground and d e junction of the transistors 221 and 223. An ouφut of the amplifier 225 is connected to its inverting input, and to an inverting input of an amplifier OTA2 thru a MOS transistor 227 (conductive at switch phases Φ3 and Φ2), a capacitor Cmult-V having a relative capacitance of 2, and a MOS transistor 231 (conductive at switch phases Φl and Φ2). A MOS transistor 229 (conductive at switch phase Φl) is connected between ground and the junction of the transistor 227 and the capacitor Cmult_V. A MOS transistor 233 (conductive at switch phase Φ3) is connected between ground and the junction of the transistor 231 and die capacitor Cmult_V. The non- inverting input of the amplifier OTA2 is connected to ground. An ouφut of the amplifier OTA2 furnishes ouφut signals thru MOS transistors 235 (conductive at switch phase Φ) and 237 (conductive at switch phase Φ). The ouφut of the amplifier OTA2 is coupled to its inverting input thru a MOS transistor 239 (conductive at switch phase Φ), a capacitor 243 having a relative capacitance of 1, and a MOS transistor 247 (conductive at switch phase Φ), and dim MOS transistor 249 (conductive at switch phase Φ), a capacitor 253 having a relative capacitance of 1 , and a MOS transistor 257 (conductive at switch phase Φ). A MOS transistor 241 (conductive at switch phase Φ) is connected between ground and d e junction of the MOS transistor 239 and the capacitor 243. A MOS transistor 245 (conductive at switch phase Φ) is connected between ground and the junction of the MOS transistor 247 and die capacitor 243. A MOS transistor 251 (conductive at switch phase Φ) is connected between ground and the junction of the MOS transistor 249 and die capacitor 253. A MOS transistor 255 (conductive at switch phase Φ) is connected between ground and the junction of the MOS transistor 257 and the capacitor 253.

The algorithm for operation of the input multiplying stage with AC coupling, can be explained by means of the following table. The input samples A, B, C, .. are those samples of the continuous-time input CVBS signal at intervals of l/3Fsc. The characters shown in bold at each interval of time for the demodulated U and V signals represent the effect of the U and V multipliers alone on the input samples in the absence of AC coupling.

Input Sample Sequence A I B I C I D I E

HPF Filtered (AC Coupling) I (B-A) I (C-B) I (D-C) I (E-D)

Demodulated U Channel Samples I (B-A) I (B-C) I O I (E-D) (* [1. -1, 0] ) Demodulated V Channel Samples I (A-B) I O I (D-C) I (D-E) (* [-l , 0, 1] ) nT (n+0.5 i))TT (n- + 1)T (n+ 1.5)T

The circuit proposed for die realisation of the input stage of the 3Fsc sampling color demodulator is shown in Fig. 13a, which is divided into two parts: Fig. 13a(l) shows the U channel of the demodulator, and Fig. 13a(2) shows me V channel. The essence of the demodulator for me U and V channels is d at which is depicted within the dashed lines - d ese are the 0° and 120° input multiplier stages for U and V, respectively. Two extra equally valued capacitors are required per channel for die AC coupling - matching to 60 dB of these equally valued capacitors would be required. Those parts of Fig. 13a which correspond to Fig. 12a bear the same references and will not be described again. The following elements are in addition to those of Fig. 12a.

In the U channel, shown by Fig. 13a(l), a series arrangement of two MOS transistors 121' (conductive at clock phase Φ3) and 123' (conductive at clock phase Φ2) is connected in parallel to d e series arrangement of the two MOS transistors 121 and 123. A capacitor Chold_U' is connected between ground and d e junction of the transistors 121 ' and 123'.

The ouφut of the amplifier 125 is coupled to ground by a compensation network including a series connection of a MOS transistor 159 (conductive at clock phase Φ3) and a capacitor 161 having a relative capacitance of 2. A MOS transistor 163 (conductive at clock phases Φl and Φ2) is connected between ground and the junction of the transistor 159 and d e capacitor 161.

The ouφut of the amplifier 125 is also coupled to the inverting input of the amplifier OTAl iru a MOS transistor 127' (conductive at switch phase Φl), a capacitor Cz_l having a relative capacitance of 2, and a MOS transistor 131' (conductive at switch phase Φ3). A MOS transistor 129' (conductive at switch phase Φ3) is connected between ground and the junction of the transistor 127' and the capacitor Cz_l . A MOS transistor 133' (conductive at switch phase Φl) is connected between ground and the junction of the transistor 131' and the capacitor Cz_l. The ouφut of the amplifier 125 is further coupled to the inverting input of the amplifier OTAl thru a MOS transistor 127" (conductive at switch phase Φ2), a capacitor Cz_l ' having a relative capacitance of 2, and a MOS transistor 131 " (conductive at switch phase Φ2). A MOS transistor 129" (conductive at switch phases Φl and Φ3) is connected between ground and the junction of die transistor 127" and the capacitor Cz_l '. A MOS transistor 133" (conductive at switch phases Φl and Φ3) is connected between ground and d e junction of d e transistor 131 " and d e capacitor Cz_l\

In die V channel, shown by Fig. 13a(2), a series arrangement of two MOS transistors 221 ' (conductive at clock phase Φ2) and 223' (conductive at clock phase Φl) is connected in parallel to the series arrangement of die two MOS transistors 221 and 223. A capacitor Chold_V" is connected between ground and the junction of the transistors 221 ' and 223'.

The ouφut of the amplifier 225 is coupled to ground by a compensation network including a series connection of a MOS transistor 259 (conductive at clock phase Φ2) and a capacitor 261 having a relative capacitance of 2. A MOS transistor 263

(conductive at clock phases Φ3 and Φl) is connected between ground and die junction of the transistor 259 and die capacitor 261.

The ouφut of the amplifier 225 is also coupled to die inverting input of the amplifier OTAl thru a MOS transistor 227' (conductive at switch phase Φ3), a capacitor Cz_2 having a relative capacitance of 2, and a MOS transistor 231' (conductive at switch phase Φ2). A MOS transistor 229' (conductive at switch phase Φl) is connected between ground and the junction of die transistor 227' and die capacitor Cz_2. A MOS transistor 233' (conductive at switch phase Φ3) is connected between ground and die junction of the transistor 231' and the capacitor Cz_2. The ouφut of the amplifier 225 is further coupled to me inverting input of the amplifier OTAl thru a MOS transistor 227" (conductive at switch phase Φl), a capacitor Cz_2' having a relative capacitance of 2, and a MOS transistor 231 " (conductive at switch phase Φl). A MOS transistor 229" (conductive at switch phases Φ2 and Φ3) is connected between ground and die junction of the transistor 227" and the capacitor Cz_2'. A MOS transistor 233" (conductive at switch phases Φ2 and Φ3) is connected between ground and the junction of die transistor 231" and the capacitor Cz_2'.

To give an indication of how the circuit works, the U channel will be examined for the generation of demodulated samples (B-A), (B-C), 0. Note that in die realisation, diere is a delay of 2T between the input and the ouφut of the demodulator stage of Fig. 13a.

Voltage level A is sampled on Chold_U' at time nT with clock phase Φ3. Voltage level B is sampled on Cmult_U on clock phase Φl at time (n+0.5)T. On clock phase Φ2, sample A is available at the ouφut of the sample-and-hold and is at that instant transferred to the demodulator ouφut via me inverting configuration formed by Czl'. Similarly, sample B on Cmult_U is transferred to die ouφut on Φ2 widi the non-inverting configuration formed by Cmult_U. The sample that appears at the ouφut at time (n+ l)T on clock phase is thus B-A.

Voltage level B is also sampled on Czl at time (n+0.5)T with clock phase Φl. Voltage level C is sampled on Chold_U on clock phase Φ2 at time (n+ l)T. Subsequently, on clock phase Φ3, sample B is transferred to die ouφut via die non-inverting configuration formed by capacitor Czl. Similarly, sample C is transferred to the ouφut on Φ3 via the inverting configuration formed by Cmult_U. Thus, on clock phase Φ3 at time (n+ 1.5)T, sample value (B-C) appears at the ouφut of die U channel. On clock phase Φl, no charge is transferred to die ouφut so as to generate a

O at the ouφut.

This represents one complete cycle of the regenerated subcarrier frequency for die U channel. The same explanation for the operation of the V channel can be given as for d e U channel for die generation of samples (A-B), 0, (D-C). The capacitor Ccomp is used in each channel to ensure equal loading conditions of d e multiplier on each clock phase. For instance, in die U channel, Cmult_U samples the charge held on Chold_U on clock phases Φl and Φ3. However, on clock phase Φl me capacitor Czl, for the creation of a zero at the ouφut, is connected to die ouφut of the sample-and-hold buffer. The capacitor Ccomp thus compensates on the Φ3 phase so as to create die same loading conditions for the multiplier as for the phase.

Fig. 13b illustrates clock phases for use in the embodiments of Figs. 12a and 13a. The first line shows a master clock MC whose period equals d e sampling period Ts. The second and third lines show a double sampling clock phase Φ and its inverse Φ. The fourth, fifth and sixth lines show d e mutually shifted clock phases Φl , Φ2 and Φ3.

The application shown does not require a delay to be made in OTA's 1 and 2. It is suitable, thus, for use with double-sampling FIR filters. However, if IIR filters are used, then the feedback capacitors of OTAl and OTA2 may be used for die realisation of first order recursive low-pass filters in d e U and V channels. These recursive low-pass filters would dien be die translation of the usual input bandpass filter as used in conventional color decoders. This input demodulator stage can also be used for a SECAM decoder, where OTAl and OTA2 would be used for die transformed cloche bandpass filter (an IIR filter with a specified non-linear group delay time), as shown in Fig. 13c which illustrates a transformed recursive bandpass filter or a SECAM cloche filter.

In Fig. 13c, die filter input signal is applied to an inverting input of an amplifier 331. A non-inverting input of me amplifier 331 is connected to ground. An ouφut of die amplifier 331 furnishes ouφut signals thru MOS transistors 335 (conductive at switch phase Φ) and 337 (conductive at switch phase Φ). The ouφut of the amplifier OTA2 is coupled to its inverting input thru a capacitance 333 having a relative capacitance of 1 , thru a MOS transistor 339 (conductive at switch phase Φ), a capacitor 343 having a relative capacitance of 1 , and a MOS transistor 347 (conductive at switch phase Φ), and thru MOS transistor 349 (conductive at switch phase Φ), a capacitor 353 having a relative capacitance of 1 , and a MOS transistor 357 (conductive at switch phase Φ). A MOS transistor 341 (conductive at switch phase Φ) is connected between ground and the junction of the MOS transistor 339 and die capacitor 343. A MOS transistor 345 (conductive at switch phase Φ) is connected between ground and die junction of die MOS transistor 347 and die capacitor 343. A MOS transistor 351 (conductive at switch phase Φ) is connected between ground and die junction of the MOS transistor 349 and the capacitor 353. A MOS transistor 355 (conductive at switch phase Φ) is connected between ground and d e junction of the MOS transistor 357 and d e capacitor 353.

A switched capacitor realisation for the matrixing stage is shown in Fig. 14.

This circuit appears after the U and V channel low-pass filters which band limit the chrominance signals to < 0.5 MHz (from > 5 MHz). Half die U channel signal must be added to the V channel signal. The U channel signal must, in turn, be multiplied by O.SN/3. The same value capacitors (one unit capacitor) are used for the matrix circuit. At the ouφut of the channel low-pass filters, the U signal is multiplied by 1/(1 + 1) , while die V channel is multiplied by (1 + 1)/(1 + 1), with bodi signals being added up at the same instant in time in an amplifier (OTA2) 1427. The gain factor in the U channel is realised by multiplying the ouφut of me U channel low-pass filter by die factor V3/( 1 + 1) with d e same delay as for die V channel matrixing. No matching is required of the V3 term with the V channel. An error in this term just gives a gain error in the U channel. Matching between equally valued unit capacitors in the matrix circuit to +_ 55 dB gives rise to high performance of the color decoder. When recursive filtering is chosen for use in the demodulator, OTAl 1407 and OTA2 1427 may be used for extra recursive filtering in each channel.

In Fig. 14, the signal 2\J /3 from the U channel demodulator is applied to an inverting input of die amplifier 1407 dirough a series connection of a MOS transistor 1401 switched by a clock signal Φ, a capacitor 1403 having relative capacitance V3, and a MOS transistor 1405 switched by a clock signal Φ. The clock signals Φ and Φ are non-overlapping clocks of frequency Fsc. A MOS transistor 1409 (switched by clock signal Φ), is connected between ground and the junction of d e transistor 1401 and the capacitor 1403. A MOS transistor 1411 (switched by clock signal Φ), is connected between ground and the junction of d e transistor 1405 and the capacitor 1403.

A non-inverting input of the amplifier 1407 is connected to ground. An ouφut of me amplifier 1407 furnishes the U ouφut signal thru a MOS transistor 1413 switched by a clock signal Φ. The ouφut of the amplifier 1407 is connected to its inverting input thru a " capacitor 1415, d m a capacitance 1417, both of relative capacitance 1 , and thru a MOS transistor 1419 switched by a clock signal Φ.

The signal 2U/v 3 from the U channel demodulator is also applied to an inverting input of d e amplifier 1427 dirough a series connection of a MOS transistor 1421 switched by a clock signal Φ, a capacitor 1423 having relative capacitance 1, and a MOS transistor 1425 switched by a clock signal Φ. A MOS transistor 1429 (switched by clock signal Φ), is connected between ground and the junction of the transistor 1421 and die capacitor 1423. A MOS transistor 1421 (switched by clock signal Φ), is connected between ground and d e junction of the transistor 1425 and die capacitor 1423. A non-inverting input of the amplifier 1427 is connected to ground. An ouφut of the amplifier 1427 furnishes me V ouφut signal di a MOS transistor 1433 switched by a clock signal Φ. The ouφut of the amplifier 1427 is connected to its inverting input thru a capacitor 1435, d m a capacitance 1437, both of relative capacitance 1 , and thru a MOS transistor 1439 switched by a clock signal Φ. The signal V - Oh/3 from the V channel demodulator is applied to the inverting input of the amplifier 1427 through a series connection of a MOS transistor 1441 switched by a clock signal Φ, a parallel connection of two capacitors 1443, 1444 each having relative capacitance 1, and a MOS transistor 1445 switched by a clock signal Φ. A MOS transistor 1449 (switched by clock signal Φ), is connected between ground and the junction of the transistor 1441 and the capacitors 1443, 1444. A MOS transistor 1441 (switched by clock signal Φ), is connected between ground and d e junction of the transistor 1445 and the capacitors 1443, 1444.

To summarize the present invention, in a sampled data color demodulator, where die sampling frequency is chosen to be 3 times die chrominance subcarrier frequency Fsc, demodulation of d e U and V chrominance signals wi 0° and 90° subcarrier locked oscillator signals would at first sight require that coefficients [0, 0.5V3, -0.5^3] be used for the U channel multiplier and coefficients [l.-'Λ,-^] for the V channel multiplier. Such a realisation requires that a bandpass filter be placed before die color decoder to remove the unwanted luminance so as to reduce the dynamic range of die multipliers to +_ 55 dB. In addition, very large capacitors are required in a switched capacitor realisation to ensure accuracy of matching (± 55 dB) between different valued capacitors.

The proposal here is to firstly demodulate the U and V chrominance signals wim Fsc locked oscillator signals at angles of 360°/(3*2ⁿ) with respect to the color subcarrier phase, preferably at angles of 0° and 120°. Simple coefficients of [0, 1,-1] for the U channel multiplier and [1, -1, 0] for the V channel multiplier with simple matrixing following the channel low-pass filters gives an inherently high dynamic range color decoder. With direct conversion (no input bandpass filter), a dynamic range of more than 70 dB can be realised in a standard CMOS process - only one capacitor is used for die multipliers - thus, no matching is required. The matching of equally valued matrix coefficients (unit capacitors) to only _+ 55 dB ensures high performance of the color decoder.

In a color decoder using recursive filtering, no extra hardware is required for the realisation of first order low-pass filters in the multiplier circuit and die matrix circuit. This makes the demodulator suitable, for instance, as the input stage of a direct conversion SECAM decoder. The matrixing may also be used for rotation of the I and Q axes for NTSC demodulation. The I channel linear phase low-pass filter may then have a wider bandwidth compared to the Q channel low-pass filter for a high quality NTSC color decoder.

It should be noted diat the above-mentioned embodiments illustrate rather than limit die invention, and that diose skilled in die art will be able to design many alternative embodiments without departing from the scope of the appended claims. It is, for example, also conceivable to demodulate die video signal at angles of 30° and 90°, i.e. with coefficients [0.5, 0.5, -1] and [1 , -0.5, -0.5] or indeed another combination whereby coefficients [0.5, 0.5, -1] are used instead of [0, 1, -1]. The point here is mat it is sometimes undesirable to multiply by 0 (do nothing) in say a noisy environment, whereby for the coefficients 1 and -1 noise is added to the ouφut and for die coefficient 0 no noise is added. This could introduce a 3T pattern to die ouφut. It has to be said that die [0.5, 0.5, -1] solution is somewhat worse as regards die matching of capacitors (where 1 must be realised as 2*0.5) but the exact same principles can still be used as described above, i.e. similar coefficients are used for U and V demodulation wi very little line to line variations. In this modification, the architecture of Fig. 1 remains the same, only the signals at each stage are different, as shown in the table below with reference to some examples.

With regard to the last two examples shown in the above table, it is to be noted d at demodulator Du is used to obtain the V ouφut signal. The factor 0.5^3 in the ouφut signal of adder A can easily be corrected for by inserting a further multiplier at the ouφut of the adder A, or by adapting die coefficients of the multipliers M2 and M3. Of course, it is possible to add 180° to the demodulation angles to obtain further implementations of the invention. In the claims, any reference signs (including the demodulator ouφut signal examples) placed between parentheses shall not be construed as limiting the claim. The invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer.

Claims

Claims:

1. A method of demodulating chrominance signals having a color subcarrier frequency, comprising the steps of: sampling input signals (CVBS) at three times the color subcarrier frequency to obtain sampled signals; demodulating (Du, Dv) the sampled signals at demodulation angles with respect to the color subcarrier phase which demodulation angles differ by 360°/(3*2ⁿ), with n being 0, 1 or 2, to obtain demodulator ouφut signals (2UJV3; -U/v/3 + V); and matrixing (Mx) die demodulator ouφut signals (2UΛ/3; -U/V3 + V) to obtain demodulated chrominance signals (U, V).

2. An arrangement for demodulating chrominance signals having a color subcarrier frequency, comprising: means for sampling input signals at three times the color subcarrier frequency to obtain sampled signals; means (Du, Dv) for demodulating die sampled signals at demodulation angles widi respect to the color subcarrier phase which demodulation angles differ by 360°/(3*2ⁿ), with n being 0, 1 or 2, to obtain demodulator ouφut signals (2UΛ 3; -U 3 + V); and means (Mx) for matrixing die demodulator ouφut signals (2UΛ/3; -\lh/3 + V) to obtain demodulated chrominance signals (U, V).

3. An arrangement as claimed in claim 2, wherein n equals 0, and the demodulation angles are 0° and 120°, or -30° and 90°.

4. An arrangement as claimed in claim 2, wherein n equals 1 , and me demodulation angles are 0° and 60°, or 30° and 90°.

5. An arrangement as claimed in claim 2, wherein said input signals are sampled by means of a sampling clock which is reset at the start of each video line.

6. An arrangement as claimed in claim 5, wherein demodulation coefficients are changed at the start of each video line.

7. An arrangement as claimed in claim 6, wherein inputs of said matrixing means

(Mx) are interchanged at die start of each video line, and wherein ouφuts of said matrixing means (Mx) are interchanged at d e start of each video line.

8. A receiver for video signals (CVBS) having luminance signal components (Y) and chrominance signal components (C) modulated on a color subcarrier having a color subcarrier frequency (Fsc), the receiver comprising: clock signal generating means (111) for generating a sampling clock at three times d e color subcarrier frequency which is reset at the start of each video line; means (S) for sampling said video signals (CVBS) at three times the color subcarrier frequency to obtain sampled signals; comb filtering means (113) for separating said luminance signal components (Y) and said chrominance signal components (C) modulated on said color subcarrier, from said sampled signals to obtain luminance signal samples (Y) and chrominance signal samples

(C); means (115: Du, Dv) for demodulating said chrominance signal samples at demodulation angles with respect to die color subcarrier phase which demodulation angles differ by 3607(3*2"), with n being 0, 1 or 2, to obtain demodulator ouφut samples (2U/V3; -UΛ 3 + V); means (115: Mx) for matrixing the demodulator ouφut samples (2U 3; - U v/3 + V) to obtain demodulated chrominance samples (U, V); means (117) for processing said luminance signal samples (Y) and said demodulated chrominance samples (U, V) to obtain color signals (R, G, B); and means (119) for displaying said color signals (R, G, B).