EP0733982A1 - Verfahren zur Beschleunigung der Ausführungsgeschwindigkeit Neuronalnetzwerken für korrelierte Signalverarbeitung - Google Patents

Verfahren zur Beschleunigung der Ausführungsgeschwindigkeit Neuronalnetzwerken für korrelierte Signalverarbeitung Download PDF

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EP0733982A1
EP0733982A1 EP96104445A EP96104445A EP0733982A1 EP 0733982 A1 EP0733982 A1 EP 0733982A1 EP 96104445 A EP96104445 A EP 96104445A EP 96104445 A EP96104445 A EP 96104445A EP 0733982 A1 EP0733982 A1 EP 0733982A1
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neuron
neurons
activation
quantized
quant
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French (fr)
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EP0733982B1 (de
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Dario Albesano
Roberto Gemello
Franco Mana
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Telecom Italia SpA
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CSELT Centro Studi e Laboratori Telecomunicazioni SpA
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/04Architecture, e.g. interconnection topology
    • G06N3/048Activation functions
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

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  • the present invention relates to automatic signal recognition systems and in particular it concerns a method of speeding up the execution of neural networks to process correlated signals.
  • a neural network is a parallel processing model reproducing, in extremely simplified form, the cerebral cortex organization.
  • a neural network comprises multiple processing units, known as neurons, strongly interconnected by means of links of various intensities, called synapses or interconnection weights.
  • Neurons in general are arranged along a multi-level structure, with an input level, one or more intermediate levels and an output level. Starting from the input units, which receive the signal to be processed, processing propagates to the subsequent levels of the network up to the output units, which provide the result.
  • a neural network is not programmed, but it is trained by means of a series of examples of the phenomenon to be modelled. Various embodiments of neural networks are described, for instance, in the book by D. Rumelhart “Parallel Distributed Processing", Vol. 1 Foundations, MIT Press, Cambridge, Mass., 1986.
  • Neural network technology can be applied to many sectors, such as function estimation, audio and video signal processing and classification, automatic controls, forecasting and optimisation, although it still presents some problems stemming from the lack of means that are powerful enough in terms of processing power and speed. It is well known that the execution of a neural network, when it is carried out by emulation on a sequential processor, is very burdensome, especially in cases requiring networks with many thousands of weights. If the need arises to process, in real time, signals continuously varying through time, such as for example voice, video, sonar or radar signals, use of this technology takes on additional difficulties.
  • the first is aimed at decreasing the network size by pruning weights and units, as described for example by R. Reed in "Pruning Algorithms - A Survey” in IEEE Transactions on Neural Networks, Vol. 4, no. 5, 1993. These methods, however, have limited effectiveness since the number of weights and units that can be pruned without incurring a degradation in performance is often very limited.
  • a second route is based on implementation of the neural network on a VLSI chip, by exploiting its intrinsic potential for parallelisation. This method is, potentially, very promising, but it is not very mature yet. It also entails the use of specialised hardware, which is often very expensive and not easy to integrate with commercial processors.
  • a third route is the use of specialised hardware of multi-processor type, by distributing the execution of the neural network among various processors.
  • this possible solution also requires non-standard hardware, which is costly and difficult to integrate with commercial platforms like personal computers or workstations.
  • the aforesaid drawbacks are obviated by the method of speeding up the execution of neural network for correlated signal processing, according to the present invention, which allows speeding up the execution of a wide class of neural networks to process sequential input signals evolving slowly through time, such as, for instance, voice, radar, sonar, video signals, and which requires no specialised, costly or hard to find hardware.
  • the object of the present invention is to provide a method of speeding up the execution of neural networks for correlated signal processing, as defined in the characterising part of claim 1.
  • the idea the method is based upon is the following: since the input signal is sequential and evolves slowly and continuously through time, it is not necessary to compute again all the activation values of all neurons for each input, but rather it is enough to propagate through the network the differences with respect to the previous input. That is, the operation does not consider the absolute neuron activation values at time t, but the differences with respect to activation values at time t-1. Therefore at any point of the network, if a neuron has at time t an activation that is sufficiently similar (preferably identical) to that of time t-1, then the neuron will not propagate any signal forward.
  • the execution of the neural network can be speeded up by propagating significant activation differences, and this allows saving up to two thirds of execution time in case of speech recognition.
  • This method requires a very small amount of auxiliary memory and it does not entail an appreciable degradation in performance, as it was experimentally verified.
  • Figure 1 shows a Multi-layer Perception neural network like the one described in the already mentioned book by D. Rumelhart "Parallel Distributed Processing".
  • the network input is a signal sampled in time and the network output are values corresponding to the desired processing, for instance input signal classification.
  • FIG. 2 shows a single neuron i with its forward connections, along which it propagates the activation differences, and with its memory structures M1 i and M2 i required for the speeding up method.
  • M1 i contains the activation value at time t, o i (t), as in conventional neural networks, and M2 i the value at the preceding time t-1, o i (t-1).
  • the other neurons in the network also have similar memory structures, for example M1 k and M2 k for neuron k.
  • Figure 3 depicts the quantization of the set of output values (co-domain) of the sigmoid transfer function of the neuron, with the purpose of quantizing the activation levels of the neurons, thus making it possible to recognise the condition of activation similarity at times t and t-1, required in order no signal is propagated.
  • the neurons do not propagate any signal when the quantized values at times t and t-1 are identical. The elementary operation to speed up execution of the network is thus accomplished.
  • the number of quantization values must be estimated empirically: the smaller it is, the more the method accelerates; however, it cannot be excessively small to avoid a degradation in performance. In the case of realistic Multi-layer Perceptron networks, with about 50,000 - 100,000 weights, this number can vary from about 25 to about 50.

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  • Physics & Mathematics (AREA)
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EP96104445A 1995-03-22 1996-03-20 Verfahren zur Beschleunigung der Ausführungsgeschwindigkeit von Neuronalnetzwerken für korrelierte Signalverarbeitung Expired - Lifetime EP0733982B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT95TO000216A IT1280816B1 (it) 1995-03-22 1995-03-22 Metodo per velocizzare l'esecuzione di reti neurali per il trattamento di segnali correlati.
ITTO950216 1995-03-22

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EP0733982A1 true EP0733982A1 (de) 1996-09-25
EP0733982B1 EP0733982B1 (de) 1999-06-02

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US (1) US5742739A (de)
EP (1) EP0733982B1 (de)
JP (1) JPH08272759A (de)
CA (1) CA2172199C (de)
DE (2) DE733982T1 (de)
IT (1) IT1280816B1 (de)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003073416A1 (en) * 2002-02-28 2003-09-04 Loquendo S.P.A. Method for accelerating the execution of speech recognition neural networks and the related speech recognition device
WO2004057573A1 (en) * 2002-12-23 2004-07-08 Loquendo S.P.A. Method of optimising the execution of a neural network in a speech recognition system through conditionally skipping a variable number of frames
CN105306779A (zh) * 2015-10-27 2016-02-03 西安电子科技大学 基于压缩感知和索引置乱的图像加密方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6516309B1 (en) * 1998-07-17 2003-02-04 Advanced Research & Technology Institute Method and apparatus for evolving a neural network
US9627532B2 (en) * 2014-06-18 2017-04-18 Nuance Communications, Inc. Methods and apparatus for training an artificial neural network for use in speech recognition
WO2017149722A1 (ja) * 2016-03-03 2017-09-08 三菱電機株式会社 演算装置および演算方法
US10949737B2 (en) * 2016-07-13 2021-03-16 Samsung Electronics Co., Ltd. Method for neural network and apparatus performing same method
DE102017206892A1 (de) * 2017-03-01 2018-09-06 Robert Bosch Gmbh Neuronalnetzsystem
US11030518B2 (en) * 2018-06-13 2021-06-08 United States Of America As Represented By The Secretary Of The Navy Asynchronous artificial neural network architecture
WO2020240687A1 (ja) * 2019-05-28 2020-12-03 株式会社ソシオネクスト 演算処理方法、演算処理装置及びプログラム

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JPH02207369A (ja) * 1989-02-08 1990-08-17 Hitachi Ltd ニューラルネットワーク計算機
US5313558A (en) * 1991-08-13 1994-05-17 Adams James L System for spatial and temporal pattern learning and recognition
DE4224621C2 (de) * 1992-07-25 1994-05-05 Boehringer Mannheim Gmbh Verfahren zur Analyse eines Bestandteils einer medizinischen Probe mittels eines automatischen Analysegerätes
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GHORBANI A A ET AL: "Training artificial neural networks using variable precision incremental communication", PROCEEDINGS OF 1994 IEEE INTERNATIONAL CONFERENCE ON NEURAL NETWORKS (ICNN'94), ORLANDO, FL, USA, 27 JUNE-29 JUNE 1994, ISBN 0-7803-1901-X, 1994, NEW YORK, NY, USA, IEEE, USA, pages 1409 - 1414 vol.3, XP002007127 *
KWAN H K ET AL: "MULTIPLIERLESS MULTILAYER FEEDFORWARD NEURAL NETWORKS", PROCEEDINGS OF THE MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, DETROIT, AUG. 16 - 18, 1993, vol. VOL. 2, no. SYMP. 36, 16 August 1993 (1993-08-16), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 1085 - 1088, XP000499764 *
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MYUNG WON KIM ET AL: "An asynchronous inter-processor communication based, input recycling parallel architecture for large scale neural network simulation", PROCEEDINGS OF WORLD CONGRESS ON NEURAL NETWORKS, SAN DIEGO, CA, USA, 5-9 JUNE 1994, ISBN 0-8058-1745-X, 1994, HILLSDALE, NJ, USA, LAWRENCE ERLBAUM ASSOCIATES, USA, pages II/576 - 83 vol.2, XP000574437 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003073416A1 (en) * 2002-02-28 2003-09-04 Loquendo S.P.A. Method for accelerating the execution of speech recognition neural networks and the related speech recognition device
US7827031B2 (en) 2002-02-28 2010-11-02 Loquendo S.P.A. Method for accelerating the execution of speech recognition neural networks and the related speech recognition device
WO2004057573A1 (en) * 2002-12-23 2004-07-08 Loquendo S.P.A. Method of optimising the execution of a neural network in a speech recognition system through conditionally skipping a variable number of frames
US7769580B2 (en) 2002-12-23 2010-08-03 Loquendo S.P.A. Method of optimising the execution of a neural network in a speech recognition system through conditionally skipping a variable number of frames
CN105306779A (zh) * 2015-10-27 2016-02-03 西安电子科技大学 基于压缩感知和索引置乱的图像加密方法

Also Published As

Publication number Publication date
DE69602662T2 (de) 1999-11-18
IT1280816B1 (it) 1998-02-11
ITTO950216A1 (it) 1996-09-22
JPH08272759A (ja) 1996-10-18
DE69602662D1 (de) 1999-07-08
CA2172199C (en) 1999-07-20
EP0733982B1 (de) 1999-06-02
ITTO950216A0 (it) 1995-03-22
DE733982T1 (de) 1997-03-13
CA2172199A1 (en) 1996-09-23
US5742739A (en) 1998-04-21

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