EP0731566A2 - Circuit arrangement for the conversion of a 1-bit digital signal into an analog signal - Google Patents

Abstract

The circuit converts a 1-bit digital signal with a predetermined sampling frequency into an analogue signal. The circuit includes a multiplier which receives a digital signal at one of its inputs and a reference signal at its other input. A delay device also receives the digital signal a shifts it by one period of the sampling frequency. A second multiplier receives the output of the delay device at one input and a reference signal at its other input. The outputs of the two multipliers are added to from an analogue signal.

Description

The invention relates to a circuit arrangement for converting a 1-bit digital signal with a given sampling frequency into an analog signal containing an analog multiplier, at one input of which the digital signal and at the other input of which a reference signal is applied.

Circuit arrangements of this type are used, for example, when returning the digital output signal of an analog-digital converter based on the sigma-delta principle in its analog input circuit. A circuit arrangement of the type mentioned at the beginning and its use in an analog-digital converter based on the sigma-delta principle is described in T.Hayashi et al, A Multistage Delta-Sigma Modulator without Double Integration Loop, 1986 IEEE International Solid-State Circuits Conference , P. 182 u. 183. This type of converter converts an analog input signal into a digital 1-bit output signal. The resulting large quantization noise is shifted from the baseband to higher frequencies by the so-called "noise shaping function" and then attenuated by means of digital filters. The corresponding digital-to-analog converter works essentially according to the same principles, but only in the reverse order. This means that digital noise shaping is carried out first, followed by the digital-to-analog conversion and then by an analog filtering.

The noise shaping function of the sigma-delta converters not only has the property of shifting the quantization noise to higher frequencies, but also tends to form of limit cycles for DC voltages at the input. Depending on the order of the noise shaping function, these are more or less pronounced and occur at low DC voltages in the range of half the sampling frequency. Such a case occurs, for example, when there is no signal at the input, but a DC voltage component arises from internal offset voltages of the analog components, such as amplifiers, filters and converters. The greater the offset voltage, the farther the limit cycles are from half the sampling frequency. Limit cycles do not disturb in the ideal case, since they lie outside the baseband and are eliminated by the subsequent filtering.

The 1-bit digital-analog conversion required for all sigma-delta converters corresponds to a multiplication of a digital 1-bit pulse density signal with an analog reference signal. Since the converters are usually operated in combination with other digital circuit units, for example a signal processor, and can usually even be integrated on one and the same chip, their clock pulses very easily get into the reference signal as interferers. The frequency of the interference signal often corresponds to half the sampling frequency.

The multiplication of the digital 1-bit pulse density signal by a limit cycle caused by an input offset with a frequency of, for example, half the sampling frequency minus a low-frequency signal of, for example, 2 KHz and a reference signal superimposed by an interference signal with half the sampling frequency results in a convolution the limit cycle in the baseband, whereby the low-frequency signal caused by the offset becomes audible.

The level of such limit cycles depends on the size of the interference coupling to the reference signal and can appear as a discrete line in the noise spectrum. Next In such limit cycles, the noise spectrum is also folded into the baseband by half the sampling frequency and thus additionally reduces the signal-to-noise ratio.

The object of the invention is to provide a circuit arrangement of the type mentioned in the introduction in which these disadvantages do not occur.

The object is achieved in a generic circuit arrangement by the characterizing features of claim 1. Refinements and developments of the inventive concept are the subject of dependent claims.

The advantage of the invention is that extensive interference suppression is achieved with little additional circuitry complexity.

Figur 1

eine prinzipielle Ausführungsform einer erfindungsgemäßen Schaltungsanordnung in einem Blockdiagramm,

Figur 2

das Schaltbild einer Ausführungsform der erfindungsgemäßen Schaltungsanordnung in Switched-Capacitor-Technik,

Figur 3

die Anwendung einer erfindungsgemäßen Schaltungsanordnung bei einem Digital-Analog-Umsetzer nach dem Sigma-Delta-Prinzip und

Figur 4

eine Anwendung der erfindungsgemäßen Schaltungsanordnung bei einem Analog-Digital-Umsetzer nach dem Sigma-Delta-Prinzip.

The invention is explained in more detail below with reference to the exemplary embodiments shown in the figures of the drawing.
It shows:

Figure 1

1 shows a basic embodiment of a circuit arrangement according to the invention in a block diagram,

Figure 2

2 shows the circuit diagram of an embodiment of the circuit arrangement according to the invention using switched capacitor technology,

Figure 3

the use of a circuit arrangement according to the invention in a digital-to-analog converter based on the sigma-delta principle and

Figure 4

an application of the circuit arrangement according to the invention in an analog-digital converter based on the sigma-delta principle.

In the exemplary embodiment according to FIG. 1, a digital 1-bit pulse density signal is sent to an input of a multiplier 3 and to the input of a Delay device 4 created. The delay device 4 delays the digital signal D by one sampling clock period. The output of the delay device 4 is fed to an input of a further multiplier 5. The other inputs of the two multipliers 3 and 5 are each assigned a reference signal R. The multipliers 3 and 5 are each followed by a damping device 6 or 7, each of which effects a damping by half. The damping of both damping devices 6 and 7 can, however, also assume any values depending on the respective application. However, the same damping values are preferably selected. By changing the damping values, different amplitude and frequency responses can be achieved. The outputs of the two damping devices 6 and 7 each lead to an input of an analog adding device 8, at the output of which an analog signal A corresponding to the digital signal D is available.

In the exemplary embodiment according to FIG. 2, the two multiplier devices, the damping devices and the adding device are provided by a switched capacitor network. This switched capacitor network has a capacitor 9, one connection of which can be connected to the reference signal R via a switch 10 and to a reference potential M via a switch 11. The other connection of the capacitor 9 can be connected via a changeover switch 12 either to one connection of a switch 13 or to one connection of a switch 14. The other connections of the switches 13 and 14 are each connected to the reference potential M. A connection of a capacitor 15 can be connected to the reference signal R via a switch 16 and to the reference potential M via a switch 17. The other connection of the capacitor 15 can be connected via a changeover switch 18 either to one connection of the switch 13 or to one connection of the switch 14. The one Connection of the switch 13 and one connection of the switch 14 can be connected to an input of an integrator via a switch 19 or 20. The integrator in turn consists of a symmetrical operational amplifier 21 which is fed back between the inverting input and the non-inverted output and between the non-inverting input and the inverted output by a respective capacitor 22 or 23. Analog signal A is available at the symmetrical outputs of an operational amplifier 21. The multiplier 3 and the damping device 6 according to FIG. 1 are realized in this configuration.

To implement the multiplier 5 and the damping device 7, a capacitor 24 is additionally provided, one connection of which is connected to one connection of the capacitor 9 and the other connection of which is connected via a changeover switch 25 either to one connection of the switch 13 or to one connection of the switch 14 can be activated. Furthermore, the one connection of a capacitor 26 is connected to the one connection of the capacitor 15. The other connection of the capacitor 26 can be connected via a changeover switch 27 either to one connection of the switch 13 or to one connection of the switch 14.

des Digitalsignals D oder die beiden Schaltphasen Ind und $\overline{\text{Ind}}$

des verzögerten Digitalsignals D Verwendung. Dabei werden die Schalter 10, 13, 14 und 17 durch die Schaltphase 1 und die Schalter 11, 16, 19 und 20 durch die Schaltphase 2 durchgeschaltet. Die Umschalter 12 und 18 werden durch die Schaltphase In bzw. In auf den einen Anschluß des Schalters 14 bzw. auf den einen Anschluß des Schalters 13 aufgeschaltet. Die Umschalter 25 und 27 werden dementsprechend durch die Schaltphase Ind bzw. $\overline{\text{Ind}}$

auf den einen Anschluß des Schalters 14 bzw. den einen Anschluß des Schalters 13 aufgeschaltet.To control the individual switches, there are two switching phases 1 and 2 of a clock signal or the two switching phases In and $\overline{\text{In}}$

of the digital signal D or the two switching phases Ind and $\overline{\text{Ind}}$

of the delayed digital signal D use. The switches 10, 13, 14 and 17 are switched through the switching phase 1 and the switches 11, 16, 19 and 20 through the switching phase 2. The changeover switches 12 and 18 are connected through the switching phase In or In to one connection of the switch 14 or to one connection of the switch 13. The switch 25 and 27 are accordingly by the switching phase Ind or $\overline{\text{Ind}}$

on the a connection of the switch 14 or the one connection of the switch 13.

The addition of the two different multiplied signals takes place, on the one hand, at one connection of the switch 13 and, on the other hand, at the one connection of the switch 14. Because of the symmetry, the capacitors 22 and 23 are mutually identical and the capacitors 9 and 15 are mutually identical. The capacitors 24 and 26 are also identical to one another. The ratio of the damping devices 6 and 7 is adjusted by means of the capacitances of the capacitors 24, 26 in relation to the capacitors 9 and 15. If one chooses a damping value of 0.5 in each case, the capacitance of the capacitors 9 and 15 is halved compared to the use of only a single multiplier 3. Since in this case the capacitance of the capacitors 24 and 26 is also equal to the capacitance of the capacitors 9 and 15 , again half, the total capacitor area required remains the same. The damping factor 0.5 thus halves the capacitor values, which means that when the circuit arrangement according to the invention is implemented in integrated circuit technology, the increase in area of the integrated circuit is limited only to the two additional changeover switches 25 and 27 and the delay device 4.

The use of a circuit arrangement 28 according to the invention in a digital-to-analog conversion device based on the sigma-delta principle is shown in FIG. A digital signal d to be converted is fed to a digital filter 29, by means of which the noise shaping of the signal D is carried out. The digital signal D supplied to the circuit arrangement 28 is available at the output of the digital filter 29. Compared to the embodiment of the circuit arrangement according to the invention according to FIG. 1, the embodiment according to FIG. 3 has been modified such that both multiplication devices each have one by Have digital signal D controlled switches 30 and 31, each in a switching state through a positive reference signal + R and in the other switching state through a negative reference signal -R to the respective input of the adder 8. The switch 31 is controlled by the digital signal D delayed by the delay device 4. In this embodiment, the damping of the damping devices 6 and 7 is replaced by a corresponding choice of the two reference voltages + R and -R, in which case the two damping factors are always the same. The analog signal A available at the output of the adder 8 is fed to an analog filter 32 for band limitation. An analog signal a, which results from the digital signal d, is thus available at its output.

According to FIG. 4, another preferred application of the circuit arrangement 33 according to the invention is in an analog-digital conversion device based on the sigma-delta principle. The circuit arrangement 33 is constructed, for example, in accordance with the embodiment shown in FIG. An analog signal a 'to be converted is, for example, applied to a second order sigma-delta converter at the input of an adder 34, the other input of which is supplied with the analog signal A provided at the output of the circuit arrangement 33. The output of the adder 34 is followed by a first integrator 35, the output of which is in turn routed to an input of an adder 36. Analog signal A is also applied to the other input of adder 36. The adder 36 is followed by a second integrator 37, which is followed by a comparator 38. The comparator 38 outputs the digital signal D, which is supplied to the circuit arrangement 33 according to the invention on the one hand and is available for further processing, for example by means of a digital filter.

The functioning of the circuit arrangement according to the invention is based on the fact that a notch filter function is generated, the greatest attenuation of which lies at half the sampling frequency. Limit cycles around half the sampling frequency and interference components at half the sampling frequency in the reference signal are thereby filtered out and a folding of the limit cycles and the noise into the baseband is avoided.

Claims (6)

Circuit arrangement for converting a 1-bit digital signal with a given sampling frequency into an analog signal (A) containing a multiplier (3), at one input of which the digital signal (D) and at the other input of which a reference signal (R) are applied,
marked by
a delay device (4) to which the digital signal (D) is applied and which delays the digital signal (D) by one period of the sampling frequency,
by a further multiplier (5), one input of which is connected to the output of the delay device (4) and the other of which the reference signal (R) is applied, and
by an adder (8), the inputs of which are connected to the outputs of the two multipliers (3, 5) and the analog signal (A) is available at the output. Circuit arrangement according to claim 1,
characterized in that between the outputs of the two multiplier devices (3, 5) and the inputs of the adder device (8) there is in each case a damping device (6, 7) each with a specific damping factor. Circuit arrangement according to claim 1 or 2,
characterized in that
at least one of the multiplication devices (3, 5) has a switch (30, 31) controlled by the digital signal (D), which switches through the reference signal (+ R) in one switching state and the inverted reference signal (-R) to the output in the other switching state. Circuit arrangement according to claim 1,
characterized,
that the two multipliers (3, 5) and the adding device (8) are formed,
by a first capacitor (9), one connection of which can be connected to the reference signal (R) via a first switch (10) and to a reference potential (M) via a second switch (11) and the other connection of which can be connected via a third switch (12 ) can be connected to a connection of a fourth switch (13) or to a connection of a fifth switch (14), the other connections of the fourth and fifth switches (13, 14) being connected to the reference potential (M),
by a second capacitor (15), one connection of which can be connected to the reference signal (R) via a sixth switch (16) and to the reference potential (M) via a seventh switch (17) and the other connection of which can be connected via an eighth switch (18 ) can be connected to one connection of the fourth switch (13) or to one connection of the fifth switch (14),
by a third capacitor (24), one terminal of which is connected to one terminal of the first capacitor (9) and the other terminal of which is connected via a neutral switch (25) to one terminal of the fourth switch (13) or to one terminal of the fifth switch (14) can be activated,
by a fourth capacitor (26), one terminal of which is connected to one terminal of the second capacitor (15) and the other terminal of which is connected via a tenth switch (27) to one terminal of the fourth switch (13) or to one terminal of the fifth switch (14) can be switched on and
by an integrator (21, 22, 23) with symmetrical inputs, one input via an eleventh switch (19) to one terminal of the fourth switch (13) and the other input via a twelfth switch (20) to one terminal of the fifth switch (14) can be switched on and which outputs the analog signal (A) at the output,
that first, fourth, fifth and seventh switches (10, 13, 14, 17) by a first switching phase (1) of a clock signal and second, sixth, eleventh and twelfth switches (11, 16, 19, 20) by one to the first switching phase (1) inverted second switching phase (2) of the clock signal and
that the third switch (12) by the digital signal (D), the eighth switch (18) by the inverted digital signal (D), the ninth switch (25) by the delayed digital signal (D) by means of the delay device (4) and the tenth Switch (27) is switched by the inverted, delayed digital signal (D). Use of the circuit arrangement according to one of claims 1 to 4 in a digital-to-analog conversion device based on the sigma-delta principle. Use of the circuit arrangement according to one of claims 1 to 4 in an analog-digital conversion device based on the sigma-delta principle.

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