EP0722215B1 - PLL-FM demodulator - Google Patents

PLL-FM demodulator Download PDF

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Publication number
EP0722215B1
EP0722215B1 EP96410007A EP96410007A EP0722215B1 EP 0722215 B1 EP0722215 B1 EP 0722215B1 EP 96410007 A EP96410007 A EP 96410007A EP 96410007 A EP96410007 A EP 96410007A EP 0722215 B1 EP0722215 B1 EP 0722215B1
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EP
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Prior art keywords
output
input
filter
frequency
inputs
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EP96410007A
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German (de)
French (fr)
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EP0722215A1 (en
Inventor
Pascal Mellot
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STMicroelectronics SA
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STMicroelectronics SA
SGS Thomson Microelectronics SA
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
    • H03D3/02—Demodulation of angle-, frequency- or phase- modulated oscillations by detecting phase difference between two signals obtained from input signal
    • H03D3/24—Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits
    • H03D3/241—Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits the oscillator being part of a phase locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
    • H03D3/02—Demodulation of angle-, frequency- or phase- modulated oscillations by detecting phase difference between two signals obtained from input signal
    • H03D3/24—Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits
    • H03D3/241—Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits the oscillator being part of a phase locked loop
    • H03D3/245—Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits the oscillator being part of a phase locked loop using at least twophase detectors in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/113—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using frequency discriminator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0001—Circuit elements of demodulators
    • H03D2200/0025—Gain control circuits
    • H03D2200/0027—Gain control circuits including arrangements for assuring the same gain in two paths
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop

Definitions

  • the present invention relates to tuning a loop to phase lock (PLL) and demodulation of a carrier modulated sound and applies in particular to demodulation frequency modulated (FM) sound in a television receiver.
  • PLL phase lock
  • FM demodulation frequency modulated
  • a plurality of carrier frequencies typically range from 4.5 to 6.5 MHz.
  • FIG. 1 shows in block form the diagram of a classic FM demodulation PLL.
  • This PLL includes a mixer 100, sometimes called a multiplier, a low-pass filter 110, a buffer amplifier 120, an amplifier 130 and a voltage controlled frequency oscillator (VCO) 140.
  • VCO voltage controlled frequency oscillator
  • the mixer 100 receives and mixes signals f IN and f VCO which are respectively present on its inputs 150 and 160, the input 160 being the output of the VCO 140.
  • the output 170 of the mixer which comprises the demodulated audio signal f D , is transmitted by the filter 110 and the buffer 120.
  • the output 180 of the buffer is connected to the inputs of the amplifier 130 and of the VCO 140.
  • the frequency modulated input signal f IN is a composite signal which may correspond to any one of a plurality of carrier frequencies which span a wide frequency range.
  • a problem associated with the system illustrated in FIG. 1 is that, since the carrier frequencies extend over a wide frequency range, the VCO 140 oscillator will have to have a high gain, typically several MHz / Volt, to allow the PLL to be locked. on any one of the plurality of carrier frequencies.
  • carrier frequencies which span a large dynamic range require that the VCO have a high gain and a frequency range greater than the carrier frequency range.
  • the use of a high gain VCO results in the demodulated audio signal f D having a low amplitude, typically in the range of a few tens of millivolts, from which there results a demodulated audio signal f D which has a bad signal to noise ratio.
  • the demodulated audio signal f D must then be amplified by the amplifier 130 to obtain a larger useful signal.
  • unwanted noise will also be amplified by the same amount as the desired audio signal. Consequently, the respective signal-to-noise ratios at the input and at the output of the amplifier 130 will be substantially identical.
  • a high gain VCO will exhibit poor linearity characteristics which will affect the quality of the demodulated audio signal f D.
  • the required audio signal which is superimposed on the carrier signal, should be demodulated by a low gain VCO so that the demodulated audio signal f D has an amplitude of a few hundred millivolts, which ensures good ratio. signal to noise.
  • the gain characteristic as a function of the frequency of the system in Figure 1 is substantially flat.
  • An object of the present invention is to provide a Demodulation PLL which presents a signal to noise ratio improved.
  • Another object of the invention is to provide a PLL of demodulation which exhibits improved characteristics of demodulation linearity.
  • a demodulation PLL which has a high gain loop for its locking and a low gain loop for demodulation. More particularly, the present invention provides a loop locked in demodulation phase comprising a mixer connected to a controlled oscillator, having an input low gain control, a high gain control input, and an output connected to an input of the mixer; a filter low pass having its input connected to the output of the mixer; a level comparator which provides an active output when the signal levels on the input and output of the first filter have sufficiently converged; a frequency comparator which provides active output when the signal frequencies on the first and second mixer inputs have enough converged; a controlled switch having a first position in which the input and output of the first filter are respectively connected to high gain and gain inputs low oscillator controlled and a second position in which the input and output of the first filter are respectively connected to the low gain and high gain inputs of the oscillator; and control means coupled to said level comparator and to said frequency comparator, for selecting the first position of the
  • the controlled oscillator comprises a controlled oscillator in current and first and second controlled current sources in voltage which respectively have control inputs which correspond to the high gain and low gain inputs of the oscillator controlled, to control the frequency of the oscillator current controlled.
  • the second voltage-controlled current source has characteristics very linear.
  • the loop includes a second low pass filter and a buffer that are connected downstream of the mixer and upstream of the first filter, controlled switch and level comparator.
  • the first filter is a resistance filter and capacitor.
  • a means is provided for reducing the value of the resistance of the first filter when the switch is in its first position.
  • the present invention applies to a satellite, radio system, or television system including a cable television system.
  • an FM demodulation PLL includes a mixer 100, a filter low pass 205, level comparator 210, control block 215, a frequency comparator 220, a double switch 225 and a voltage controlled oscillator 230 with double input.
  • This FM demodulation PLL also includes a 110 low pass filter and a buffer 120, as shown in Figure 1, which have not have been illustrated in this figure 2 for the sake of clarity; the low pass filter 110 will filter the "sum" components at high frequency of the mixer while the buffer 120 will adapt the impedance of the downstream low-pass filter 205 without affecting the impedance of the upstream low pass filter 110.
  • the composite FM input signal f IN is supplied to the first common inputs 235 of the mixer 100 and of the frequency comparator 220, the second common inputs 240 of which are connected to the output of the VCO 230.
  • the outputs 240, 245 of the VCO 230 and of the mixer 100 are continuously polarized according to the required carrier frequency.
  • the output 245 of the mixer 100 is connected to the input of the low-pass filter 205, to a first input of the switch 225 and to a first input of the level comparator 210.
  • the output 250 of the low-pass filter 205 is connected to the seconds common inputs of switch 225 and level comparator 210.
  • the respective outputs 255, 260 of frequency and level comparators 220 and 210 are connected to control block 215, the output 265 of which controls switch 225 in response to its inputs (255 , 260).
  • the first and second outputs H and L of switch 225 are respectively connected to the first and second inputs of VCO 230 and correspond respectively to a high gain input H and to a low gain input L.
  • the diagram in Figure 2 has two modes of operation. In the first mode, the PLL makes an agreement and " locks “only on the required carrier frequency, while that, in the second mode, the PLL demodulates the audio signal from the carrier frequency locked.
  • the switch 255 In the first operating mode, the switch 255 is in its first position (shown in solid lines) in which its first and second inputs 245, 250 are respectively connected to the gain inputs H and L of the VCO 230.
  • the low frequency gain of this system during this tuning mode is determined by the sum of the gains of the high and low gain inputs H and L of the VCO. This sum of the gains is due to the fact that the low-pass filter of 205 has a minimum effect on its input signal when this input signal has a frequency f S which is less than that of the cut-off frequency (in this example 0.7 Hz) of the low pass filter 205.
  • the overall gain at low frequency of this system is 3.07 MHz / V (3.0 + 0.07 MHz / V).
  • the high frequency gain of this system during this tuning mode is determined by the high gain input H of the VCO.
  • This gain of the input H is due to the fact that the low-pass filter 205 substantially attenuates its input signal when this input signal has a frequency f s greater than that of the cut-off frequency (0.7 Hz) of the low-pass filter 205. Consequently, when f s > 0.7 Hz, the overall gain at high frequency of this system is 3.0 MHz / V.
  • this first mode it is substantially the continuous component of the output 245 of the mixer 100 (and of course the output 240 of the VCO 230) which has a high gain so as to ensure rapid and suitable locking of the carrier, a possible demodulated audio signal having very little influence on the gain of the system.
  • the arrangement of Figure 2 includes a switch control block 215 that responds to outputs 255, 260 of the frequency and level comparators respectively 220, 210 so that when the frequencies of the signals on the inputs 235, 240 of the mixer 100 are substantially equal, the frequency comparator provides an active signal, for example a logic signal 1, and, when the signal levels on the inputs 245, 250 of switch 225 are substantially equal, the level comparator provides an active signal.
  • the block of control 215 responds to the active signals of the two comparators of to switch switch 225 from first to second position (shown in dotted lines).
  • the control block 215 will return switch 225 to its first preferred position only when the output signal of the frequency comparator 220 goes for example from a logic state 1 to a logic state 0, regardless of the state of the comparator output signal level 210, i.e. the control block acts as that lock.
  • the switch goes from its first to its second position, the PLL goes from its first to its second mode functional.
  • the switch 255 In the second functional mode, the switch 255 is in its second position in which its first and second inputs 245, 250 are respectively connected to the low and high gain inputs L and H of the VCO 230.
  • the gain at low frequency of these systems, during its second mode, demodulation is determined by the sum of the gains of the high and low gain inputs H and L of the VCO. Consequently, when 0 ⁇ f s ⁇ 0.7Hz, the overall gain at low frequency of the system is 3.07 MHz / V. However, this high frequency gain of the system during its demodulation mode is determined by the low gain input L of the VCO.
  • This input gain L is due to the fact that the low-pass filter 205 substantially attenuates its input signal when this input signal has a frequency f s greater than that of the cut-off frequency (0.7 Hz) of the filter low pass 205. Consequently, when f s > 0.7 Hz, the overall high frequency gain of the system is 0.07 MHz / V or 70 kHz / V.
  • this second mode it is substantially the alternative audio component of the output 245 of the mixer 100 (and of course the output 240 of the VCO 230) which has a low gain so as to provide a large demodulated audio signal f D which has a good signal-to-noise ratio, the continuous signal having very little influence on the gain of the system; however, this continuous signal is always present thus ensuring the locking of the system on the required carrier.
  • the gain as a function of the frequency of the VCO goes from 3.07 MHz / V for 0.7 Hz to 70 kHz / V, for 30 Hz; 30 Hz corresponding to the frequency for which the gain of the VCO equals 70 kHz / V plus 3dB.
  • the audio signal is demodulated by a low gain VCO from which there results a demodulated audio signal f D of a few hundred millivolts. Consequently, the signal-to-noise ratio of this demodulated audio signal f D will be better than for the demodulated audio signal f D associated with FIG. 1.
  • FIG. 3 is a block diagram of an embodiment of the VCO of FIG. 2.
  • the VCO 230 comprises an oscillator 300 and two controlled current sources 305, 310.
  • the oscillator 300 is preferably a conventional oscillator current controlled such as an oscillator with coupled transmitters. It is supplied by a positive voltage source VCC and provides a frequency signal f VCO on output 240 and a current I on output 315. The frequency of signal f VCO is proportional to current I.
  • the terminals of the current sources 305, 310, on the high voltage side, are connected to the output 315 and their terminals on the low voltage side are connected to another voltage source VEE which is less positive than the voltage source VCC.
  • the current source 305 corresponds to a high gain current source which is controlled by a "tuning voltage" VT on the input H and lets current IT pass
  • the current source 310 corresponds to a source of low gain current which is controlled during demodulation by a "demodulation voltage” VD on the input L, and allows a current ID to pass.
  • Current I is the sum of IT and ID currents.
  • the current sources 305 and 310 are controlled by the voltages VT, VD on their respective inputs H and L so that the current I is demodulated around a central value which itself modulates the output frequency signal f VCO around with a central frequency F 0 .
  • FIG 4A shows a circuit diagram of an embodiment of the high gain current source 305 of Figure 3 and Figure 4B shows the transfer characteristic of the high gain current source of Figure 4A.
  • This high gain current source 305 includes four NPN transistors Q5-Q8 and four resistors R3-R6. The gain of this current source is substantially proportional to the ratio of resistors R3 / R6; resistors R3 and R4 have the same value.
  • the collector of transistor Q5 is connected to the voltage VCC, its emitter is connected to the collector of transistor Q8 via a resistor R3 and its base is biased by a reference voltage V REF1 .
  • the collector of transistor Q6 corresponds to output 315, its emitter is connected to the collector of transistor Q8 by a resistor R4 and its base corresponds to input H.
  • the emitter of transistor Q8 is connected to voltage VEE via of resistance R6.
  • the collector of transistor Q7 is connected to the voltage VCC via the resistor R5.
  • the basic terminals of transistors Q7 and Q8 are connected to the collector of transistor Q7.
  • the emitter of transistor Q7 is preferably connected to the voltage VEE via a diode D1 which provides temperature compensation in association with an oscillator with coupled emitters.
  • the diode D1 can consist of an NPN transistor connected as a diode.
  • This current source 305 is in fact a differential amplifier associated with a current mirror.
  • the central frequency F 0 of the PLL is proportional to: IT [(V BE / 2R6) + (VT-V REF1 ) / 2R3].
  • the transfer characteristic is linear in practice only around the point [V REF , I x / 2], that is to say between the points A and B.
  • FIG. 5A represents a circuit diagram of a mode for making the low gain current source 310 of the Figure 3 and Figure 5B shows the transfer characteristic from this current source.
  • This gain current source low 310 includes two PNP transistors Q9-Q10; three transistors NPN Q11-Q13; four resistors R7-R10; an amplifier operational 600 and a buffer amplifier 610.
  • the emitters of the transistors Q9 and Q10 are connected to the voltage VCC via respective resistors R7 and R8.
  • the collectors of the transistors Q9 and Q10 are respectively connected to the collectors of the transistors Q11 and Q12, the emitters of which are connected to the voltage VEE.
  • the collectors of transistors Q9 and Q11 are connected to output 315 and receive the current ID ( Figure 3).
  • the base terminals of the transistors Q11 and Q12 are connected to the base and to the collector of the transistor Q13.
  • the collector of transistor Q13 is connected to voltage VCC via resistor R9.
  • the transistor Q13 acts as the input transistor of a current mirror having the transistors Q11 and Q12 as the output transistors.
  • the output L of the switch 225 is connected to the input of the buffer 610 which is preferably a unity gain amplifier.
  • the output of the buffer 610 which is at the voltage VD, is connected to the positive input 620 of the amplifier 600 by the resistor R10.
  • Input 620 is a voltage designated by V + .
  • the collectors of the transistors Q10 and Q12 are connected to the positive input 620 of the amplifier.
  • the negative input of amplifier 600 is connected to a reference voltage source V REF2 .
  • the base terminals of transistors Q9 and Q10 are connected to output 620 of amplifier 600.
  • V + V REF2 .
  • the modulation frequency F M is proportional to ID and therefore to - (V REF2 -VD) / R10.
  • FIG. 6 is a block diagram of a embodiment of the control block 215 of FIG. 2.
  • This control block 215 includes a rocker of the RS 800 type and a logic block 805.
  • the respective outputs 255, 260, 265 of the frequency comparator 220, level comparator 210 and flip-flop 800 are sent to logic block 805.
  • the flip-flop 800 and the logic block 805 are arranged for example so that output 265 of flip-flop 800 has a logic state 0 unless inputs 255, 260 all have two of the logic states 1, i.e. unless the frequencies signals on inputs 235, 240 of mixer 200 are substantially equal and that the signal levels on the inputs 245, 250 of switch 225 are substantially equal.
  • the output 265 of flip-flop 800 passes from a logic state 0 to a logical state 1 and remains in logical state 1 until the output 255 of the frequency comparator 220 changes state for indicate that the PLL frequency is not "locked" which that either the state of the signal coming from the level comparator 210, that is to say the flip-flop 800 and the logic block 805 act like a lock.
  • Figure 7A is a block diagram of a embodiment of the level comparator 210 of the figure 2. This diagram represents an amplifier 900, a mixer 905 and a comparator 910.
  • Amplifier 900 which provides differential outputs 915, 920, receives inputs from input 245 and output 250 from filter 205.
  • Outputs 915, 920 are connected to mixer 905 which performs an elevation function squared, ie a function X 2 , on the inverted and non-inverted voltage difference ⁇ V of the signals on these outputs 915, 920.
  • the output 925 of the mixer is connected to the positive input of comparator 910 whose negative input is polarized by a reference voltage V REF3 and whose output 260 provides a logic signal.
  • FIG. 7B represents the relationship between the signals which are present on the outputs 925 and 260 of FIG. 7A.
  • the upper signal represents the product of the inverted and non-inverted voltage difference ⁇ V of the signals present on outputs 915 and 920 of amplifier 900.
  • the lower signal represents the signal on output 260 of comparator 910.
  • the output 260 of the comparator has a logic state 1 and, when the voltage on the output 925 of the mixer 905 is greater than V REF3 , the output 260 of the comparator has a logic state 0 .
  • Figure 8A is a block diagram of a embodiment of the frequency comparator 220 of the figure 2. This diagram represents a mixer 1000, a low-pass filter 1010, a comparator 1020 and a digital integrator 1030.
  • the mixer 1000 mixes the respective signals f IN , f VCO on the inputs 235, 240 and provides an output 1040 which is connected to the filter 1010.
  • the filter 1010 has for example a cut-off frequency of 400 kHz.
  • the output 1050 of the filter 1010 which is a voltage V IN , is connected to the positive input of the comparator 1020 whose negative input is biased by a reference voltage V REF4 .
  • the comparator 1020 provides a logic signal V OUT on its output 1060 which is connected to the input of the integrator 1030.
  • the output of the integrator 1030 constitutes the output 255.
  • FIG. 8B represents the voltage V IN , that is to say the output voltage of the filter 1010, when the frequency difference f 1 between f IN and f VCO is greater than approximately 1 MHz.
  • the filter 1010 eliminates by filtering the frequency components higher than approximately 400 kHz and this leaves a signal whose peak value is never higher than the reference V REF4 . Consequently, the output of comparator 1020 and of the integrator is always at logic level 0.
  • FIG. 8C represents the voltage V IN when the frequency difference f 2 between f IN and f VCO is less than approximately 1 MHz.
  • the filter 1010 filters out the frequency components greater than about 400 kHz.
  • V IN has a peak value which is sometimes greater than the reference V REF4 since the filter 1010 has less influence on its input signal. This results in an output signal V IN of greater amplitude. Consequently, the output of comparator 1020 will have a logic state 1 each time V IN is greater than V REF4 .
  • the integrator acts as a filter with respect to the comparator output and can be arranged so that it will have a logic state 0 until the frequencies f IN , f VCO have sufficiently converged, for example when the frequencies f IN , f VCO are within 100 kHz of each other.
  • FIG. 8D represents the voltage V IN when the frequency difference f 2 between f IN and f VCO is substantially zero.
  • the voltage V IN is substantially a direct voltage which is always greater than V REF4 and, consequently, the respective outputs 1060 and 255 of the comparator and of the integrator have logic states 1.
  • Figures 9A and 9B show two embodiments an accelerator which can be used in conjunction with the present invention to reduce the time constant of the low pass filter 205 of FIG. 2 when the filter 205 is a RC low-pass filter, as shown in dotted lines.
  • the basic function of the accelerator is to reduce, during the "ok" mode, that is to say during the first mode functional, the resistance of the low-pass filter 205 so that the capacitor of this filter can charge more quickly, that is, the capacitor can follow the filter input voltage.
  • the accelerator is a switched resistance 1100 placed in parallel on the resistance of the filter. The switched resistance is controlled by the output 265 from the control block so that when the system is in its first functional mode, the switched resistor is placed in parallel with the resistance of the filter and, when the system is in its second functional mode, i.e. the mode of "demodulation", the switched resistance has no effect on the filter resistance.
  • the switched resistance can be realized in the form a suitably connected transconductance amplifier and ordered 1110.
  • the present invention can be adapted to be advantageously used for demodulation, preferably but not necessarily FM demodulation, sound in systems radio or television and / or video systems and / or satellite receiver systems.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Superheterodyne Receivers (AREA)
  • Television Receiver Circuits (AREA)

Description

La présente invention concerne l'accord d'une boucle à verrouillage de phase (PLL) et la démodulation d'une porteuse sonore modulée et s'applique en particulier à la démodulation d'un son modulé en fréquence (FM) dans un récepteur de télévision. Dans un tel système, une pluralité de fréquences porteuses s'étendent typiquement sur la plage de 4,5 à 6,5 MHz.The present invention relates to tuning a loop to phase lock (PLL) and demodulation of a carrier modulated sound and applies in particular to demodulation frequency modulated (FM) sound in a television receiver. In such a system, a plurality of carrier frequencies typically range from 4.5 to 6.5 MHz.

La figure 1 représente sous forme de blocs le schéma d'un PLL classique de démodulation FM. Ce PLL comprend un mélangeur 100, quelquefois appelé multiplieur, un filtre passe-bas 110, un amplificateur tampon 120, un amplificateur 130 et un oscillateur à fréquence commandée par la tension (VCO) 140.Figure 1 shows in block form the diagram of a classic FM demodulation PLL. This PLL includes a mixer 100, sometimes called a multiplier, a low-pass filter 110, a buffer amplifier 120, an amplifier 130 and a voltage controlled frequency oscillator (VCO) 140.

Le mélangeur 100 reçoit et mélange des signaux fIN et fVCO qui sont respectivement présents sur ses entrées 150 et 160, l'entrée 160 étant la sortie du VCO 140. La sortie 170 du mélangeur, qui comporte le signal audio démodulé fD, est transmise par le filtre 110 et le tampon 120. La sortie 180 du tampon est connectée aux entrées de l'amplificateur 130 et du VCO 140.The mixer 100 receives and mixes signals f IN and f VCO which are respectively present on its inputs 150 and 160, the input 160 being the output of the VCO 140. The output 170 of the mixer, which comprises the demodulated audio signal f D , is transmitted by the filter 110 and the buffer 120. The output 180 of the buffer is connected to the inputs of the amplifier 130 and of the VCO 140.

Le signal d'entrée modulé en fréquence fIN est un signal composite qui peut correspondre à l'une quelconque d'une pluralité de fréquences porteuses qui s'étalent sur une large plage de fréquence. Un problème associé au système illustré en figure 1 est que, comme les fréquences porteuses s'étendent sur une large plage de fréquence, l'oscillateur VCO 140 devra avoir un gain élevé, typiquement plusieurs MHz/Volt, pour permettre au PLL de se verrouiller sur l'une quelconque de la pluralité de fréquences porteuses. Ainsi, des fréquences porteuses qui s'étalent sur une grande plage dynamique nécessitent que le VCO ait un gain élevé et une plage de fréquence supérieure à la plage de fréquence des porteuses. Toutefois, l'utilisation d'un VCO à gain élevé entraíne que le signal audio démodulé fD a une faible amplitude, typiquement dans la plage de quelques dizaines de millivolts, d'où il résulte un signal audio démodulé fD qui a un mauvais rapport signal sur bruit. Le signal audio démodulé fD doit alors être amplifié par l'amplificateur 130 pour obtenir un plus grand signal utile. Toutefois, le bruit indésiré sera également amplifié de la même quantité que le signal audio désiré. En conséquence, les rapports signal sur bruit respectifs à l'entrée et à la sortie de l'amplificateur 130 seront sensiblement identiques. En outre, un VCO à gain élevé présentera de mauvaises caractéristiques de linéarité qui affecteront la qualité du signal audio démodulé fD.The frequency modulated input signal f IN is a composite signal which may correspond to any one of a plurality of carrier frequencies which span a wide frequency range. A problem associated with the system illustrated in FIG. 1 is that, since the carrier frequencies extend over a wide frequency range, the VCO 140 oscillator will have to have a high gain, typically several MHz / Volt, to allow the PLL to be locked. on any one of the plurality of carrier frequencies. Thus, carrier frequencies which span a large dynamic range require that the VCO have a high gain and a frequency range greater than the carrier frequency range. However, the use of a high gain VCO results in the demodulated audio signal f D having a low amplitude, typically in the range of a few tens of millivolts, from which there results a demodulated audio signal f D which has a bad signal to noise ratio. The demodulated audio signal f D must then be amplified by the amplifier 130 to obtain a larger useful signal. However, unwanted noise will also be amplified by the same amount as the desired audio signal. Consequently, the respective signal-to-noise ratios at the input and at the output of the amplifier 130 will be substantially identical. In addition, a high gain VCO will exhibit poor linearity characteristics which will affect the quality of the demodulated audio signal f D.

De façon idéale, le signal audio requis, qui est superposé au signal de porteuse, devrait être démodulé par un VCO à faible gain de sorte que le signal audio démodulé fD ait une amplitude de quelques centaines de millivolts, ce qui assure un bon rapport signal sur bruit.Ideally, the required audio signal, which is superimposed on the carrier signal, should be demodulated by a low gain VCO so that the demodulated audio signal f D has an amplitude of a few hundred millivolts, which ensures good ratio. signal to noise.

En conséquence, avec le système de la figure 1, on arrive à un conflit entre les exigences de gain du VCO dans les modes de verrouillage et de démodulation.Consequently, with the system of FIG. 1, one arrives at a conflict between the VCO gain requirements in the lock and demodulation modes.

Il faut noter que la caractéristique de gain en fonction de la fréquence du système de la figure 1 est sensiblement plate.It should be noted that the gain characteristic as a function of the frequency of the system in Figure 1 is substantially flat.

Un objet de la présente invention est de prévoir un PLL de démodulation qui présente un rapport signal sur bruit amélioré. An object of the present invention is to provide a Demodulation PLL which presents a signal to noise ratio improved.

Un autre objet de l'invention est de prévoir un PLL de démodulation qui présente des caractéristiques améliorées de linéarité de démodulation.Another object of the invention is to provide a PLL of demodulation which exhibits improved characteristics of demodulation linearity.

Ces objets sont atteints selon la présente invention par un PLL de démodulation qui présente une boucle à fort gain pour son verrouillage et une boucle à faible gain pour la démodulation. Plus particulièrement, la présente invention prévoit une boucle verrouillée en phase de démodulation comprenant un mélangeur connecté à un oscillateur commandé, ayant une entrée de commande de gain faible, une entrée de commande de gain fort, et une sortie connectée à une entrée du mélangeur ; un filtre passe-bas ayant son entrée connectée à la sortie du mélangeur ; un comparateur de niveau qui fournit une sortie active quand les niveaux de signal sur l'entrée et la sortie du premier filtre ont suffisamment convergé ; un comparateur de fréquence qui fournit une sortie active quand les fréquences du signal sur les première et seconde entrées du mélangeur ont suffisamment convergé ; un commutateur commandé ayant une première position dans laquelle l'entrée et la sortie du premier filtre sont respectivement connectées à des entrées de gain élevé et de gain faible de l'oscillateur commandé et une seconde position dans laquelle l'entrée et la sortie du premier filtre sont respectivement connectées aux entrées de gain faible et de gain fort de l'oscillateur ; et des moyens de commande couplés audit comparateur de niveau et audit comparateur de fréquence, pour sélectionner la première position du commutateur quand les fréquences du signal sur les première et seconde entrées du mélangeur n'ont pas suffisamment convergé et la seconde position du commutateur quand les fréquences du signal sur les entrées du mélangeur et les niveaux de signal sur l'entrée et la sortie du filtre ont suffisamment convergé.These objects are achieved according to the present invention by a demodulation PLL which has a high gain loop for its locking and a low gain loop for demodulation. More particularly, the present invention provides a loop locked in demodulation phase comprising a mixer connected to a controlled oscillator, having an input low gain control, a high gain control input, and an output connected to an input of the mixer; a filter low pass having its input connected to the output of the mixer; a level comparator which provides an active output when the signal levels on the input and output of the first filter have sufficiently converged; a frequency comparator which provides active output when the signal frequencies on the first and second mixer inputs have enough converged; a controlled switch having a first position in which the input and output of the first filter are respectively connected to high gain and gain inputs low oscillator controlled and a second position in which the input and output of the first filter are respectively connected to the low gain and high gain inputs of the oscillator; and control means coupled to said level comparator and to said frequency comparator, for selecting the first position of the switch when the signal frequencies on the first and second mixer inputs have not sufficiently converged and the second position of the switch when the signal frequencies on the inputs of the mixer and the signal levels on the filter input and output have sufficiently converged.

Selon un mode de réalisation de la présente invention, l'oscillateur commandé comprend un oscillateur commandé en courant et des première et seconde sources de courant commandées en tension qui ont respectivement des entrées de commande qui correspondent aux entrées de gain fort et de gain faible de l'oscillateur commandé, pour commander la fréquence de l'oscillateur commandé en courant. According to an embodiment of the present invention, the controlled oscillator comprises a controlled oscillator in current and first and second controlled current sources in voltage which respectively have control inputs which correspond to the high gain and low gain inputs of the oscillator controlled, to control the frequency of the oscillator current controlled.

Selon un mode de réalisation de la présente invention, la seconde source de courant commandée en tension a des caractéristiques très linéaires.According to an embodiment of the present invention, the second voltage-controlled current source has characteristics very linear.

Selon un mode de réalisation de la présente invention, la boucle comprend un deuxième filtre passe-bas et un tampon qui sont connectés en aval du mélangeur et en amont du premier filtre, du commutateur commandé et du comparateur de niveau.According to an embodiment of the present invention, the loop includes a second low pass filter and a buffer that are connected downstream of the mixer and upstream of the first filter, controlled switch and level comparator.

Selon un mode de réalisation de la présente invention, le premier filtre est un filtre à résistance et condensateur.According to an embodiment of the present invention, the first filter is a resistance filter and capacitor.

Selon un mode de réalisation de la présente invention, il est prévu un moyen pour réduire la valeur de la résistance du premier filtre quand le commutateur est dans sa première position.According to an embodiment of the present invention, a means is provided for reducing the value of the resistance of the first filter when the switch is in its first position.

La présente invention s'applique à un récepteur de satellite, un système radio, ou un système de télévision incluant un système de télévision par câble.The present invention applies to a satellite, radio system, or television system including a cable television system.

Ces objets, caractéristiques et avantages ainsi que d'autres de la présente invention seront décrits en détail dans la description suivante de modes de réalisation particuliers faite, à titre non-limitatif, en relation avec les figures jointes parmi lesquelles :

  • la figure 1 est un schéma sous forme de blocs d'une boucle à verrouillage de phase (PLL) classique de démodulation d'un signal modulé en fréquence (FM) ;
  • la figure 2 est un schéma sous forme de blocs d'un mode de réalisation d'un PLL de démodulation FM selon l'invention ;
  • la figure 3 représente sous forme de blocs un mode de réalisation du VCO de la figure 2 ;
  • la figure 4A est un schéma de circuit d'une source de courant à gain élevé de la figure 3 ;
  • la figure 4B représente la caractéristique de transfert du circuit de la figure 4A ;
  • la figure 5A est un schéma de circuit d'une source de courant à faible gain de la figure 3 ;
  • la figure 5B représente la caractéristique de transfert du circuit de la figure 5A ;
  • la figure 6 est un schéma sous forme de blocs d'un mode de réalisation d'un bloc de commande de la figure 2 ;
  • la figure 7A est un schéma sous forme de blocs d'un mode de réalisation d'un comparateur de niveau de la figure 2 ;
  • la figure 7B représente la relation entre des signaux du schéma de la figure 7A ;
  • la figure 8A représente un schéma sous forme de blocs d'un mode de réalisation d'un comparateur de fréquence de la figure 2 ;
  • la figure 8B représente la tension de sortie du filtre de la figure 8A en fonction de la différence de fréquence entre la fréquence d'entrée et la fréquence du VCO quand la différence de fréquence est supérieure à environ 1 MHz ;
  • la figure 8C représente la tension de sortie du filtre de la figure 8A en fonction de la différence de fréquence entre la fréquence d'entrée et la fréquence du VCO quand la différence de fréquence est inférieure à environ 1 MHz ;
  • la figure 8D représente la tension de sortie du filtre de la figure 8A en fonction de la différence de fréquence entré la fréquence d'entrée et la fréquence du VCO quand la différence de fréquence est sensiblement nulle ;
  • la figure 9A représente un mode de réalisation d'un accélérateur pour réduire la constante de temps du filtre passe-bas de la figure 2A ; et
  • la figure 9B représente une variante du circuit de la figure 9A.
    • These objects, characteristics and advantages as well as others of the present invention will be described in detail in the following description of particular embodiments made, without implied limitation, in relation to the attached figures among which:
  • Figure 1 is a block diagram of a conventional phase locked loop (PLL) for demodulating a frequency modulated signal (FM);
  • FIG. 2 is a block diagram of an embodiment of an FM demodulation PLL according to the invention;
  • FIG. 3 represents in the form of blocks an embodiment of the VCO of FIG. 2;
  • Figure 4A is a circuit diagram of a high gain current source of Figure 3;
  • Figure 4B shows the transfer characteristic of the circuit of Figure 4A;
  • Figure 5A is a circuit diagram of a low gain current source of Figure 3;
  • Figure 5B shows the transfer characteristic of the circuit of Figure 5A;
  • Figure 6 is a block diagram of an embodiment of a control block of Figure 2;
  • Figure 7A is a block diagram of an embodiment of a level comparator of Figure 2;
  • Figure 7B shows the relationship between signals in the diagram of Figure 7A;
  • FIG. 8A represents a block diagram of an embodiment of a frequency comparator of FIG. 2;
  • FIG. 8B represents the output voltage of the filter of FIG. 8A as a function of the frequency difference between the input frequency and the frequency of the VCO when the frequency difference is greater than approximately 1 MHz;
  • FIG. 8C represents the output voltage of the filter of FIG. 8A as a function of the frequency difference between the input frequency and the frequency of the VCO when the frequency difference is less than approximately 1 MHz;
  • FIG. 8D represents the output voltage of the filter of FIG. 8A as a function of the frequency difference entered the input frequency and the frequency of the VCO when the frequency difference is substantially zero;
  • FIG. 9A shows an embodiment of an accelerator for reducing the time constant of the low pass filter of FIG. 2A; and
  • FIG. 9B represents a variant of the circuit of FIG. 9A.

    • En figure 2, un PLL de démodulation FM selon la présente invention comprend un mélangeur 100, un filtre passe-bas 205, un comparateur de niveau 210, un bloc de commande 215, un comparateur de fréquence 220, un commutateur double 225 et un oscillateur commandé en tension 230 à double entrée. Ce PLL de démodulation FM comprend aussi un filtre passe-bas 110 et un tampon 120, tels que représentés en figure 1, qui n'ont pas été illustrés dans cette figure 2 par souci de clarté ; le filtre passe-bas 110 filtrera les composantes "somme" à haute fréquence du mélangeur tandis que le tampon 120 adaptera l'impédance du filtre passe-bas aval 205 sans affecter l'impédance du filtre passe-bas amont 110.In Figure 2, an FM demodulation PLL according to the present invention includes a mixer 100, a filter low pass 205, level comparator 210, control block 215, a frequency comparator 220, a double switch 225 and a voltage controlled oscillator 230 with double input. This FM demodulation PLL also includes a 110 low pass filter and a buffer 120, as shown in Figure 1, which have not have been illustrated in this figure 2 for the sake of clarity; the low pass filter 110 will filter the "sum" components at high frequency of the mixer while the buffer 120 will adapt the impedance of the downstream low-pass filter 205 without affecting the impedance of the upstream low pass filter 110.

    Le signal d'entrée FM composite fIN est fourni aux premières entrées communes 235 du mélangeur 100 et du comparateur de fréquence 220 dont les secondes entrées communes 240 sont connectées à la sortie du VCO 230. Les sorties 240, 245 du VCO 230 et du mélangeur 100 sont polarisées en continu selon la fréquence porteuse requise. La sortie 245 du mélangeur 100 est connectée à l'entrée du filtre passe-bas 205, à une première entrée du commutateur 225 et à une première entrée du comparateur de niveau 210. La sortie 250 du filtre passe-bas 205 est connectée aux secondes entrées communes du commutateur 225 et du comparateur de niveau 210. Les sorties respectives 255, 260 des comparateurs de fréquence et de niveau 220 et 210 sont connectées au bloc de commande 215 dont la sortie 265 commande le commutateur 225 en réponse à ses entrées (255, 260). Les première et seconde sorties H et L du commutateur 225 sont respectivement connectées aux première et seconde entrées du VCO 230 et correspondent respectivement à une entrée à gain élevé H et à une entrée à gain faible L.The composite FM input signal f IN is supplied to the first common inputs 235 of the mixer 100 and of the frequency comparator 220, the second common inputs 240 of which are connected to the output of the VCO 230. The outputs 240, 245 of the VCO 230 and of the mixer 100 are continuously polarized according to the required carrier frequency. The output 245 of the mixer 100 is connected to the input of the low-pass filter 205, to a first input of the switch 225 and to a first input of the level comparator 210. The output 250 of the low-pass filter 205 is connected to the seconds common inputs of switch 225 and level comparator 210. The respective outputs 255, 260 of frequency and level comparators 220 and 210 are connected to control block 215, the output 265 of which controls switch 225 in response to its inputs (255 , 260). The first and second outputs H and L of switch 225 are respectively connected to the first and second inputs of VCO 230 and correspond respectively to a high gain input H and to a low gain input L.

    Le schéma de la figure 2 a deux modes de fonctionnement. Dans le premier mode, le PLL réalise un accord et "se verrouille" seulement sur la fréquence porteuse requise, tandis que, dans le second mode, le PLL démodule le signal audio de la fréquence porteuse verrouillée.The diagram in Figure 2 has two modes of operation. In the first mode, the PLL makes an agreement and " locks "only on the required carrier frequency, while that, in the second mode, the PLL demodulates the audio signal from the carrier frequency locked.

    Pour rendre l'analyse ci-après plus compréhensible, on supposera un cas où l'on a les valeurs numériques suivantes :

  • fréquence d'entrée (fIN) : de 4,5 à 6,5 MHz ;
  • entrée à gain élevé (H) du VCO 3 MHz/V (polarisation continue de 5 V pour 6 MHz) ;
  • entrée à faible gain (L) du VCO - 70 kHz/V ;
  • fréquence de coupure du filtre passe-bas 205 : 0,7 Hz.
    • Ces valeurs sont données uniquement à titre d'exemple et ne doivent pas être interprétées limitativement quant à la portée de la présente invention.To make the following analysis more understandable, we will assume a case where we have the following numerical values:
  • input frequency (f IN ): 4.5 to 6.5 MHz;
  • 3 MHz / V VCO high gain input (H) (5 V continuous polarization for 6 MHz);
  • VCO low gain input (L) - 70 kHz / V;
  • cut-off frequency of the low-pass filter 205: 0.7 Hz.
    • These values are given by way of example only and should not be interpreted restrictively as to the scope of the present invention.

    Dans le premier mode de fonctionnement, le commutateur 255 est dans sa première position (représentée en traits pleins) dans laquelle ses première et seconde entrées 245, 250 sont respectivement connectées aux entrées de gain H et L du VCO 230. Le gain à basse fréquence de ce système pendant ce mode d'accord est déterminé par la somme des gains des entrées de gain fort et faible H et L du VCO. Cette somme des gains est due au fait que le filtre passe-bas de 205 a un effet minimum sur son signal d'entrée quand ce signal d'entrée a une fréquence fS qui est inférieure à celle de la fréquence de coupure (dans cet exemple 0,7 Hz) du filtre passe-bas 205. En conséquence, quand 0 ≤ fs ≤ 0,7 Hz, le gain d'ensemble à fréquence basse de ce système est 3,07 MHz/V (3,0+0,07 MHz/V). Toutefois, le gain à haute fréquence de ce système pendant ce mode d'accord est déterminé par l'entrée de gain fort H du VCO. Ce gain de l'entrée H est dû au fait que le filtre passe-bas 205 atténue sensiblement son signal d'entrée quand ce signal d'entrée a une fréquence fs supérieure à celle de la fréquence de coupure (0,7 Hz) du filtre passe-bas 205. En conséquence, quand fs > 0,7 Hz, le gain d'ensemble à fréquence haute de ce système est 3,0 MHz/V. Ainsi, dans ce premier mode, c'est sensiblement la composante continue de la sortie 245 du mélangeur 100 (et bien sûr la sortie 240 du VCO 230) qui a un gain élevé de façon à assurer un verrouillage rapide et convenable de la porteuse, un éventuel signal audio démodulé ayant très peu d'influence sur le gain du système.In the first operating mode, the switch 255 is in its first position (shown in solid lines) in which its first and second inputs 245, 250 are respectively connected to the gain inputs H and L of the VCO 230. The low frequency gain of this system during this tuning mode is determined by the sum of the gains of the high and low gain inputs H and L of the VCO. This sum of the gains is due to the fact that the low-pass filter of 205 has a minimum effect on its input signal when this input signal has a frequency f S which is less than that of the cut-off frequency (in this example 0.7 Hz) of the low pass filter 205. Consequently, when 0 ≤ f s ≤ 0.7 Hz, the overall gain at low frequency of this system is 3.07 MHz / V (3.0 + 0.07 MHz / V). However, the high frequency gain of this system during this tuning mode is determined by the high gain input H of the VCO. This gain of the input H is due to the fact that the low-pass filter 205 substantially attenuates its input signal when this input signal has a frequency f s greater than that of the cut-off frequency (0.7 Hz) of the low-pass filter 205. Consequently, when f s > 0.7 Hz, the overall gain at high frequency of this system is 3.0 MHz / V. Thus, in this first mode, it is substantially the continuous component of the output 245 of the mixer 100 (and of course the output 240 of the VCO 230) which has a high gain so as to ensure rapid and suitable locking of the carrier, a possible demodulated audio signal having very little influence on the gain of the system.

    Le PLL tendra à se verrouiller sur la fréquence porteuse requise sensiblement de la même façon que le PLL de la figure 1. Toutefois, l'agencement de la figure 2 comprend un bloc de commande de commutateur 215 qui répond aux sorties respectives 255, 260 des comparateurs de fréquence et de niveau 220, 210 de sorte que, quand les fréquences des signaux sur les entrées 235, 240 du mélangeur 100 sont sensiblement égales, le comparateur de fréquence fournit un signal actif, par exemple un signal logique 1, et, quand les niveaux des signaux sur les entrées 245, 250 du commutateur 225 sont sensiblement égaux, le comparateur de niveau fournit un signal actif. Le bloc de commande 215 répond aux signaux actifs des deux comparateurs de façon à commuter le commutateur 225 de sa première à sa seconde position (représentée en pointillés). Le bloc de commande 215 ramènera le commutateur 225 à sa première position de préférence seulement quand le signal de sortie du comparateur de fréquence 220 passe par exemple d'un état logique 1 à un état logique 0, quel que soit l'état du signal de sortie du comparateur de niveau 210, c'est-à-dire que le bloc de commande agit en tant que verrou. Quand le commutateur passe de sa première à sa seconde position, le PLL passe de son premier à son second mode fonctionnel.The PLL will tend to lock onto the frequency carrier required in much the same way as the PLL of the Figure 1. However, the arrangement of Figure 2 includes a switch control block 215 that responds to outputs 255, 260 of the frequency and level comparators respectively 220, 210 so that when the frequencies of the signals on the inputs 235, 240 of the mixer 100 are substantially equal, the frequency comparator provides an active signal, for example a logic signal 1, and, when the signal levels on the inputs 245, 250 of switch 225 are substantially equal, the level comparator provides an active signal. The block of control 215 responds to the active signals of the two comparators of to switch switch 225 from first to second position (shown in dotted lines). The control block 215 will return switch 225 to its first preferred position only when the output signal of the frequency comparator 220 goes for example from a logic state 1 to a logic state 0, regardless of the state of the comparator output signal level 210, i.e. the control block acts as that lock. When the switch goes from its first to its second position, the PLL goes from its first to its second mode functional.

    Dans le second mode fonctionnel, le commutateur 255 est dans sa seconde position dans laquelle ses première et seconde entrées 245, 250 sont respectivement connectées aux entrées de gain faible et fort L et H du VCO 230. Comme dans le cas du premier mode, le gain à fréquence faible de ces systèmes, pendant son second mode, de démodulation, est déterminé par la somme des gains des entrées de gain fort et faible H et L du VCO. En conséquence, quand 0 ≤ fs ≤ 0,7Hz, le gain d'ensemble à fréquence basse du système est 3,07 MHz/V. Toutefois, ce gain haute fréquence du système pendant son mode de démodulation est déterminé par l'entrée de gain faible L du VCO. Ce gain d'entrée L est dû au fait que le filtre passe-bas 205 atténue sensiblement son signal d'entrée quand ce signal d'entrée a une fréquence fs supérieure à celle de fréquence de coupure (0,7 Hz) du filtre passe-bas 205. En conséquence, quand fs>0,7 Hz, le gain d'ensemble à haute fréquence du système est 0,07 MHz/V ou 70 kHz/V. Pendant ce second mode, c'est sensiblement la composante audio alternative de la sortie 245 du mélangeur 100 (et bien sûr la sortie 240 du VCO 230) qui a un gain faible de façon à fournir un signal audio démodulé important fD qui a un bon rapport signal-sur-bruit, le signal continu ayant très peu d'influence sur le gain du système ; toutefois, ce signal continu est toujours présent assurant ainsi le verrouillage du système sur la porteuse requise.In the second functional mode, the switch 255 is in its second position in which its first and second inputs 245, 250 are respectively connected to the low and high gain inputs L and H of the VCO 230. As in the case of the first mode, the gain at low frequency of these systems, during its second mode, demodulation, is determined by the sum of the gains of the high and low gain inputs H and L of the VCO. Consequently, when 0 ≤ f s ≤ 0.7Hz, the overall gain at low frequency of the system is 3.07 MHz / V. However, this high frequency gain of the system during its demodulation mode is determined by the low gain input L of the VCO. This input gain L is due to the fact that the low-pass filter 205 substantially attenuates its input signal when this input signal has a frequency f s greater than that of the cut-off frequency (0.7 Hz) of the filter low pass 205. Consequently, when f s > 0.7 Hz, the overall high frequency gain of the system is 0.07 MHz / V or 70 kHz / V. During this second mode, it is substantially the alternative audio component of the output 245 of the mixer 100 (and of course the output 240 of the VCO 230) which has a low gain so as to provide a large demodulated audio signal f D which has a good signal-to-noise ratio, the continuous signal having very little influence on the gain of the system; however, this continuous signal is always present thus ensuring the locking of the system on the required carrier.

    En conséquence, le gain en fonction de la fréquence du VCO passe de 3,07 MHz/V pour 0,7 Hz à 70 kHz/V, pour 30 Hz ; 30 Hz correspondant à la fréquence pour laquelle le gain du VCO égale 70 kHz/V plus 3dB. Dans ce cas, le signal audio est démodulé par un VCO à faible gain d'où il résulte un signal audio démodulé fD de quelques centaines de millivolts. En conséquence, le rapport signal sur bruit de ce signal audio démodulé fD sera meilleur que pour le signal audio démodulé fD associé à la figure 1.Consequently, the gain as a function of the frequency of the VCO goes from 3.07 MHz / V for 0.7 Hz to 70 kHz / V, for 30 Hz; 30 Hz corresponding to the frequency for which the gain of the VCO equals 70 kHz / V plus 3dB. In this case, the audio signal is demodulated by a low gain VCO from which there results a demodulated audio signal f D of a few hundred millivolts. Consequently, the signal-to-noise ratio of this demodulated audio signal f D will be better than for the demodulated audio signal f D associated with FIG. 1.

    La figure 3 est un schéma sous forme de blocs d'un mode de réalisation du VCO de la figure 2. Le VCO 230 comprend un oscillateur 300 et deux sources de courant commandées 305, 310. L'oscillateur 300 est de préférence un oscillateur classique commandé en courant tel qu'un oscillateur à émetteurs couplés. Il est alimenté par une source de tension positive VCC et fournit un signal de fréquence fVCO sur la sortie 240 et un courant I sur une sortie 315. La fréquence du signal fVCO est proportionnelle au courant I.FIG. 3 is a block diagram of an embodiment of the VCO of FIG. 2. The VCO 230 comprises an oscillator 300 and two controlled current sources 305, 310. The oscillator 300 is preferably a conventional oscillator current controlled such as an oscillator with coupled transmitters. It is supplied by a positive voltage source VCC and provides a frequency signal f VCO on output 240 and a current I on output 315. The frequency of signal f VCO is proportional to current I.

    Les bornes des sources de courant 305, 310, du côté haute tension, sont connectées à la sortie 315 et leurs bornes du côté basse tension sont connectées à une autre source de tension VEE qui est moins positive que la source de tension VCC. La source de courant 305 correspond à une source de courant à gain élevé qui est commandée par une "tension d'accord" VT sur l'entrée H et laisse passer un courant IT, tandis que la source de courant 310 correspond à une source de courant de gain faible qui est commandée pendant la démodulation par une "tension de démodulation" VD sur l'entrée L, et laisse passer un courant ID. Le courant I est la somme des courants IT et ID. Les sources de courant 305 et 310 sont commandées par les tensions VT, VD sur leurs entrées respectives H et L de sorte que le courant I est démodulé autour d'une valeur centrale qui module elle-même le signal de fréquence de sortie fVCO autour d'une fréquence centrale F0.The terminals of the current sources 305, 310, on the high voltage side, are connected to the output 315 and their terminals on the low voltage side are connected to another voltage source VEE which is less positive than the voltage source VCC. The current source 305 corresponds to a high gain current source which is controlled by a "tuning voltage" VT on the input H and lets current IT pass, while the current source 310 corresponds to a source of low gain current which is controlled during demodulation by a "demodulation voltage" VD on the input L, and allows a current ID to pass. Current I is the sum of IT and ID currents. The current sources 305 and 310 are controlled by the voltages VT, VD on their respective inputs H and L so that the current I is demodulated around a central value which itself modulates the output frequency signal f VCO around with a central frequency F 0 .

    La figure 4A représente un schéma de circuit d'un mode de réalisation de la source de courant de gain élevé 305 de la figure 3 et la figure 4B représente la caractéristique de transfert de la source de courant de gain élevé de la figure 4A. Cette source de courant de gain élevé 305 comprend quatre transistors NPN Q5-Q8 et quatre résistances R3-R6. Le gain de cette source de courant est sensiblement proportionnel au rapport de résistances R3/R6 ; les résistances R3 et R4 ont la même valeur. Le collecteur du transistor Q5 est connecté à la tension VCC, son émetteur est connecté au collecteur du transistor Q8 par l'intermédiaire d'une résistance R3 et sa base est polarisée par une tension de référence VREF1. Le collecteur du transistor Q6 correspond à la sortie 315, son émetteur est connecté au collecteur du transistor Q8 par une résistance R4 et sa base correspond à l'entrée H. L'émetteur du transistor Q8 est connecté à la tension VEE par l'intermédiaire de la résistance R6. Le collecteur du transistor Q7 est connecté à la tension VCC par l'intermédiaire de la résistance R5. Les bornes de base des transistors Q7 et Q8 sont connectées au collecteur du transistor Q7. L'émetteur du transistor Q7 est de préférence connecté à la tension VEE par l'intermédiaire d'une diode D1 qui assure une compensation en température en association avec un oscillateur à émetteurs couplés. La diode D1 peut être constituée d'un transistor NPN connecté en diode.Figure 4A shows a circuit diagram of an embodiment of the high gain current source 305 of Figure 3 and Figure 4B shows the transfer characteristic of the high gain current source of Figure 4A. This high gain current source 305 includes four NPN transistors Q5-Q8 and four resistors R3-R6. The gain of this current source is substantially proportional to the ratio of resistors R3 / R6; resistors R3 and R4 have the same value. The collector of transistor Q5 is connected to the voltage VCC, its emitter is connected to the collector of transistor Q8 via a resistor R3 and its base is biased by a reference voltage V REF1 . The collector of transistor Q6 corresponds to output 315, its emitter is connected to the collector of transistor Q8 by a resistor R4 and its base corresponds to input H. The emitter of transistor Q8 is connected to voltage VEE via of resistance R6. The collector of transistor Q7 is connected to the voltage VCC via the resistor R5. The basic terminals of transistors Q7 and Q8 are connected to the collector of transistor Q7. The emitter of transistor Q7 is preferably connected to the voltage VEE via a diode D1 which provides temperature compensation in association with an oscillator with coupled emitters. The diode D1 can consist of an NPN transistor connected as a diode.

    Cette source de courant 305 est en fait un amplificateur différentiel associé à un miroir de courant. Le courant extrait Ix est donné par la relation : Ix=VBE(diode)/R6. En conséquence, le courant IT est en première approximation donné par la relation : IT = Ix/2+(VT-VREF1)/2R3 = (VBE/2R6)+(VT-VREF1)/2 ; qui se ramène à IT=VBE/2R6 quand VT=VREF1.This current source 305 is in fact a differential amplifier associated with a current mirror. The extracted current I x is given by the relation: I x = V BE (diode) / R6. Consequently, the current IT is in first approximation given by the relation: IT = I x / 2 + (VT-V REF1 ) / 2R3 = (V BE / 2R6) + (VT-V REF1 ) / 2; which comes down to IT = V BE / 2R6 when VT = V REF1 .

    La fréquence centrale F0 du PLL est proportionnelle à: IT[(VBE/2R6)+(VT-VREF1)/2R3]. The central frequency F 0 of the PLL is proportional to: IT [(V BE / 2R6) + (VT-V REF1 ) / 2R3].

    Le gain de la source de courant commandée en tension 305 est donné par la relation dIT/dVT=1/2R3 et le gain du VCO, pour l'entrée H de gain élevé, est proportionnel à IT.The gain of the voltage-controlled current source 305 is given by the relation dIT / dVT = 1 / 2R3 and the gain of the VCO, for the high gain input H, is proportional to IT.

    Comme le représente la figure 4B, la caractéristique de transfert est linéaire en pratique seulement autour du point [VREF, Ix/2], c'est-à-dire entre les points A et B.As shown in FIG. 4B, the transfer characteristic is linear in practice only around the point [V REF , I x / 2], that is to say between the points A and B.

    La figure 5A représente un schéma de circuit d'un mode de réalisation de la source de courant de gain faible 310 de la figure 3 et la figure 5B représente la caractéristique de transfert de cette source de courant. Cette source de courant de gain faible 310 comprend deux transistors PNP Q9-Q10 ; trois transistors NPN Q11-Q13 ; quatre résistances R7-R10 ; un amplificateur opérationnel 600 et un amplificateur tampon 610.FIG. 5A represents a circuit diagram of a mode for making the low gain current source 310 of the Figure 3 and Figure 5B shows the transfer characteristic from this current source. This gain current source low 310 includes two PNP transistors Q9-Q10; three transistors NPN Q11-Q13; four resistors R7-R10; an amplifier operational 600 and a buffer amplifier 610.

    Les émetteurs des transistors Q9 et Q10 sont connectés à la tension VCC par l'intermédiaire de résistances respectives R7 et R8. Les collecteurs des transistors Q9 et Q10 sont respectivement connectés aux collecteurs des transistors Q11 et Q12 dont les émetteurs sont connectés à la tension VEE. Les collecteurs des transistors Q9 et Q11 sont connectés à la sortie 315 et reçoivent le courant ID (figure 3). Les bornes de base des transistors Q11 et Q12 sont connectées à la base et au collecteur du transistor Q13. Le collecteur du transistor Q13 est connecté à la tension VCC par l'intermédiaire de la résistance R9. Le transistor Q13 agit comme transistor d'entrée d'un miroir de courant ayant les transistors Q11 et Q12 comme transistors de sortie. La sortie L du commutateur 225 est connectée à l'entrée du tampon 610 qui est de préférence un amplificateur de gain unité. La sortie du tampon 610, qui est à la tension VD, est connectée à l'entrée positive 620 de l'amplificateur 600 par la résistance R10. L'entrée 620 est une tension désignée par V+. Les collecteurs des transistors Q10 et Q12 sont connectés à l'entrée positive 620 de l'amplificateur. L'entrée négative de l'amplificateur 600 est connectée à une source de tension de référence VREF2. Les bornes de base des transistors Q9 et Q10 sont connectées à la sortie 620 de l'amplificateur 600.The emitters of the transistors Q9 and Q10 are connected to the voltage VCC via respective resistors R7 and R8. The collectors of the transistors Q9 and Q10 are respectively connected to the collectors of the transistors Q11 and Q12, the emitters of which are connected to the voltage VEE. The collectors of transistors Q9 and Q11 are connected to output 315 and receive the current ID (Figure 3). The base terminals of the transistors Q11 and Q12 are connected to the base and to the collector of the transistor Q13. The collector of transistor Q13 is connected to voltage VCC via resistor R9. The transistor Q13 acts as the input transistor of a current mirror having the transistors Q11 and Q12 as the output transistors. The output L of the switch 225 is connected to the input of the buffer 610 which is preferably a unity gain amplifier. The output of the buffer 610, which is at the voltage VD, is connected to the positive input 620 of the amplifier 600 by the resistor R10. Input 620 is a voltage designated by V + . The collectors of the transistors Q10 and Q12 are connected to the positive input 620 of the amplifier. The negative input of amplifier 600 is connected to a reference voltage source V REF2 . The base terminals of transistors Q9 and Q10 are connected to output 620 of amplifier 600.

    L'amplificateur 600 agit pour que ses entrées positive et négative soient toujours identiques ; ainsi V+=VREF2. Ceci amène un courant IY à circuler du collecteur du transistor Q10 à travers la résistance R10, cette valeur de courant étant donnée par la relation : IY = [V+-VD]/R10 = (VREF2 - VD)/R10. En conséquence, le courant ID est obtenu par une recopie du courant IY de sorte que : ID = -IY = -(VREF2-VD)/R10. La fréquence de modulation FM est proportionnelle à ID et donc à -(VREF2-VD)/R10.Amplifier 600 acts so that its positive and negative inputs are always identical; thus V + = V REF2 . This causes a current I Y to flow from the collector of transistor Q10 through the resistor R10, this current value being given by the relation: I Y = [V + -VD] / R10 = (V REF2 - VD) / R10. Consequently, the current I D is obtained by a copy of the current I Y so that: ID = -I Y = - (V REF2 -VD) / R10. The modulation frequency F M is proportional to ID and therefore to - (V REF2 -VD) / R10.

    Si l'amplificateur 600 a un gain élevé, ceci permet à la réponse en courant en fonction de la tension d'être extrêmement linéaire, comme cela est illustré en figure 5B.If the amplifier 600 has a high gain, this allows the current response as a function of the voltage to be extremely linear, as illustrated in Figure 5B.

    La figure 6 est un schéma sous forme de blocs d'un mode de réalisation du bloc de commande 215 de la figure 2. Ce bloc de commande 215 comprend une bascule du type RS 800 et un bloc logique 805. Les sorties respectives 255, 260, 265 du comparateur de fréquence 220, du comparateur de niveau 210 et de la bascule 800 sont envoyées au bloc logique 805.Figure 6 is a block diagram of a embodiment of the control block 215 of FIG. 2. This control block 215 includes a rocker of the RS 800 type and a logic block 805. The respective outputs 255, 260, 265 of the frequency comparator 220, level comparator 210 and flip-flop 800 are sent to logic block 805.

    La bascule 800 et le bloc logique 805 sont disposés par exemple de sorte que la sortie 265 de la bascule 800 a un état logique 0 à moins que les entrées 255, 260 aient toutes deux des états logiques 1, c'est-à-dire à moins que les fréquences des signaux sur les entrées 235, 240 du mélangeur 200 soient sensiblement égales et que les niveaux des signaux sur les entrées 245, 250 du commutateur 225 soient sensiblement égaux. Quand les entrées 255, 260 ont toutes deux des états logiques 1, la sortie 265 de la bascule 800 passe d'un état logique 0 à un état logique 1 et reste à l'état logique 1 jusqu'à ce que la sortie 255 du comparateur de fréquence 220 change d'état pour indiquer que la fréquence du PLL n'est pas "verrouillée" quel que soit l'état du signal en provenance du comparateur de niveau 210, c'est-à-dire que la bascule 800 et le bloc logique 805 agissent comme un verrou.The flip-flop 800 and the logic block 805 are arranged for example so that output 265 of flip-flop 800 has a logic state 0 unless inputs 255, 260 all have two of the logic states 1, i.e. unless the frequencies signals on inputs 235, 240 of mixer 200 are substantially equal and that the signal levels on the inputs 245, 250 of switch 225 are substantially equal. When inputs 255, 260 both have logic states 1, the output 265 of flip-flop 800 passes from a logic state 0 to a logical state 1 and remains in logical state 1 until the output 255 of the frequency comparator 220 changes state for indicate that the PLL frequency is not "locked" which that either the state of the signal coming from the level comparator 210, that is to say the flip-flop 800 and the logic block 805 act like a lock.

    La figure 7A est un schéma sous forme de blocs d'un mode de réalisation du comparateur de niveau 210 de la figure 2. Ce schéma représente un amplificateur 900, un mélangeur 905 et un comparateur 910.Figure 7A is a block diagram of a embodiment of the level comparator 210 of the figure 2. This diagram represents an amplifier 900, a mixer 905 and a comparator 910.

    L'amplificateur 900, qui fournit des sorties différentielles 915, 920, reçoit des entrées en provenance de l'entrée 245 et de la sortie 250 du filtre 205. Les sorties 915, 920 sont connectées au mélangeur 905 qui réalise une fonction d'élévation au carré, c'est-à-dire une fonction X2, sur la différence de tension inversée et non-inversée ΔV des signaux sur ces sorties 915, 920. La sortie 925 du mélangeur est connectée à l'entrée positive du comparateur 910 dont l'entrée négative est polarisée par une tension de référence VREF3 et dont la sortie 260 fournit un signal logique.Amplifier 900, which provides differential outputs 915, 920, receives inputs from input 245 and output 250 from filter 205. Outputs 915, 920 are connected to mixer 905 which performs an elevation function squared, ie a function X 2 , on the inverted and non-inverted voltage difference ΔV of the signals on these outputs 915, 920. The output 925 of the mixer is connected to the positive input of comparator 910 whose negative input is polarized by a reference voltage V REF3 and whose output 260 provides a logic signal.

    La figure 7B représente la relation entre les signaux qui sont présents sur les sorties 925 et 260 de la figure 7A. Le signal supérieur représente le produit de la différence de tension ΔV inversée et non-inversée des signaux présents sur les sorties 915 et 920 de l'amplificateur 900. Le signal inférieur représente le signal sur la sortie 260 du comparateur 910. Quand la tension sur la sortie 925 du mélangeur 905 est inférieure à VREF3, la sortie 260 du comparateur a un état logique 1 et, quand la tension sur la sortie 925 du mélangeur 905 est supérieure à VREF3, la sortie 260 du comparateur a un état logique 0.FIG. 7B represents the relationship between the signals which are present on the outputs 925 and 260 of FIG. 7A. The upper signal represents the product of the inverted and non-inverted voltage difference ΔV of the signals present on outputs 915 and 920 of amplifier 900. The lower signal represents the signal on output 260 of comparator 910. When the voltage on the output 925 of the mixer 905 is less than V REF3 , the output 260 of the comparator has a logic state 1 and, when the voltage on the output 925 of the mixer 905 is greater than V REF3 , the output 260 of the comparator has a logic state 0 .

    La figure 8A est un schéma sous forme de blocs d'un mode de réalisation du comparateur de fréquence 220 de la figure 2. Ce schéma représente un mélangeur 1000, un filtre passe-bas 1010, un comparateur 1020 et un intégrateur numérique 1030.Figure 8A is a block diagram of a embodiment of the frequency comparator 220 of the figure 2. This diagram represents a mixer 1000, a low-pass filter 1010, a comparator 1020 and a digital integrator 1030.

    Le mélangeur 1000 mélange les signaux respectifs fIN, fVCO sur les entrées 235, 240 et fournit une sortie 1040 qui est connectée au filtre 1010. Le filtre 1010 a par exemple une fréquence de coupure de 400 kHz. La sortie 1050 du filtre 1010, qui est une tension VIN, est connectée à l'entrée positive du comparateur 1020 dont l'entrée négative est polarisée par une tension de référence VREF4. Le comparateur 1020 fournit un signal logique VOUT sur sa sortie 1060 qui est connectée à l'entrée de l'intégrateur 1030. La sortie de l'intégrateur 1030 constitue la sortie 255.The mixer 1000 mixes the respective signals f IN , f VCO on the inputs 235, 240 and provides an output 1040 which is connected to the filter 1010. The filter 1010 has for example a cut-off frequency of 400 kHz. The output 1050 of the filter 1010, which is a voltage V IN , is connected to the positive input of the comparator 1020 whose negative input is biased by a reference voltage V REF4 . The comparator 1020 provides a logic signal V OUT on its output 1060 which is connected to the input of the integrator 1030. The output of the integrator 1030 constitutes the output 255.

    La figure 8B représente la tension VIN, c'est-à-dire la tension de sortie du filtre 1010, quand la différence de fréquence f1 entre fIN et fVCO est supérieure à environ 1 MHz. Le filtre 1010 élimine par filtrage les composantes de fréquence supérieures à environ 400 kHz et ceci laisse un signal dont la valeur de crête n'est jamais supérieure à la référence VREF4. En conséquence, la sortie du comparateur 1020 et de l'intégrateur est toujours à un niveau logique 0.FIG. 8B represents the voltage V IN , that is to say the output voltage of the filter 1010, when the frequency difference f 1 between f IN and f VCO is greater than approximately 1 MHz. The filter 1010 eliminates by filtering the frequency components higher than approximately 400 kHz and this leaves a signal whose peak value is never higher than the reference V REF4 . Consequently, the output of comparator 1020 and of the integrator is always at logic level 0.

    La figure 8C représente la tension VIN quand la différence de fréquence f2 entre fIN et fVCO est inférieure à environ 1 MHz. A nouveau, le filtre 1010 élimine par filtrage les composantes de fréquences supérieures à environ 400 kHz. Toutefois, dans ce cas, VIN a une valeur de crête qui est parfois supérieure à la référence VREF4 puisque le filtre 1010 a moins d'influence sur son signal d'entrée. Il en résulte un signal de sortie VIN de plus grande amplitude. En conséquence, la sortie du comparateur 1020 aura un état logique 1 chaque fois que VIN est supérieure à VREF4. L'intégrateur agit comme un filtre par rapport à la sortie du comparateur et peut être disposé de sorte qu'il aura un état logique 0 jusqu'à ce que les fréquences fIN, fVCO aient suffisamment convergé, par exemple quand les fréquences fIN, fVCO sont à moins de 100 kHz l'une de l'autre. FIG. 8C represents the voltage V IN when the frequency difference f 2 between f IN and f VCO is less than approximately 1 MHz. Again, the filter 1010 filters out the frequency components greater than about 400 kHz. However, in this case, V IN has a peak value which is sometimes greater than the reference V REF4 since the filter 1010 has less influence on its input signal. This results in an output signal V IN of greater amplitude. Consequently, the output of comparator 1020 will have a logic state 1 each time V IN is greater than V REF4 . The integrator acts as a filter with respect to the comparator output and can be arranged so that it will have a logic state 0 until the frequencies f IN , f VCO have sufficiently converged, for example when the frequencies f IN , f VCO are within 100 kHz of each other.

    La figure 8D représente la tension VIN quand la différence de fréquence f2 entre fIN et fVCO est sensiblement nulle. Dans ce cas, la tension VIN est sensiblement une tension continue qui est toujours supérieure à VREF4 et, en conséquence, les sorties respectives 1060 et 255 du comparateur et de l'intégrateur ont des états logiques 1.FIG. 8D represents the voltage V IN when the frequency difference f 2 between f IN and f VCO is substantially zero. In this case, the voltage V IN is substantially a direct voltage which is always greater than V REF4 and, consequently, the respective outputs 1060 and 255 of the comparator and of the integrator have logic states 1.

    Les figures 9A et 9B représentent deux modes de réalisation d'un accélérateur qui peut être utilisé en relation avec la présente invention pour réduire la constante de temps du filtre passe-bas 205 de la figure 2 quand le filtre 205 est un filtre passe-bas RC, comme cela est représenté en pointillés.Figures 9A and 9B show two embodiments an accelerator which can be used in conjunction with the present invention to reduce the time constant of the low pass filter 205 of FIG. 2 when the filter 205 is a RC low-pass filter, as shown in dotted lines.

    La fonction de base de l'accélérateur est de réduire, pendant le mode "d'accord", c'est-à-dire pendant le premier mode fonctionnel, la résistance du filtre passe-bas 205 de sorte que le condensateur de ce filtre peut se charger plus rapidement, c'est-à-dire que le condensateur peut suivre plus rapidement la tension d'entrée du filtre. En figure 9A, l'accélérateur est une résistance commutée 1100 placée en parallèle sur la résistance du filtre. La résistance commutée est commandée par la sortie 265 du bloc de commande de sorte que, quand le système est dans son premier mode fonctionnel, la résistance commutée est placée en parallèle avec la résistance du filtre et, quand le système est dans son second mode fonctionnel, c'est-à-dire le mode de "démodulation", la résistance commutée n'a pas d'effet sur la résistance du filtre.The basic function of the accelerator is to reduce, during the "ok" mode, that is to say during the first mode functional, the resistance of the low-pass filter 205 so that the capacitor of this filter can charge more quickly, that is, the capacitor can follow the filter input voltage. In FIG. 9A, the accelerator is a switched resistance 1100 placed in parallel on the resistance of the filter. The switched resistance is controlled by the output 265 from the control block so that when the system is in its first functional mode, the switched resistor is placed in parallel with the resistance of the filter and, when the system is in its second functional mode, i.e. the mode of "demodulation", the switched resistance has no effect on the filter resistance.

    A titre de variante, comme cela est représenté en figure 9B, la résistance commutée peut être réalisée sous forme d'un amplificateur à transconductance convenablement connecté et commandé 1110.Alternatively, as shown in Figure 9B, the switched resistance can be realized in the form a suitably connected transconductance amplifier and ordered 1110.

    La présente invention peut être adaptée pour être avantageusement utilisée à la démodulation, de préférence mais non nécessairement à la démodulation FM, du son dans des systèmes de radio ou de télévision et/ou des systèmes vidéo et/ou des systèmes de récepteurs de satellite.The present invention can be adapted to be advantageously used for demodulation, preferably but not necessarily FM demodulation, sound in systems radio or television and / or video systems and / or satellite receiver systems.

    Claims (9)

    1. A demodulation phase-locked loop including a mixer (100) connected to a controlled oscillator (230), characterized in that it comprises:
      said controlled oscillator (230) having a low gain control input (L), a high gain control input (H), and an output (240) connected to a first input of the mixer (100);
      a first low-pass filter (205) having its input connected to the output (245) of the mixer (100);
      a level comparator (210) which provides an output (260) that is active when the signal levels at the input (245) and the output (250) of the first filter (205) have sufficiently converged;
      a frequency comparator (220) which provides an output (255) that is active when the signal frequencies (fVCO, fIN) at the first and second inputs (240, 235) of the mixer (100) have sufficiently converged;
      a controlled switch (225) having a first position in which the input and the output (245, 250) of the first filter (205) are respectively connected to the high gain (H) and to low gain (L) inputs of the controlled oscillator (230), and a second position in which the input and the output (245, 250) of the first filter (205) are connected to the low gain (L) and the high gain (H) inputs of the oscillator (230), respectively; and
      control means (215), coupled to said level comparator and said frequency comparator, for selecting the first position of the switch (225) when the frequencies of the signal on the first and second inputs (240, 235) of the mixer (100) have not sufficiently converged and the second position of the switch (225) when the frequencies of the signal on the first and second inputs (240, 235) of the mixer (100) and the levels of the signal at the input and the output (245, 250) of the first filter (205) have sufficiently converged.
    2. The demodulation phase-locked loop of claim 1, characterized in that the controlled oscillator (230) comprises a current-controlled oscillator (300) and first and second voltage-controlled current sources (305, 310) that have control inputs which correspond to the high gain and to the low gain (H, L) inputs of the controlled oscillator (230), respectively, to control the frequency of the current-controlled oscillator (300).
    3. The demodulation phase-locked loop of claim 2, characterized in that the second voltage-controlled current source (310) has very linear characteristics.
    4. The demodulation phase-locked loop of any of claims 1 to 3, characterized in that it comprises a second low-pass filter (110) and a buffer (120) which are connected downstream the mixer (100) and upstream the first filter (205), of the controlled switch (225) and level comparator (210).
    5. The demodulation phase-locked loop of any of claims 1 to 4, characterized in that the first filter (205) is a filter including a resistor and a capacitor.
    6. The demodulation phase-locked loop of claim 5, characterized in that it includes a means for decreasing the value of the resistance of the first filter (205) when the switch (225) is in its first position.
    7. A satellite receiver characterized in that it includes a demodulation phase-locked loop according to any of claims 1 to 6.
    8. A radio system characterized in that it includes a demodulation phase-locked loop according to any of claims 1 to 6.
    9. A television system characterized in that it includes demodulation phase-locked loop according to any of claims 1 to 6.
    EP96410007A 1995-01-13 1996-01-10 PLL-FM demodulator Expired - Lifetime EP0722215B1 (en)

    Applications Claiming Priority (2)

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    FR9500603 1995-01-13
    FR9500603A FR2729518B1 (en) 1995-01-13 1995-01-13 DEMODULATION PHASE LOCKED LOOP OF A FREQUENCY MODULATED SIGNAL

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    EP0722215A1 EP0722215A1 (en) 1996-07-17
    EP0722215B1 true EP0722215B1 (en) 2001-08-16

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    Also Published As

    Publication number Publication date
    FR2729518A1 (en) 1996-07-19
    US5640126A (en) 1997-06-17
    FR2729518B1 (en) 1997-06-06
    JP2932997B2 (en) 1999-08-09
    EP0722215A1 (en) 1996-07-17
    JPH08288878A (en) 1996-11-01
    US5850164A (en) 1998-12-15
    DE69614415D1 (en) 2001-09-20

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