EP0715239A1 - Mirroir de courant de haute précision pour alimentation à basse tension - Google Patents

Mirroir de courant de haute précision pour alimentation à basse tension Download PDF

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Publication number
EP0715239A1
EP0715239A1 EP94830555A EP94830555A EP0715239A1 EP 0715239 A1 EP0715239 A1 EP 0715239A1 EP 94830555 A EP94830555 A EP 94830555A EP 94830555 A EP94830555 A EP 94830555A EP 0715239 A1 EP0715239 A1 EP 0715239A1
Authority
EP
European Patent Office
Prior art keywords
transistor
transistors
terminal
terminals
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP94830555A
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German (de)
English (en)
Other versions
EP0715239B1 (fr
Inventor
Francesco Brianti
Valerio Pisati
Roberto Alini
David Moloney
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
SGS Thomson Microelectronics SRL
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Publication date
Application filed by STMicroelectronics SRL, SGS Thomson Microelectronics SRL filed Critical STMicroelectronics SRL
Priority to DE1994627479 priority Critical patent/DE69427479T2/de
Priority to EP19940830555 priority patent/EP0715239B1/fr
Publication of EP0715239A1 publication Critical patent/EP0715239A1/fr
Application granted granted Critical
Publication of EP0715239B1 publication Critical patent/EP0715239B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/265—Current mirrors using bipolar transistors only
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • This invention relates to a high-precision current generating circuit.
  • the invention particularly concerns a high-precision current generating circuit for a low-impedance circuit user outlet, being of the type which comprises a current mirror having an input branch which is applied a reference current and an output branch which supplies a proportional current to the reference current.
  • a current mirror configuration is a conventional circuit arrangement which is normally employed to generate a constant output current proportional to a given reference current.
  • Such circuits can be implemented, in general, either using transistors of the bipolar type or transistors of the MOS type.
  • the current mirror described in the above-mentioned book comprises two transistors and a reference current generator.
  • the reference generator comprises a resistor connected in series with one of the two transistors.
  • the relatively low precision of such a circuit can be explained in relation to its implementation with transistors of the MOS type.
  • the output current from the generator is supplied by one of the two MOS transistors comprising the mirror, and as is well recognized, the internal resistance of a MOS transistor varies with the difference in potential between its drain and source terminals. Since the drain terminal of the transistor, which outputs the current, is usually connected to a load whose impedance may not be always constant, the voltage Vds between the drain and the source of the transistor may also vary during the normal operation of the circuit. This variation in voltage results in a variation in the internal resistance of the transistor, and consequently in the output current from the circuit.
  • cascode current mirror configuration
  • This prior approach while representing an advance from the standpoint of precision, still has some shortcomings. Its particular cascode structure, for instance, reduces the useful dynamic range for the signal, making the circuit unsuited to low supply voltage applications, e.g. in the 2.5 to 3 volts range.
  • Wilson configuration of the current generating circuit is an improvement over the former arrangement as far as precision is concerned, but is again beset with the same drawbacks as the former approach in that it retains the cascode configuration. Also, this approach disallows the biasing of plural output branches on the basis of a single reference current and cannot provide plural output currents.
  • the underlying technical problem of this invention is to provide a current generating circuit which has such high-precision functional features, and constructional features of reduced silicon area occupation in the integrated circuit, as to overcome the aforementioned drawbacks besetting the prior art.
  • the circuit 1 is a current mirror configuration, and comprises two transistors M1 and M2 of the N-channel MOS type.
  • the first transistor M1 forms substantially the input branch 2 of the current mirror and has its source terminal S1 connected to a fixed potential reference, specifically the electric ground GND of the circuit.
  • the drain terminal D1 of the transistor M1 is connected to a reference current Iref generator.
  • the output branch 3 of the current mirror comprises the second transistor M2.
  • the source terminal S2 of the transistor M2 is connected to the circuit electric ground GND, its drain terminal D2 being the output terminal of the circuit.
  • control terminals G1 and G2 of both transistors M1 and M2 are connected together.
  • a voltage regulator 4 is connected to the drain terminals D1 and D2 of the transistors M1 and M2 to maintain at said terminals a drain-source voltage value, Vds1 and Vds2, which is the same for both transistors.
  • the voltage regulator 4 comprises an operational amplifier OA having two inputs, one of the inverting (-) type and another of the non-inverting (+) type, and an output U.
  • the non-inverting (+) input of the amplifier OA is connected to the drain terminal D1 of the first transistor M1.
  • the inverting (-) input is connected to the drain terminal D2 of the second transistor M2, and the output U is connected to the common node A between the gate terminals G1 and G2 of both transistors M1, M2.
  • a compensation capacitor C1 is connected between the output U and the non-inverting (+) input of the operational amplifier.
  • the reference current Iref being flowed through the first transistor M1 is mirrored into the current Iout from the second transistor M2.
  • the two transistors have their source terminals S1 and S2, and gate terminals G1 and G2, connected together.
  • the voltage regulator 4 consisting of the operational amplifier OA, implies that the drain-source voltages Vds1 and Vds2 should be the same value for both transistors M1 and M2. Accordingly, since the transistors M1 and M2 also have the same gate-source voltage, they will be operating in exactly the same condition.
  • the bias voltage of the two transistors M1 and M2 is supplied from the output U of the operational amplifier OA.
  • the output terminal U of the amplifier OA is connected to the gate terminal G1 of the transistor M1, and the drain terminal D1 of this transistor is connected to the non-inverting (+) input of the amplifier OA.
  • the feedback loop on this branch is bound to be a negative one.
  • the capacitor C1 also feedback connected between the output U and the non-inverting (+) input of the amplifier OA, applies a typical compensation, referred to as "pole splitting", whereby the poles are split by Miller's Effect.
  • the feedback branch connected to the inverting (-) input of the amplifier OA it is at once apparent that the feedback at this input is a positive one.
  • the signal present on the amplifier output U is inverted by the transistor M2 before it is applied to the inverting (-) input.
  • the load connected to the output of this current generator, on the drain terminal D2 of the transistor M2 has a very low input impedance value.
  • FIG 2 Shown in Figure 2 is a wiring diagram for a first implementation of the current generating circuit in Figure 1.
  • the same circuit arrangement as in the previous embodiment has now been implemented using P-channel MOS transistors.
  • the circuit 1 comprises two P-channel transistors M1 and M2, and a voltage regulator 4.
  • the first transistor M3 forms the input branch 2 of the current mirror and has its source terminal S3 connected to a fixed potential reference, specifically the positive pole Vcc of the supply voltage generator, while its drain terminal D3 is connected to a reference current Iref generator.
  • the output branch 3 of the current mirror consists of a second P-channel transistor M4.
  • the source terminal S4 of this transistor is connected to the positive pole Vcc of the supply voltage generator, while the transistor drain terminal D4 is coincident with the output terminal of the circuit.
  • control terminals G3 and G4 of both transistors M3 and M4 are connected together.
  • a voltage regulator 4 is connected to the drain terminals D3 and D4 of the transistors M3 and M4, thereby maintaining on said terminals a drain-source voltage value, Vds3 and Vds4, which is the same for both transistors.
  • the voltage regulator 4 comprises an operational amplifier OA having two inputs, one of the inverting (-) type and another of the non-inverting (+) type, and an output U.
  • the non-inverting (+) input of the amplifier OA is connected to the drain terminal D3 of the first transistor M3.
  • the inverting (-) input is connected to the drain terminal D4 of the second transistor M4, while the output U is connected to the common node A between the gate terminals G3 and G4 of both transistors M3 and M4.
  • a compensation capacitor C1 is connected between the output U and the non-inverting (+) input of the operational amplifier.
  • the circuit of Figure 2 operates in the same manner as the previously described circuit of Figure 1.
  • the voltage regulator 4 consisting of the operational amplifier OA, implies that the drain-source voltages, Vds3 and Vds4, at the two transistors M3 and M4 should be the same value.
  • transistors M3 and M4 at the same gate-source voltage, they will operate in exactly the same condition.
  • the feedback existing at the inverting (-) input of the operational amplifier OA is a positive one. It is therefore necessary that, to reduce the loop gain of said positive feedback to a value of less than one, the load connected to the output of this current generator has a very low input impedance value.
  • Figure 1 The circuit of Figure 1 is illustrated in greater detail by Figure 3; in particular, an optional embodiment of the operational amplifier OA using transistors of the MOS type is shown.
  • This amplifier OA is formed by four MOS transistors denoted by M5, M6, M7 and M8, in a known circuit arrangement.
  • the two P-channel transistors M5 and M6 form the differential input stage, while the drain terminal D8 of the N-channel transistor M8 is the output terminal U of the amplifier.
  • FIG 4 Shown in Figure 4 is a wiring diagram for a second implementation of the current generating circuit illustrated by Figure 1. In particular, a circuit arrangement is shown which uses bipolar transistors of the NPN type.
  • the circuit 1 comprises two transistors T1 and T2 and a voltage regulator 4.
  • the first transistor T1 forms the input branch 2 of the current mirror and has its emitter terminal E1 connected to a fixed potential reference, specifically the electric ground GND of the circuit, while its collector terminal C1 is connected to a reference current Iref generator.
  • the output branch 3 of the current mirror consists of a second transistor T2.
  • the emitter terminal E2 of this transistor is connected to the electric ground GND of the circuit, the transistor collector terminal C2 being the output terminal of the circuit.
  • the base terminals B1 and B2 of both transistors T1 and T2 are connected together.
  • a voltage regulator 4 is connected to the collector terminals C1 and C2 of the transistors T1 and T2 to maintain at said terminals a collector-emitter voltage value, Vce1 and Vce2, which is the same for both transistors.
  • the voltage regulator 4 comprises an operational amplifier OA having two inputs, one of the inverting (-) type and another of the non-inverting (+) type, and an output U.
  • the non-inverting (+) input of the amplifier OA is connected to the collector terminal C1 of the first transistor T1.
  • the inverting (-) input is connected to the collector terminal C2 of the second transistor T2, while the output U is connected to the common node A between the base terminals B1 and B2 of both transistors T1 and T2.
  • a compensation capacitor C1 is connected between the output U of the operational amplifier and the non-inverting (+) input thereof.
  • the voltage regulator 4 consisting of the operational amplifier OA, implies that the collector-emitter voltages Vce1 and Vce2 at the two transistors T1 and T2 should be the same value. Accordingly, since the transistors T1 and T2 also have equal base-emitter voltages, they will be operating in similar conditions.
  • the feedback existing at the inverting (-) input of the operational amplifier OA is in this circuit positive, as in the circuit of Figure 1. It is necessary, therefore, that in order to reduce the loop gain of said positive feedback to a value of less than unity, the load connected to the output of this current generator has a very low input impedance value.
  • Figure 5 shows a wiring diagram for a third implementation of the current generating circuit illustrated by Figure 1.
  • the same circuit arrangement has been embodied here using bipolar transistors of the PNP type.
  • the circuit comprises two transistors T3 and T4 and a voltage regulator 4.
  • the first transistor T3 forms the input branch of the current mirror and has its emitter terminal E3 connected to a fixed potential reference, specifically the positive pole Vcc of the supply voltage generator, while its collector terminal C3 is connected to a reference current Iref generator.
  • the output branch of the current mirror consists of a second transistor T4.
  • the emitter terminal E4 of this transistor is connected to the positive pole Vcc of the supply voltage generator, while the transistor collector terminal C4 is the output terminal of the circuit.
  • the base terminals B3 and B4 of both transistors T3 and T4 are connected together.
  • a voltage regulator 4 is connected to the collector terminals C3 and C4 of the transistors T3 and T4 to maintain, at said terminals, an equal collector-emitter voltage value, Vce3 and Vce4, for both transistors.
  • the non-inverting (+) input of the amplifier OA is connected to the collector terminal C3 of the first transistor T3.
  • the inverting (-) input is connected to the collector terminal C4 of the second transistor T4, while the output U is connected to the common node A between the base terminals B3 and B4 of both transistors T3 and T4.
  • a compensation capacitor C1 is connected between the output U and the non-inverting (+) input of the operational amplifier.
  • the circuit of Figure 5 operates similar to the circuit of Figure 1.
  • the voltage regulator 4 comprising the operational amplifier OA, implies that the collector-emitter voltages, Vce3 and Vce4, at the two transistors T3 and T4 should be the same. Accordingly, since the transistors T3 and T4 also have the same base-emitter voltage, their conditions of operation will also be the same.
  • this circuit also has a positive feedback present at the inverting (-) input of the operational amplifier OA, whereby the load connected to the output of this current generator is to have a very low input impedance value, if the loop gain of said positive feedback is to be a value of less than unity.
  • Figure 6 shows a wiring diagram for a digital-to-analog converter which employs a high-precision current generating circuit in accordance with this invention.
  • the output branch 30 of the current mirror circuit 10 comprises, additionally to the first transistor M12, two more transistors M13 and M14.
  • the drain D13, D14 and source S13, S14 terminals of these transistors are respectively connected to the drain D12 and source S12 terminals of the first transistor M12, while their gate terminals G13 and G14 are connected, each through a switch sw1 and sw2, to the gate terminal G12 of the first transistor M12.
  • the two switches sw1 and sw2 are controlled by the digital input signal, and the currents flowed through the individual transistors M12, M13 and M14 are summed into the output current Iout from the D/A converter.
  • the digital input signal is a two-bit signal, but it would be quite easy, as can be evinced from the modular construction of the output branch 30, to multiply the number of the transistors provided to achieve enhanced resolution for the D/A converter.
  • the circuit of this invention provides a high-precision current generator which is quite simple circuit-wise.
  • this circuit can be used in different technologies, bipolar and MOS transistors, and can operate on a low supply voltage.
  • a further advantage is that the output branch of this current generator can be easily duplicated to output several currents from a single reference current.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)
  • Control Of Electrical Variables (AREA)
EP19940830555 1994-11-30 1994-11-30 Mirroir de courant de haute précision pour alimentation à basse tension Expired - Lifetime EP0715239B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE1994627479 DE69427479T2 (de) 1994-11-30 1994-11-30 Hochgenauer Stromspiegel für niedrige Versorgungsspannung
EP19940830555 EP0715239B1 (fr) 1994-11-30 1994-11-30 Mirroir de courant de haute précision pour alimentation à basse tension

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP19940830555 EP0715239B1 (fr) 1994-11-30 1994-11-30 Mirroir de courant de haute précision pour alimentation à basse tension

Publications (2)

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EP0715239A1 true EP0715239A1 (fr) 1996-06-05
EP0715239B1 EP0715239B1 (fr) 2001-06-13

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EP19940830555 Expired - Lifetime EP0715239B1 (fr) 1994-11-30 1994-11-30 Mirroir de courant de haute précision pour alimentation à basse tension

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EP (1) EP0715239B1 (fr)
DE (1) DE69427479T2 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0994402A1 (fr) * 1998-10-15 2000-04-19 Lucent Technologies Inc. Miroir de courant
EP1004953A1 (fr) * 1998-11-25 2000-05-31 Siemens Aktiengesellschaft Dispositif de commande d'un générateur de courant
EP1884856A1 (fr) * 2006-07-26 2008-02-06 Austriamicrosystems AG Circuit convertisseur tension/courant et méthode pour produire un courant en rampe.
WO2009046151A1 (fr) * 2007-10-03 2009-04-09 Qualcomm Incorporated Amplificateur de courant à double trajet
US8085092B2 (en) 2006-07-26 2011-12-27 Austriamicrosystems Ag Amplifier arrangement and method for amplification

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4587477A (en) * 1984-05-18 1986-05-06 Hewlett-Packard Company Binary scaled current array source for digital to analog converters
EP0356570A1 (fr) * 1988-09-02 1990-03-07 Siemens Aktiengesellschaft Miroir de courant
EP0403195A1 (fr) * 1989-06-12 1990-12-19 Inmos Limited Circuit miroir de courant
EP0461803A2 (fr) * 1990-06-11 1991-12-18 International Business Machines Corporation Convertisseur numérique-analogique
EP0523266A1 (fr) * 1991-07-17 1993-01-20 Siemens Aktiengesellschaft Miroir à courant intégrable
US5212458A (en) * 1991-09-23 1993-05-18 Triquint Semiconductor, Inc. Current mirror compensation circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4587477A (en) * 1984-05-18 1986-05-06 Hewlett-Packard Company Binary scaled current array source for digital to analog converters
EP0356570A1 (fr) * 1988-09-02 1990-03-07 Siemens Aktiengesellschaft Miroir de courant
EP0403195A1 (fr) * 1989-06-12 1990-12-19 Inmos Limited Circuit miroir de courant
EP0461803A2 (fr) * 1990-06-11 1991-12-18 International Business Machines Corporation Convertisseur numérique-analogique
EP0523266A1 (fr) * 1991-07-17 1993-01-20 Siemens Aktiengesellschaft Miroir à courant intégrable
US5212458A (en) * 1991-09-23 1993-05-18 Triquint Semiconductor, Inc. Current mirror compensation circuit

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0994402A1 (fr) * 1998-10-15 2000-04-19 Lucent Technologies Inc. Miroir de courant
US6194957B1 (en) 1998-10-15 2001-02-27 Lucent Technologies Inc. Current mirror for preventing an extreme voltage and lock-up
EP1004953A1 (fr) * 1998-11-25 2000-05-31 Siemens Aktiengesellschaft Dispositif de commande d'un générateur de courant
EP1884856A1 (fr) * 2006-07-26 2008-02-06 Austriamicrosystems AG Circuit convertisseur tension/courant et méthode pour produire un courant en rampe.
US7663409B2 (en) 2006-07-26 2010-02-16 Austriamicrosystems Ag Voltage/current converter circuit and method for providing a ramp current
US8085092B2 (en) 2006-07-26 2011-12-27 Austriamicrosystems Ag Amplifier arrangement and method for amplification
WO2009046151A1 (fr) * 2007-10-03 2009-04-09 Qualcomm Incorporated Amplificateur de courant à double trajet
US7724092B2 (en) 2007-10-03 2010-05-25 Qualcomm, Incorporated Dual-path current amplifier

Also Published As

Publication number Publication date
DE69427479D1 (de) 2001-07-19
EP0715239B1 (fr) 2001-06-13
DE69427479T2 (de) 2002-01-17

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