Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
  • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
  • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
  • H03K19/1778—Structural details for adapting physical parameters
  • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
  • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
  • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
  • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns

Definitions

• the invention relates to programmable logic devices formed in integrated circuits and more particularly to an architecture of a programmable logic device in which logic blocks are provided in a repeating pattern.
• FPGAs Field programmable gate arrays
• An FPGA comprises an array of configurable logic blocks (CLBs) which are programmably interconnected to each other to provide a logic function desired by a user.
• CLBs configurable logic blocks
• An FPGA is considered to be a general purpose device, i.e. being capable of performing any one of a plurality of functions, and is programmed by an end user to perform a selected function. Because of this design flexibility, a general purpose FPGA includes a significant number of wiring lines and transistors which remain unused in most applications. Moreover, FPGAs include overhead devices which facilitate programing of the FPGA to do the specified function. These overhead devices undesirably add area to the FPGA chip.
• a field programmable gate array (FPGA) architecture includes repeatable tiles.
• Each tile comprises a programmable routing matrix and a configurable logic block matrix.
• the configurable logic block matrix is programmably connectable to the programmable routing matrix, as well as to the configurable logic block matrices in adjacent tiles.
• the programmable routing matrix is programmably connectable to the programmable routing matrices adjacent to the tile, as well as to long lines which extend across the tile.
• each tile provides a combination of logic, connection to nearby tiles, and connection to a general routing structure. A plurality of these tiles are joined together to form an array of tiles which make up the functional portion of an FPGA chip.
• the programmable routing matrix and configurable logic block matrix minimize the number of programmable interconnection points (PIPs), thereby reducing expensive chip area and maximizing density of the entire chip.
• PIPs programmable interconnection points
• proper positioning of the PIPs ensures the necessary routing flexibility, thereby maximizing functionality of the FPGA.
• a tile architecture has a set of signal lines exiting the tile at the boundaries. Thus, for example, signal lines exiting at the right of one tile connect with signal lines exiting at the left of another tile. In one embodiment, adjacent tiles are identical, forming a repeating pattern.
• adjacent tiles are not identical but have signal lines at least most of which match at the tile boundaries.
• a chip can be formed as an array of modular units which match at their boundaries, and additional flexibility of designing tiles for use in a plurality of chip designs i ⁇ easily available.
• Fig. 1 shows an FPGA chip which includes components' according to the present invention.
• Fig. 2A shows a single core tile which populate ⁇ a majority of the FPGA chip illustrated in Fig. 1.
• Fig. 2B shows four adjacent core tiles of the type illustrated in Fig. 2A.
• Fig. 3A illustrates a configurable logic block matrix which is part of the tile of Fig. 2A.
• Fig. 3B illustrates a multiplexer structure which implements all PIPs which connect the output lines of a configurable logic block to one output line.
• Fig. 3C shows one embodiment of a multiplexer structure which drives a configurable logic block input line.
• Fig. 4C illustrates the configurable logic block in the matrix of Fig.
• Fig. 4B illustrates tri-state buffer block 302 of Fig. 3A.
• Fig. 4C illustrates the output enable block 309 of Fig. 3A.
• Fig. 4D show ⁇ a look up table embodiment of the F, G, H and J function generator ⁇ of Fig. 4A.
• Fig. 4E ⁇ how ⁇ another look up table embodiment of the F, G, H and J function generator ⁇ of Fig. 4A.
• Fig. 4F shows one Karnaugh map for the look up table function generator of Fig. 4D or 4E.
• Fig. 4G show ⁇ one of the 2 16 logic function ⁇ which can be implemented by the look up table function generator of Fig. 4D or 4E.
• FIG. 5A-5C illustrate application of the configurable logic block of Fig. 4A to form a carry chain, a cascadable decode circuit, and two 5-input combinational functions, respectively.
• Fig. 6 illustrate ⁇ the programmable routing matrix of Fig. 2A.
• Fig. 7A illustrate ⁇ an example of the connectivity achieved by a programmable routing matrix of the invention such as shown in Fig. 6.
• Fig. 7B illustrates an example of the connectivity achieved by the combination of the programmable routing matrix of Fig. 6 and the tile structure of Fig. 2A or 2B.
• Fig. 8 illustrate ⁇ connection ⁇ from global signal pads near corners of a chip to global signal lines which extend near four edges of the chip and connect to global lines which drive core tiles.
• Fig. 6 illustrate ⁇ the programmable routing matrix of Fig. 2A.
• Fig. 7A illustrate ⁇ an example of the connectivity achieved by a programmable routing matrix of the invention such as shown in Fig. 6.
• Fig. 7B illustrates an
• FIG. 9 illustrates long line splitters which are provided on long lines in one embodiment of the invention.
• Figs. 10A-10D illustrate, respectively, left, top, right, and bottom edge tiles according to one embodiment of the invention.
• Fig ⁇ . 11A-11D illustrate upper left, upper right, lower right, and lower left corner tiles for the same embodiment.
• Fig. 12 illustrated a logic diagram for one embodiment of the oscillator structure used in Fig. 11B.
• a ⁇ mall solid black dot at the intersection ⁇ of two lines indicates a permanent electrical connection between the cros ⁇ ing lines.
• An open circle enclosing an intersection between two lines indicates a programmable connection between the lines (for example, a pass transistor which is turned on to make the connection) .
• Open circles represent bidirectional signal flow between the two lines.
• An open triangle at an intersection of two lines indicates a programmable connection with signal flow going onto the line pointed to by the apex of the triangle. (The signal is of course then present on the full length of the line.
• programmable connections are provided by using programmable interconnection points (PIPs), wherein each PIP includes at lea ⁇ t one transistor.
• PIPs programmable interconnection points
• a triangle on a line which is not intersected by another line indicates a buffer which produces signal flow in the direction indicated by the apex of the triangle.
• ENOUT and ENLL illustrated in Fig. 3A
• a line which ends within the tile or matrix structure i.e. does not extend to the border of a tile or matrix
• FIG. 1 shows an FPGA chip 100 according to the present invention. ' In the center portion of chip 100 are a plurality of identical core tiles 101, which are interconnected by conductive lines (described in detail below) . Along the four edges of chip 100 are west, north, east, and south edge tiles 103, 104, 105, 106, respectively.
• Chip 100 includes pads, i.e. pads P1-P56, for connecting edge tiles 103, 104, 105, 106, and corner tiles 113-116 to external pins of a package (which holds chip 100) .
• pads P1-P56 for connecting edge tiles 103, 104, 105, 106, and corner tiles 113-116 to external pins of a package (which holds chip 100) .
• each edge tile is further connected to a core tile 101.
• edge tiles are connected to different numbers of pads P, typically from zero to four pads (explained in detail in reference to Fig ⁇ . lOa-lOd) .
• Fig. 1 al ⁇ o illu ⁇ trate ⁇ high voltage source pads VCC and low voltage source pads GND.
• FIG. 2A shows a core tile 101.
• Core tile 101 includes a programmable routing matrix 201 and a configurable logic block matrix 202.
• Extending to the west from programmable routing matrix 201 are twelve lines with suffixes 0 through 11. These include single length west lines W1-W5, W7-W11, and double length west lines DW0 and DW6 (described in detail below) .
• Extending to the north from programmable routing matrix 201 are single length north lines N1-N5, N7-N11 and double length north lines DN0 and DN6. Extending to the east are single length east lines E1-E5 and E7-E11 and double length east lines DEO and DE6. Extending to the south are single length south lines S1-S5 and S7-S11 and double length south lines DSO and DS6. Extending east to west acros ⁇ tile 101 are double length horizontal line ⁇ DH0 and DH6. Extending north to ⁇ outh across tile 101 are double length vertical lines DV0 and DV6. Fig.
• FIG. 2B shows four adjacent core tiles 101a, 101b, 101c and lOld having a configuration identical to tile 101 illustrated in Fig. 2A. For clarity in Fig. 2B, most lines are not labeled. As mentioned previously, lines extending to the edges of tile 101 connect to lines in adjacent tiles. For example, single length west line Wlb in tile 101b extending to the west from programmable routing matrix 201b connects to single length east line Ela in adjacent tile 101a. Double length horizontal line DH6a of tile 101a is coupled to double length west line DW6b of tile 101b, and is further coupled to a double length ea ⁇ t line DE6 of a tile not ⁇ hown in Fig.
• Fig. 2B also illustrates that horizontal global lines GH0 and GH1 and vertical global line ⁇ GVO and GVl extend continuou ⁇ ly from one tile 101 to the next.
• the ⁇ e global lines may be connected to a common line at the edge of the tile ⁇ o that a signal on a global line such a ⁇ GHO extends through all tiles.
• configurable logic block (CLB) matrix 202 is connected to the CLB matrix in the west tile (not shown) by output lines Q0-Q3 and input lines QW0-QW3, to the CLB matrix in the north tile (not shown) by output lines Q0-Q3 and input lines QN0-QN3, to the CLB matrix in the east by output lines Q0-Q3 and input lines QE0-QE3, and to the CLB matrix in the south tile (not shown) by output lines Q0-Q3 and input lines QS0-QS3.
• output lines Q0-Q3 carry the ⁇ ame signal ⁇ from CLB matrix 202 to adjacent tiles in four directions and thus have the same name ⁇ .
• Carry-in line CIN and carry-out line COUT which extend vertically in tile 101, connect to carry-out and carry-in lines, respectively, in adjacent tiles to form a fast carry path for arithmetic functions, as di ⁇ cu ⁇ sed in detail in U.S. Patent No. 5,349,250, "LOGIC STRUCTURE AND CIRCUIT FOR FAST CARRY", which is incorporated herein by reference.
• Configurable Lo ⁇ ic Block Matrix 202 Fig. 3A illustrate ⁇ configurable logic block (CLB) matrix 202 of Fig. 2a.
• CLB matrix 202 includes a CLB 301, a tristate buffer block 302, an input interconnect ⁇ tructure 303, a CLB output interconnect ⁇ tructure 304, a feedback interconnect ⁇ tructure 305, a general input interconnect ⁇ tructure 306, a register control interconnect structure 307, an output interconnect structure 308, and an output enable block 309.
• Sparse Pioulation Programmable connections are provided by using programmable interconnection points (PIPs) , wherein each PIP includes at least one transistor. As is well known in the art, each transistor occupie ⁇ valuable space on the chip substrate. Thus, in accordance with the present invention and referring to Fig. 3A, a majority of the horizontal and vertical lines in input interconnect structure 303, feedback interconnect structure 305, general input interconnect structure 306, and register control interconnect structure 307 are not programmably connectable. In other words, these structure ⁇ are ⁇ parsely populated with PIPs, or are spar ⁇ ely "pipulated” . Spar ⁇ e pipulation minimize ⁇ chip area u ⁇ ed by PIPs, thereby maximizing density of the entire chip.
• PIPs programmable interconnection points
• PIPs are positioned to allow connection from each output line Q0-Q3 from CLB output interconnect structure 304 to one of the function generators F, G, H, or J of an adjacent tile in each of the four compas ⁇ direction ⁇ .
• general input interconnect structure 306 provides four to six PIPs for each CLB input line (J0-J3, JB, H0-H3, HB, G0-G3, GB, F0-F3 and FB) to CLB 301.
• Feedback interconnect structure 305 provides direct connections from two of output lines Q0-Q3 to one of the function generator input terminals in CLB 301.
• 24 PIPs in output interconnect structure 308 connect output lines Q0-Q7 to tile interconnect lines M0-M23.
• signals on tile interconnect lines M0-M23 are selectively transferred between CLB 301 and programmable routing matrix 201 (via CLB output interconnect structure 304, general input interconnect structure 306, and output interconnect structure 308) .
• less than one intersection in eight is provided with a PIP, thereby minimizing silicon area. Yet, connectivity from any output line to any input line is ensured by the PIPs provided.
• CLB 301 A configurable logic block (CLB) 301 is illustrated in Fig. 4A.
• CLB 301 includes four function generators F, G, H, and J, wherein each function generator comprises a 16-bit look up table that generates an output signal determined by the four input signal ⁇ provided to the function generator and the value ⁇ stored in the look up table.
• function generator F generates an output signal determined by the input signal ⁇ provided on line ⁇ F0-F3
• function generator G generate ⁇ an output ⁇ ignal determined by the signals provided on CLB input lines G0-G3
• function generator H generates an output signal determined by the signals provided on CLB input lines H0-H3
• function generator J generates an output signal determined by the signals provided on CLB input lines J0-J3.
• Fig. 4D illu ⁇ trate ⁇ a look up table, in this embodiment a 16-bit RAM, which provides an output signal in response to any one of sixteen possible combinations of four input signals.
• input signals A and B control the X decoder to select any one of the four columns in the 16-bit RAM.
• input signals C and D control the Y decoder to select any one of the four rows in the 16-bit RAM.
• a particular bit stored in a particular one of the ⁇ ixteen locations in the 16 Select Bits register is transmitted to the output lead OUT.
• the signal A, B, C, D is applied to the leads so labeled.
• this regi ⁇ ter configuration also provides any one of 216 logic functions.
• the memory bits in look up tables F, G, H and J are typically loaded during configuration of the chip, for example through a shift register, or alternatively by an addres ⁇ ing means.
• the memory bit ⁇ are also loaded during operation of the chip, thereby reconfiguring the chip on the fly.
• a reconfigurable memory structure is discu ⁇ ed in commonly a ⁇ igned, U. S. Patent No. 5,343,406 invented by Freeman et al.
• Function generators F, G, H, and J provide output signals on CLB output lines X, Y, Z, and V, respectively. These output ⁇ ignal ⁇ from function generator ⁇ F, G, H, and J control multiplexer ⁇ Cl, C2, C3, and C4, thereby providing a cumulative carry-out function COUT.
• Multiplexer Cl receive ⁇ a carry-in ⁇ ignal on line CIN and an input ⁇ ignal on line FB, and generate ⁇ an output ⁇ ignal on line CF.
• Multiplexer C2 receive ⁇ the ⁇ ignal on line CF and an input ⁇ ignal on line GB, and generate ⁇ an output ⁇ ignal on line CG.
• Multiplexers C3 and C4 are connected in the same manner a ⁇ Multiplexer ⁇ Cl and C2.
• Multiplexer C4 provide ⁇ an output signal on line COUT from CLB 301.
• each CLB 301 includes four storage devices RX, RY, RZ, and RV.
• These storage devices RX, RY, RZ, and RV each comprise flip flops with master and slave stages and an output multiplexer which takes outputs from the master and slave stages as inputs.
• devices RX, RY, RZ, and RV can be configured by the multiplexer to serve a ⁇ either flip flop ⁇ or as latches.
• periodic repowering of the carry signal is nece ⁇ ary.
• a repowering buffer comprising inverters 1121 and 1122 is positioned every four multiplexers in the carry path, or once every CLB 301.
• a repowering buffer is provided every two multiplexer ⁇ in the carry path, thus two repowering buffers are provided in every CLB 301.
• CLB 301 includes five input lines per function generator. For example, referring to function generator F, CLB input line ⁇ F0-F3 provide input ⁇ ignal ⁇ to function generator F, and a fifth CLB input line FB provides a multiplexer control input signal.
• Function generators G, H, and J are configured in a similar manner.
• Three input lines CLK, CE, and RST provide clock, clock enable, and re ⁇ et ⁇ ignal ⁇ , re ⁇ pectively, to regi ⁇ ter ⁇ RX, RY, RZ, and RV. A ⁇ shown in Fig.
• the three output signals include: «a direct, unregistered output signal from the function generator (provided on CLB output lines X, Y, Z, or V) , »an alternative, unregi ⁇ tered output ⁇ ignal which may be derived from one of the CLB input ⁇ ignals, a signal from the carry chain, or in two ca ⁇ e ⁇ a ⁇ ignal from a multiplexer which provide ⁇ an output ⁇ ignal of a five- input function (provided on CLB output line ⁇ XB, YB, ZB, or VB) , and »a registered, output signal which may be loaded by the function generator or by one of the sources of the alternative output signal (provided on CLB output lines XQ, YQ, ZQ, or VQ) .
• CLB output line X receives a direct unregi ⁇ tered output signal from function generator F.
• CLB output line XB receives either the signal on CLB input line FB or the output signal of multiplexer SI (as determined by multiplexer Bl) , which in turn i ⁇ derived from either the carry-out ⁇ ignal CF or the five-input function-generator output signal from multiplexer FG (see discussion of Fig. 5C below) .
• CLB output line XQ receives the regi ⁇ tered output signal from register RX, which derives its D input signal either directly from function generator F (the signal on output line X) or the alternative output signal on line XB as determined by multiplexer DI.
• output line K provide ⁇ a constant signal, which may be high or low, as selected by multiplexer PG.
• multiplexers D1-D4 selectively provide either the output signals from function generators F, G, H, and J (the same signals on CLB output lines X-V) or the output ⁇ ignal ⁇ from multiplexer ⁇ B1-B4 to registers RX-RV, re ⁇ pectively.
• multiplexer ⁇ SI and S3 are set to forward the carry signal ⁇ of multiplexer ⁇ Cl and C3 , re ⁇ pectively, then multiplexer ⁇ B1-B4 ⁇ elect between the input signals on CLB input lines FB-JB, respectively, and the output signals of multiplexers C1-C4.
• Multiplexers C1-C4 in addition to being used for the carry function in an arithmetic operation, al ⁇ o generate wide AND and OR functions.
• a logic 0 is placed on line FB to program multiplexer Cl to generate an AND function of the F function generator output signal on CLB output line X and the carry-in signal on line CIN.
• a logic 1 is placed on CLB input line FB to program- multiplexer Cl to generate an OR function of the complement of the output signal on CLB output line X and the carry-in signal on line CIN.
• the OR function is achieved by loading the inverse values into the truth table. The function of multiplexers C1-C4 and their interaction with the logic block are further discussed in application serial no. 08/116,659 [M-2565] incorporated by reference.
• Example Applications of CLB 301 Figs. 5A-5C illustrate applications using CLB 301 (described in detail in reference to Fig. 4A) to form a carry chain, a cascadable decode circuit and 2 five-input functions, respectively.
• the ⁇ e figures use heavy lines to illustrate lines of CLB 301 which are used for the particular selected function and thin dashed lines to indicate lines and elements not used for the particular function.
• CLB 301 is configured to compute a half sum H3H2H1H0 (where H3, H2, Hi, and HO are the four bits of a four-bit half-sum) and the carry bit ⁇ C3C2C1C0 of two numbers A3A2A1A0 and B3B2B1B0.
• CLB (not shown), preferably po ⁇ itioned in the tile to the right or left of the one shown, will be used to complete the sum.
• Operands A3 and B3 are placed on any two of CLB input lines J0-J3.
• Operands A2 and B2 are placed on any two of CLB input lines H0-H3.
• Al and BI are placed on any two of CLB input lines G0-G3.
• A0 and B0 are placed on any two of CLB input lines F0-F3.
• Unused line ⁇ are either held high or held low.
• Each of function generator ⁇ F, G, H, and J is loaded with the truth table of the XOR function (which is the half sum of its input signals) .
• the truth table takes into account the values applied to unused input line ⁇ .
• Multiplexers Cl, C2, C3, and C4 are controlled by the output signals of function generators F, G, H and J, respectively. Specifically, if the function generator output signal is a logic 1 ( ⁇ ignal ⁇ A and B are not equal) , the carry-in value i ⁇ forwarded to the carry-out of that bit, and if the function generator output signal is a logic 0 (signals A and B are equal), the value of signal A or signal B is forwarded to the carry-out of that bit.
• Multiplexers B1-B4, SI and S3 are controlled to forward the carry-out of each bit to the "B" CLB output line (i.e.
• CLB output lines XB, YB, ZB, and VB CLB output lines XB, YB, ZB, and VB) of that bit.
• the function generator output signal for each bit (on CLB output lines X, Y, Z, and V) is provided as the half sum output for that bit.
• CLB 301 is configured to operate as a cascadable decoder. A 16-bit addres ⁇ repre ⁇ ented by ⁇ ignals A0-A15, i ⁇ placed on CLB input lines F0-F3, G0-G3, and J0-J3. CLB input lines FB, GB, HB, and JB are grounded.
• each of function generator ⁇ F, G, H, and J include a ⁇ ingle logic 1 to reflect a portion of a predetermined addre ⁇ .
• CLB 301 is configured to generate two functions of five input signal ⁇ each.
• Function generator ⁇ F and G generate a fir ⁇ t function of five input ⁇ ignals on CLB output line XB and function generators H and J generate a second function of five input signals on CLB output line ZB.
• For the first function four input signal ⁇ A0-A3 are provided on the CLB input lines to both function generators F and G and the fifth input signal A4 is provided to line FB.
• Input signal A4 causes multiplexer FG to select the output signal of function generator F or function generator G.
• multiplexer SI is programmed by its memory cell to select the output signal of multiplexer FG, and multiplexer Bl i ⁇ programmed by its memory cell to select the output signal of multiplexer SI.
• the five-input function output ⁇ ignal from function generators F and G is provided on CLB output line XB.
• the function of the five input signals- B0-B4 provided to function generators H and J is generated on CLB output line ZB.
• Loading the appropriate truth tables into the two as ⁇ ociated function generators F and G produces the desired function of five input signals.
• a 32-bit look up table is stored in function generators F and G (i.e. two 16-bit look up table ⁇ ) .
• Tri ⁇ tate Buffer 302 Fig 4B illustrates a schematic drawing of tri-state buffer block 302 (Fig. 3A) which includes tristate buffers B4- B7. Note that the line names are identical to those referenced in Fig. 3A.
• Output ⁇ ignals from AND gates A4-A7 control tristate buffers B4-B7, respectively. If AND gate A5, for example, provides a logic 0 output signal, buffer B5 is enabled and provide ⁇ a buffered output signal on line TQ5 which matches its corre ⁇ ponding input signal on line Q5. On the other hand, if AND gate A5 provides a logic 1 output signal, buffer B5 is disabled and provides a high impedance at the output terminal.
• the output signal ⁇ provided by AND gates A4-A7 are determined either globally by the output signal from OR gate ORl or individually by memory cells MM4-MM7, respectively. If memory cells MM4-MM7 store logic O' ⁇ , then the output signals of AND gates A4-A7 will also be logic O's regardles ⁇ of the ⁇ ignal from OR gate ORl.
• OR gate ORl provide ⁇ a high output ⁇ ignal if' the ENLL ⁇ ignal i ⁇ low or if the signal on line TS is high. Referring back to Fig. 3A, the signal on tristate line TS is programmably selected from any of tile interconnect lines M16-M23.
• the ENLL signal is a global ⁇ ignal provided to all buffer ⁇ 302 in all tile ⁇ 101.
• Output Enable Block 309 The buffer ⁇ in output enable block 309 are disabled during configuration of the device so that lines driven by these buffers will not experience contention.
• Fig. 4C illustrates the structure of block 309.
• Each buffer in output enable block 309 comprise ⁇ a two-input AND gate. One input of each AND gate is driven by a global enable ⁇ ignal ENOUT. The other input i ⁇ provided by a line Q0'-Q7' which i ⁇ in turn provided by output ⁇ ignal ⁇ from CLB 301 (Fig. 3A) .
• unexpected line ⁇ may be connected to the ⁇ e lines Q0-Q7. Therefore, to prevent contention, the ENOUT signal is held low during configuration so that all output ⁇ ignal ⁇ on line ⁇ Q0-Q7 are low and unexpected connection of other lines does not produce contention because all signal ⁇ have a low value.
• each input line QS0-QS3 is connectable to one of the CLB input lines of one function generator.
• line QS0 is connectable to CLB input line Fl of function generator F
• line QSl is connectable to CLB input line Gl of function generator G
• line QS2 is connectable to CLB input line HI of function generator H
• line QS3 is connectable to CLB input line Jl of function generator J.
• each function generator F, G, H or J is configurable to provide any function based on its input signals, a particular signal can be provided to any input terminal of a function generator and the look up table of that function generator loaded accordingly. Thus, it is not important which input signal is available to which function generator input terminal.
• a signal on input line QW0 drives both CLB input line ⁇ F0 and FB.
• a signal on input line QWl drive ⁇ CLB input lines GO and, GB
• a signal on input line QW2 drives CLB input lines HO and HB
• a signal on input line QW3 drives CLB input lines JO and JB.
• Each signal on input lines QE0, QE1, QE2, and QE3 also drives two CLB input lines.
• a signal on input line QE0 drives CLB input lines Fl and FB
• a signal on input line QE1 drives lines Gl and GB
• a signal on input line QE2 drives lines HI and HB
• a signal on input line QE3 drive ⁇ line ⁇ Jl and JB.
• Signals on input lines QN0-QN3 and QS0-QS3 each drive only one CLB input line.
• a signal on input line QN0 drives CLB input line F0
• a signal on input line QN1 drive ⁇ CLB input line GO
• a ⁇ ignal on line QN2 drives CLB input line HO
• a signal on line QN3 drives CLB input line JO.
• a signal on input line QSO drives CLB input line Fl
• a signal on input line QSl drives CLB input line Gl
• a signal on input line QS2 drives CLB input line HI
• a signal on input line QS3 drives CLB input line Jl.
• This embodiment is particularly desirable for horizontal flow of many signal ⁇ becau ⁇ e each input line QE0-QE3 and QW0-QW3 i ⁇ programmably connected to two CLB input line ⁇ .
• Other embodiments of the present invention, having a different number and positioning of programmable connections, are optimized for a different signal flows.
• Output Matrix 304 CLB 301 provide ⁇ output ⁇ ignal ⁇ on CLB output line ⁇ X, XQ ' , XB, Y, YQ, YB, Z, ZQ, ZB, V, VQ, and VB.
• CLB 301 al ⁇ o deter ine ⁇ whether it provide ⁇ the signal on carry out line COUT or whether the signal on carry in line CIN is transferred to the next CLB in the tile above.
• PIPs on CLB output lines X, XQ, XB, Y, YQ, YB, Z, ZQ, ZB, V, VQ, VB, and K are selectively programmed to drive any number of output lines Q0-Q7 through a CLB interconnect structure 304.
• CLB interconnect structure 304 is fully pipulated (i.e., any of the 13 output ⁇ ignal ⁇ of CLB 301, excluding the ⁇ ignal on carry out line COUT, can drive any of output line ⁇ Q0-Q7) .
• interconnect structure 304 also buffer ⁇ it ⁇ output ⁇ ignals for driving further lines.
• Full pipulation of interconnect ⁇ tructure 304 requires 108 (13 x 8) PIPs.
• structures 303, 305, 306, and 307 in combination use 200 PIPs, even though they are spar ⁇ ely pipulated.
• PIP ⁇ are provided (a ⁇ di ⁇ cu ⁇ ed above) for connecting input line QWO to CLB input line ⁇ F0 and FB of CLB 301. Thu ⁇ , in this manner, a path is establi ⁇ hed from the output line ⁇ of CLB 301 in CLB matrix 202c to the input lines of CLB 301 in CLB matrix 202d using only two PIPs, which in one embodiment includes two transistors.
• a PIP in CLB output interconnect structure 304 requires a signal on a CLB output line to propagate through two transi ⁇ tor ⁇ (note that signal K, a constant power or ground ⁇ ignal, propagates through four tran ⁇ i ⁇ tors) .
• FIG. 3B illustrates a multiplexer structure 400 which implements all PIPs which connect the twelve CLB output lines (X, XQ, XB, Y, YQ, YB, Z, ZQ, ZB, V, VQ, VB) of CLB 301 and one power/ground output signal line K to output line Q0.
• Multiplexer structure 400 includes memory cells 31, 32, and 33 which control a first bank of twelve transi ⁇ tors 351 and select signal K if no transi ⁇ tor in bank 351 i ⁇ selected.
• a logic 1 stored in one of memory cells 31, 32, and 33 selects one signal from each group of three signal ⁇ in bank 351. If all memory cell ⁇ 31, 32, and 33 store a logic 0, then signal K is provided to node 30.
• memory cell ⁇ 34 and 35 control AND gate ⁇ AND1-AND4 to select the output signal from one of output lines VQ, ZQ, YQ, and XQ and to provide the selected signal on output line Q0. If ' memory cells 31, 32, and 33 store a logic 0, thereby selecting signal K, then memory cells 34 and 35 must be programmed to provide the signal at node 30.
• thirteen PIPs are implemented using only 5 memory cell ⁇ and sixteen transistors, each path requiring only two transistors for all signals except the con ⁇ tant value K, which travel ⁇ a longer path. The signal on line K i ⁇ not harmed by having a longer ⁇ ignal path since it is not a switching signal.
• a multiplexer structure 400 which ⁇ elect ⁇ one of thirteen output ⁇ ignals of CLB 301 to drive a predetermined output line, is provided for each of output lines Q0-Q7. Note that although it is po ⁇ ible for none of the thirteen output signals to drive an output line Q0-Q7, multiplexer structure 400 cannot select more than one of the thirteen output signals. In this manner, contention on output lines Q0-Q7 is avoided.
• thirteen memory cell ⁇ are provided, each memory cell controlling a single transi ⁇ tor. In thi ⁇ manner, each path require ⁇ only one tran ⁇ i ⁇ tor, thereby increa ⁇ ing signal speed. However, note that this embodiment increa ⁇ e ⁇ silicon area.
• Feedback Interconnect Structure 305 selectively connects output lines Q0-Q3 to CLB input lines F2, G2, H2, and J2 within configurable logic block matrix 202.
• any output signal from CLB 301 can be fed back to selected CLB input lines of any function generator F, G, H and J in CLB 301.
• Feedback interconnect structure 305 provides a PIP pattern that supports a counter (a counter feeds back its own signal) or a shift register (a shift register requires its neighbor' ⁇ ⁇ ignal) .
• the above-de ⁇ cribed PIP pattern prevents contention between ⁇ ignal ⁇ on CLB input line ⁇ F2, G2, H2 and J2 and ⁇ ignals on CLB input line ⁇ F0, GO, HO, JO, Fl, Gl, Hi, and Jl which are provided on other input lines to CLB matrix 202, such a ⁇ input line ⁇ QWO and QN3.
• Other embodiments of the present invention provide different combinations of PIPs in feedback interconnect structure 305. •
• General input matrix 306 receive ⁇ input ⁇ ignal ⁇ on tile interconnect lines M0-M23 and includes PIPs for placing these input signals onto CLB input lines F0-F3, FB, G0-G3, GB, HO- H3, HB, J0-J3, and JB.
• PIPs for placing these input signals onto CLB input lines F0-F3, FB, G0-G3, GB, HO- H3, HB, J0-J3, and JB.
• a PIP pattern allows a signal on any tile interconnect line M0-M23 in general input interconnect structure 306 to drive one input line of each function generator F, G, H, and J. Because function generator input signals are interchangeable, (Lookup table inputs are interchangeable.) no tile interconnect line M0-M23 need be coupled to more that one input line of a function generator.
• a multiplexer structure 401 using only three memory cells 36, 37 and 38, selects one of eight pos ⁇ ible ⁇ ignal ⁇ to control a first bank of transi ⁇ tor ⁇ 361. Specifically, memory cell 38 ⁇ elect ⁇ one each of the paired ⁇ ignal ⁇ on input line ⁇ QWO or QN0, M15 or M14, M9 or M8, and M7 or M6.
• Memory cell ⁇ 36 and 37 provide ⁇ ignals to the input terminals of AND gates AND5-AND8, which in turn control a second bank of transi ⁇ tors 362 to select a single ⁇ ignal to place on CLB input line F0.
• the pattern of PIPs also provides a function of five inputs (discussed above in connection with Fig. 5C) .
• five-input function ⁇ are easily implemented with the PIP pattern provided.
• PIPs allow connection from long horizontal lines LH0-LH7 and long vertical lines LV0-LV7, as well as global (horizontal and vertical) lines GHO, GH1, GVO, and GVl to register ⁇ RV, RZ, RY, and RX without going through function generators J, H, G, and F.
• long horizontal lines LH0-LH7 and long vertical lines LVO and LV7 as well as global horizontal lines GHO, GHl and global vertical lines GVO, GVl are selectively coupled to tile interconnect lines M0-M23 (Fig. 6) .
• tile interconnect lines if coupled to CLB input lines FB, GB, HB and JB, bypass function generators F, G, H and J, respectively, and provide signals (via intermediate multiplexers) to register ⁇ RX, RY, RZ, RV, re ⁇ pectively (Fig. 3A) .
• global lines GHO, GHl, GVO, and GVl are also selectively coupled to registers RX, RY, RZ and RV via register control interconnect structure 307. Allowing all tile interconnect line ⁇ M0-M23 to connect to one CLB input line FB, GB, HB or JB and providing connection ⁇ from every long line to one tile interconnect line M0-M23 (di ⁇ cu ⁇ sed below in connection with Fig.
• output lines Q4-Q7 also provide output signals to programmable interconnect matrix 201 (Fig. 2A) via tile interconnect lines M0-M11 or via lines TQ4-TQ7.
• Output lines Q0-Q3 also provide output signals to selected ones of tile interconnect lines M12-M23.
• output interconnect structure 308 allows signals on each output line Q0-Q7 to drive up to three tile interconnect lines M0-M23.
• the full pipulation of CLB output interconnect structure 304 allows any utput line of CLB 301 to be connected to any tile interconnect line M0-M23.
• general input interconnect structure 306 also provides selected feedback signals on output lines Q0-Q3 to CLB 301.
• Clock line CLK, clock enable line CE, reset line RST and tristate line TS may be driven by signal ⁇ provided on ⁇ elected tile interconnect line ⁇ M0-M23 (from programmable routing matrix 201) .
• clock line CLK is driven directly by signal ⁇ on global horizontal line ⁇ GHO and GHl or from global vertical line ⁇ GVO and GVl.
• contention is avoided either by using a convenient decode method for selecting which PIP on a single input line is turned on or by u ⁇ ing rule ⁇ provided in the ⁇ oftware which program ⁇ the memory cell ⁇ to avoid turning on more than one PIP on an input line.
• alternative input selection means are possible. For example, in one embodiment one memory cell is loaded to specify whether each PIP is turned on or not.
• Fig. 6 illustrate ⁇ the programmable routing matrix 201 of Fig. 2a. Note that wherea ⁇ all PIP ⁇ in CLB matrix 202 are shown as triangles to indicate signal flow onto one line, in Fig. 6, most PIPs in programmable routing matrix 201 are shown a ⁇ open circle ⁇ to indicate ⁇ ignal flow on both line ⁇ . The exception ⁇ are PIP ⁇ which connect line ⁇ TQ4 through TQ7 (output line ⁇ from tri ⁇ tate buffer block 302 of Fig.
• programmable routing matrix 201 extends into programmable routing matrix 201 to long horizontal line ⁇ LH0-LH7 and long vertical line ⁇ LV0-LV7, and PIP ⁇ which place ⁇ ignal ⁇ from global signal lines GHO, GHl, GVO, and GVl onto tile interconnect lines M0 through M3.
• Extending into programmable routing matrix 201 are global lines, long lines, double length lines, and ⁇ ingle length line ⁇ . Each of the ⁇ e line ⁇ i ⁇ connectable to ⁇ elected tile interconnect line ⁇ M0-M23.
• Programmable routing matrix 201 provide ⁇ connection to programmable routing matrices in adjacent tiles through single length lines extending in the four compas ⁇ directions, i.e.
• programmable routing matrix 201 which in thi ⁇ embodiment include ⁇ only 124 PIPs, is sparse relative to the approximately 4200 PIP ⁇ which could be provided to connect every line in Fig. 6 to every other line.
• the PIP pattern en ⁇ ure ⁇ that any line i ⁇ connectable to any other line if enough intermediate PIPs are used.
• west line Wl is connectable to east line El by turning on two PIPs which connect tile interconnect line Ml to these two lines.
• to make a connection between west line Wl and ea ⁇ t line E2 require ⁇ 8 PIP ⁇ and 9 lines, i.e.
• tile interconnect line M6 connects to double length lines DN6, DS6, DE6, and DW6.
• Tile interconnect lines M7 through Mil connect to correspondingly numbered single length lines extending north, south, ea ⁇ t and we ⁇ t.
• PIPs on tile interconnect line ⁇ M12-M23 implement a pattern of cross connecting that facilitates signal transfer flexibility with minimal sacrifice of speed, and the spar ⁇ e pipulation achieve ⁇ valuable reduction of chip area.
• tile interconnect line M12 connect ⁇ to double length north line DNO, to south line S3, to east line E5, and to west line Wl
• tile interconnect line M15 connects to north line N3, east line E8, double south line DS6, and west line W4.
• the present invention provides a predetermined pattern to minimize the number of PIPs, thereby allowing any line to be connected to any other line.
• the present invention ensure ⁇ that a path is always provided, while minimizing silicon area.
• each tile interconnect line M0-M23 is connectable to five or six other lines.
• each tile interconnect line M0-M23 is represented as a ⁇ tar with five or ⁇ ix points.
• eight tile interconnect lines MO through M7 are programmably connectable to selected one ⁇ of north lines N0-N3, ea ⁇ t line ⁇ E0-E3, ⁇ outh line ⁇ S0-S3 and we ⁇ t line ⁇ W0-W3.
• Tile interconnect line ⁇ MO through M3 are connectable to north, south, east and west lines of the same numerical suffix.
• Tile interconnect line ⁇ M4 through M7 are connectable to ⁇ taggered ones of the north, south, ea ⁇ t and west lines.
• tile interconnect lines M0-M3 provide a means for interconnecting north, east,- south and we ⁇ t lines of the same suffix, while tile interconnect lines M4-M7 provide an opportunity for cross-connecting lines from four compass directions.
• tile interconnect line ⁇ M0-M7 provide means for connecting programmable routing matrix 201 to configurable logic block matrix structure 202 (Fig. 3A) .
• each CLB 301 is as ⁇ ociated with a particular ⁇ tar 201 (i.e the programmable routing matrix 201) from which radiate line ⁇ connecting to other ⁇ tar ⁇ 201 and from there to other CLB ⁇ 301.
• ⁇ tar 201 i.e the programmable routing matrix 201
• Fig. 7B double length and ⁇ ingle length line ⁇ are illustrated.
• lines of other lengths are provided in the ⁇ tar structure.
• Global Interconnect Structure Fig. 8 illu ⁇ trate ⁇ hard connections from global signal pad ⁇ P113, P114, P115, and P116, which are po ⁇ itioned near the corner ⁇ of chip 100 (Fig. 1) , to global signal lines GTL, GTR, GBR, and GBL, respectively, which are typically located near the four edges of chip 100.
• Each global ⁇ ignal line is programmably connectable to a plurality of lines extending vertically or horizontally through each row or column of core tiles 101.
• top left global signal line GTL is connectable to global vertical lines GVl-a through GVl-n, via PIPs PVl-a through PVl-n, respectively, i.e. one PIP for each column of core tiles 101.
• Top right global signal line GTR is connectable via PIPs PHO-a through PHO-m, respectively, i.e. one PIP for each row of core tile ⁇ 101 to global horizontal lines GHO-a.
• Bottom right global signal line GBR i ⁇ connectable to global vertical line ⁇ GVO-a through GVO-n.
• bottom left global signal line GBL is connectable to global horizontal lines GHl-a through GHl-m.
• the global vertical and horizontal lines with reference labels beginning with GV or GH are connectable to programmable routing matrices 201 and CLB matrices 202 in core tiles 101 through which the global lines pass, as discussed above in connection with Figs. 2A, 3, and 7. As also shown in Fig.
• long lines LV0L, LV7L, LH0T, LH7T, LVOR, LV7R, LHOB, and LH7B which extend through the edge tiles (not shown in Fig. 8 for simplicity but shown in Figs. 10A through 10D) of chip 100 (Fig. 1) are also connectable to the global lines.
• bottom right global ⁇ ignal line GBR can be driven by ⁇ ignal ⁇ on bottom horizontal long line ⁇ LHOB and LH7B via PIPs PGBR0 and PGBR7, respectively.
• Bottom left global signal line GBL can be driven by signals on left vertical long lines LV0L and LV7L via bottom left buffer BBL via PIP ⁇ PGBL0 and PGBL7, re ⁇ pectively.
• Equivalent connection ⁇ are provided for the top and right edge ⁇ of the chip.
• Left, top, right, and bottom long line ⁇ are connectable to each other through PIP ⁇ , such as PIP PBR7.
• PIP ⁇ such as PIP PBR7.
• long line ⁇ LVOL, LV7L, etc. are driven by signals provided by any of the pads at the perimeter of the chip (through edge tiles 103-106 discussed below in connection with Figs. 10A-10D) , any pad can provide a global signal.
• any of core tiles 101 can also provide a global signal through edge tiles 103- 106.
• Figs. 1 and 9 illustrate one embodiment of the pre ⁇ ent invention which includes long line splitters LLS which may be po ⁇ itioned partly through a line.
• Two columns of tiles are illustrated in Fig. 9, each column comprising a top edge tile 104, six core tiles 101, and a bottom edge tile 106.
• Long vertical lines LV0-LV7 traverse all core tiles 101, and in each of the two columns terminate in edge tile ⁇ 104 and 106.
• Long vertical line ⁇ LV0-LV7 are al ⁇ o connectable to ⁇ elected one ⁇ of tile interconnect line ⁇ M0-M15 and line ⁇ TQ0-TQ3 in edge tile ⁇ 104 and 106, a ⁇ will be discussed below in connection with Figs. 10A-10D.
• long line ⁇ LV0-LV7 are connectable to ⁇ elected line ⁇ in programmable routing matrice ⁇ 201.
• horizontal long line ⁇ LH0-LH7 are not illu ⁇ trated in Fig. 9, but are illu ⁇ trated in Figs. 2A and 6.
• vertical long lines LV0-LV7 in the three upper core tiles 101 are separated from the portions in the three lower core tiles 101 by long line splitter ⁇ LLS.
• a long ⁇ plitter LLS in one embodiment comprises an n-type tran ⁇ i ⁇ tor which i ⁇ turned off by providing a low voltage to a control gate CG, thereby separating the vertical long line into top and bottom segments.
• Long line splitter ⁇ LLS are typically u ⁇ ed in large chip embodiment ⁇ to allow top and bottom long line ⁇ to be separately driven in different portions of the chip.
• horizontal long lines LH0-LH7 are also separated in the middle of chip 100 by long line ⁇ plitter ⁇ LLS.
• ⁇ everal long line ⁇ plitters such as long line splitter ⁇ LLS and LLSA are provided along the ⁇ ame long line, or long line splitters LLSB are provided between an end of a long lines in one edge tile and an end of a long line in an adjacent edge tile, thereby programmably connecting the ⁇ e long line ⁇ .
• FIG. 10A-10D illu ⁇ trate in greater detail the edge tiles shown in Fig. 2A.
• Figs. 10A-10D show left edge tile 103, top edge tile 104, right edge tile 105, and bottom edge tile 106, respectively.
• Each edge tile in these embodiment ⁇ i ⁇ typically but not always connected to at least one of pads PV, PZ, PY or PX. In other embodiments described in detail below in reference to Fig. 1, at least one edge tile is not connected to any pad.
• Fig. 10A-10D show left edge tile 103, top edge tile 104, right edge tile 105, and bottom edge tile 106, respectively.
• Each edge tile in these embodiment ⁇ i ⁇ typically but not always connected to at least one of pads PV, PZ, PY or PX. In other embodiments described in detail below in reference to Fig. 1, at least one edge tile is not connected to any pad.
• Fig. 10A-10D show left edge tile 103, top edge tile 104, right edge tile 105, and bottom edge
• I/O devices IOBV, IOBZ, IOBY and IOBX are connected to edge tile 103 via input/output (I/O) devices IOBV, IOBZ, IOBY and IOBX, respectively.
• I/O devices IOBV, IOBZ, IOBY and IOBX are connected to edge tile 103 by three line .
• I/O device IOBV i ⁇ connected to edge tile 106 by an I/O input line IV, an I/O output line OV, and a tri- ⁇ tate line TSV.
• the output signal provided to pad P42 by output line OV is controlled by a signal on I/O tri-state line TSV. Similar lines are provided for I/O devices IOBZ, IOBY and IOBX.
• a fully pipulated I/O input interconnect structure 1001 allows signal ⁇ on I/O input lines IV, IZ, IY, and IX to drive edge tile input lines QIN0-QIN3.
• Neighbor output interconnect structure 1004 allows signal ⁇ on output lines QE0-QE3 from a core tile 101 to be provided to pads PV, PZ, PY and PX.
• I/O output interconnect structure 1002 allows signals from the neighboring core tile ⁇ (in edge tile 103, provided by north lines 100-N7, south lines S0-S7, and east line ⁇ E1-E5 and E7- Ell) a ⁇ well a ⁇ signals on long lines LH0-LH7 and LV0-LV7 and double length lines DHO, DH6, to be provided to the pad ⁇ .
• I/O output interconnect ⁇ tructure 1002 ha ⁇ a ⁇ ub ⁇ tantially complete pipulation, thereby allowing any ⁇ ignal coming into left edge tile 103 from el ⁇ ewhere in the chip interior to be placed on any of pads PV, PX, PY or PZ in spite of a sparse general interconnect structure 1006 between lines coming from other parts of the chip interior into or out of left edge tile 103 and a set of edge tile interconnect lines M0-M15.
• Intermediate interconnect structure 1003 allows signal ⁇ which come from one of tile interconnect line ⁇ M0-M15 to be placed on one of edge tile input lines QIN0-QIN3, buffered onto a corresponding output line Q0 through Q3, and provided through tristate buffer block 302 to a corresponding line TQ0- TQ3.
• a signal can thence be provided to horizontal long line ⁇ LH0-LH7 and vertical long line ⁇ LV0-LV7.
• Feedback interconnect ⁇ tructure 1005 allow ⁇ signals on output lines Q0-Q3 to drive tile interconnect lines M0-Mi5 which are in turn selectively connected to north lines N0-N7, south lines S0-S7, east lines El-Ell, -double length lines DEO, DE6, DH0, and DH6 and to long lines LV0-LV7.
• edge tile 103 allow ⁇ connection to pad ⁇ which in turn have external connection ⁇ to chip 100, as well a ⁇ on an adjacent core tile 101 chip and to adjacent edge tile ⁇ (or an adjacent corner tile, explained in detail below) .
• Fig ⁇ . 10B, 10C, and 10D ⁇ how embodiment ⁇ of edge tile ⁇ 104, 105, and 106, respectively. Because these tiles are similar in structure, except for orientation, and have identical numerical references to that shown in Fig. 10A, the detail of the interface structure ⁇ in Fig ⁇ . 10B, 10C, and 10D will not be di ⁇ cu ⁇ sed herein.
• Optional Pad Fig. 10C illustrate ⁇ a combination of connected and unconnected pad ⁇ , thereby illu ⁇ trating the flexibility available at the ma ⁇ k level.
• one unconnected pad PZ and connected pads PV, PY, PX implement a configuration which i ⁇ repre ⁇ ented in Fig. 1 by pads P6, P7 and P8 (connected to edge tile 105) .
• each edge tile has a predetermined number of pads connected to it.
• pad P17 is the only pad connected to its edge tile 106. Therefore, as shown in Fig. 10D, only one of pad ⁇ PV, PZ, PY and PX (in thi ⁇ embodiment, pad PV) is connected to edge tile 106.
• Fig. IOC pad PZ and its input/output buffer structure IOBZ are eliminated, thereby reducing total chip size by reducing the total number of pads on the chip.
• Input line IZ and output line OZ are shorted together in a region which in one embodiment is outside tile 105. In this manner, all tiles 105 are identically laid out, regardless of how many pads PV, PZ, PY, or PX are provided.
• pads P6, P7 and P8 are connected to a single edge tile 105.
• pad PY and related structure ⁇ IOBY and ESDY are not provided. Thu ⁇ , the embodiment of Fig. 10D represents pads P26 through P28 of Fig. 1.
• Fig. 1 includes certain edge tiles to which no pads have been connected (two of edge tiles 103, one of edge tiles 104, and one of edge tiles 105 have no pads at all connected to them) .
• Figs. 11A through 11D illustrate the four corner tiles 113, 114, 115, and 116, re ⁇ pectively, of chip 100 (Fig. 1) .
• Fig. 11A include ⁇ a conventional boundary ⁇ can block BSCAN compatible with IEEE 1149.1 de ⁇ cribed in detail in a Xilinx Application Note by Lui ⁇ Morale ⁇ entitled, "Boundary Scan in XC4000 Device ⁇ " and available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, which i ⁇ herein incorporated by reference in it ⁇ entirety.
• Fig. 11A include ⁇ a conventional boundary ⁇ can block BSCAN compatible with IEEE 1149.1 de ⁇ cribed in detail in a Xilinx Application Note by Lui ⁇ Morale ⁇ entitled, "Boundary Scan in XC4000 Device ⁇ " and available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, which i ⁇ herein incorporated by
• top left corner tile 113 includes hard connections from ⁇ ingle length ea ⁇ t line ⁇ E0-E7 to ⁇ ingle length ⁇ outh line ⁇ S0-S7, re ⁇ pectively, and programmable connection ⁇ from long horizontal line ⁇ LH0-LH7 to long vertical lines LV0-LV7, respectively.
• Fig. 11A further ⁇ how ⁇ one embodiment of an interconnect ⁇ tructure 1101 which provides the programmable connection of boundary scan block BSCAN to the above-described single length and long lines.
• Corner tile 113 also includes a programmable connection to an external pin P43 that provide ⁇ a global clock ⁇ ignal SGCK1. Corner tile 114, illu ⁇ trated in Fig.
• tile 114 (Fig. 11B) includes hard connections for connecting single length west line ⁇ W0-W7 to ⁇ ingle length ⁇ outh lines S0-S7, respectively, and programmable connections for connecting long horizontal lines LH0-LH7 to long vertical lines LV0-LV7, re ⁇ pectively.
• long vertical line LVO connect ⁇ to long horizontal line LHO, but becau ⁇ e of the layout of tile ⁇ 113 and 114, the line ⁇ are drawn in a different po ⁇ ition on the page, and therefore corner tile ⁇ 113 and 114 have a different appearance in Fig ⁇ . 11A and 11B.
• Corner tile 114 includes- a clock input pin Pl that provide ⁇ clock signal SGCK4.
• Corner tile 114 includes an interconnect structure 1102 which provides a programmable connection between a conventional oscillator/counter circuit DIV u ⁇ ed for counting bit ⁇ during configuration of chip 100 and the above-described single length and long line ⁇ .
• circuit DIV i ⁇ used during chip operation to provide an on-chip oscillator or a counter-divider.
• Circuit DIV is typically configured to divide an internal oscillator signal or a user-provided signal.
• Corner tile 114 further includes a boundary scan update signal BSUPD, which is part of the standard boundary scan circuitry (most of the circuitry being located in tile 113) .
• signal BSUPD is programmably placed on west lines W2 and W3 (and thus south lines S2 and S3) as well a ⁇ long horizontal line ⁇ LH2 and LH3 (and thus long vertical lines LV2 and LV3) .
• Fig. 12 illustrate ⁇ one embodiment of a circuit which implement ⁇ o ⁇ cillator/counter circuit DIV of Fig. 11B.
• Two output tap ⁇ , OSCl and OSC2 are provided, which together can be configured to provide twelve frequencie ⁇ which are divi ⁇ ion ⁇ of the original input frequency.
• An internal oscillator OSC provides an oscillator signal to NAND gate 1231.
• NAND gate 1231 i ⁇ enabled by a memory cell OSCRUN.
• the output ⁇ ignal from oscillator OSC is provided to multiplexer 1201.
• Memory cell 1202 determines whether multiplexer 1201 provides the output signal from internal o ⁇ cillator OSC or a ⁇ ignal on one of ⁇ ingle length west lines W0-W3 (equal to a signal on single length south lines S0-S3, respectively, see Fig. 11B) , or a signal on one of long horizontal lines LH0-LH3 (equal to a signal on long vertical line ⁇ LV0-LV3) .
• Multiplexer 1201 provide ⁇ an output ⁇ ignal which i ⁇ then available to be divided by flip flop ⁇ 1214 through 1220.
• Multiplexer ⁇ 1225 and 1226 provide a choice of divide factors on the data input terminals of flip flops 1227 and 1228 respectively.
• the outputs of the ⁇ e flip flops are provided as signal ⁇ on taps OSCl and OSC2.
• Flip flops 1227 and 1228 are clocked from the original input signal and serve to reduce the skew of the output signal ⁇ from multiplexers 1225 and 1226.
• Multiplexer 1225 under control of memory cells OSC1A and OSC1B, provides a switching signal which can be the input signal from multiplexer 1201 divided by 4, 16, 64, or 256.
• multiplexer 1204 can forward the original clock ⁇ ignal output from multiplexer 1201 or can provide a divided ⁇ ignal (the original frequency divided by 512) which i ⁇ output from flip flop 1213. If multiplexer 1204 is set to provide the output signal of multiplexer 1201, then the original clock signal is alternatively provided by multiplexer 1226 as divided by 2, 8, 32, or 128. If multiplexer 1204 is ⁇ et to provide a divided ⁇ ignal from flip flop 1213, multiplexer 1226 will provide an output ⁇ ignal which ha ⁇ the frequency of the original input ⁇ ignal on multiplexer 1201 divided by 1024, 4096, 16,384, or 65,536.
• Fig. 11C shows lower right corner tile 115.
• Corner tile 115 programmably connects long horizontal lines LH0-LH7 and long vertical lines LV0-LV7, respectively, and connects north lines N0-N7 to west lines W0-W7.
• Corner tile 115 further includes a programmable interconnect structure 1103 which programmably connects a start-up block STARTUP to north lines N0-N7 (and thu ⁇ west lines W0-W7) and long vertical lines LV0- LV7 (and thus long horizontal lines LH0-LH7) .
• Start-up block STARTUP includes circuitry to sequence the signals and control timing of the start-up function as chip 100 (Fig. 1) is activated.
• three events are necessary to move from configuration mode to operating mode: release of the signal on a global tri-state signal terminal GTS, release of the signal on a global reset signal terminal GSR, and release of a signal on a load complete terminal DONE (indicating that all configuration bits have been loaded into their appropriate locations in the FPGA) .
• the start-up block STARTUP allows the user to program the- order in which these signals are released, a ⁇ well a ⁇ the timing of these signals (for example separating each signal from another ⁇ ignal by one, two, or three clock cycle ⁇ ) .
• lower left corner tile 116 includes a read-back unit RDBK.
• Read-back unit RDBK allow ⁇ the user to read the content of the configuration memory onto any data line and out onto any external pin through the data line terminal DATA of readback unit RDBK.
• the trigger terminal TRIG in read-back unit RDBK carries a signal that trigger ⁇ copying of one row of configuration data from the configuration memory into the ⁇ ame shift register which loaded the configuration memory.
• the signal on a clock terminal CLK controls shifting out of that data onto line DATA.
• the ⁇ ignal on a read-in-progres ⁇ terminal RIP prevent ⁇ the chip from ⁇ ending another ⁇ ignal from trigger terminal TRIG while data are ⁇ till being ⁇ hifted out.
• many other embodiment ⁇ of the pre ⁇ ent invention will be apparent to tho ⁇ e ⁇ killed in the art.
• the above de ⁇ cription relates to an embodiment in which core tiles are rectangular or square, another embodiment of the present invention includes tiles having six sides.
• core tiles need not be identical.
• a set of tile designs may be provided which have different logic content from each other. If all tile de ⁇ ign ⁇ follow common boundary con ⁇ traint ⁇ , chip ⁇ can be formed by combining the tile designs in a variety of patterns. To be succe ⁇ ful, each tile design must have a good distribution of signals within the tile. The routing matrix of the tile must efficiently distribute the incoming signals to th logic block input terminal ⁇ and take the logic block output ⁇ ignals to the tile edges. Indeed a chip may be composed in which some tiles include RAM memory and no logic, or a combination of tiles having logic, tiles having memory only, and tiles having routing with no logic or memory.
• a tile may be designed which includes an input/output pad physically within its structure, and tile designs including a pad may be combined with other tile design ⁇ to achieve di ⁇ tributed acce ⁇ to logic.
• Such other embodiment ⁇ are intended to fall within the ⁇ cope of the pre ⁇ ent invention.
• the pre ⁇ ent invention i ⁇ ⁇ et forth in the claim ⁇ .

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