EP0698283A1 - Dispositif a semi-conducteur a caisson de type p auto-aligne dans une couche enterree de type p - Google Patents

Dispositif a semi-conducteur a caisson de type p auto-aligne dans une couche enterree de type p

Info

Publication number
EP0698283A1
EP0698283A1 EP95911124A EP95911124A EP0698283A1 EP 0698283 A1 EP0698283 A1 EP 0698283A1 EP 95911124 A EP95911124 A EP 95911124A EP 95911124 A EP95911124 A EP 95911124A EP 0698283 A1 EP0698283 A1 EP 0698283A1
Authority
EP
European Patent Office
Prior art keywords
well
dopant
layer
buried layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP95911124A
Other languages
German (de)
English (en)
Inventor
Datong Chen
Rashid Bashir
Joseph A. De Santis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Publication of EP0698283A1 publication Critical patent/EP0698283A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

Definitions

  • the method of fabrication and resulting structure as described in the present invention may be used to realize high-frequency and low noise fully complementary Bipolar processes (vertical NPN and PNP transistors in particular).
  • the processes can also be used in CMOS technologies employing single or dual wells and single or dual buried layers to suppress device latch-up.
  • a p-type buried layer was formed in a p-type substrate (or wafer) by using a mask, and then an epitaxial layer was grown over the p-type buried layer. Subsequently, an impurity, such as aluminum (Al), was implanted from the top of the substrate and driven down towards the buried layers, to form the p-well. This step required an additional mask and was followed by a step of thermal diffusion of the implanted impurity.
  • the present invention avoids having to use an additional mask step while providing additional advantages by using a self-aligned, mask-less method for forming a p-well.
  • a fast p-type diffuser is implanted into a p+ buried layer, prior to epitaxial growth. This way the p-well is self-aligned with the p+ buried layer because the same mask is used to define both, and the need for a separate p-well mask is eliminated.
  • the fast diffuser which may be aluminum (Al) will diffuse toward the silicon surface during the various thermal steps of the process such as epitaxial growth, field oxidation, sinker diffusion, and final drive-in, etc.
  • the dosage of aluminum used and the parameters of the thermal drive will determine the p-well doping level.
  • the doping level of the p-well can be easily controlled.
  • compensation for the n-well is non-problematic so long as the p-well implant dose is less than the p+ buried layer implant dose.
  • Figure 1 is an illustration of a structure according to the present invention after the buried layer is implanted using a mask.
  • Figure 2 is an illustration of the structure of Figure 1 after the p-well is implanted.
  • Figure 3 is an illustration of the structure of Figure 2 after the removal of the photoresist mask, etching of an oxide layer and growth of an epitaxial layer.
  • Figure 4 is an illustration of the structure of Figure 3 after pad oxide growth, nitride deposition and masking, and field oxidation steps.
  • Figure 5 is an illustration of the cross-sectional doping profile after epitaxial growth.
  • Figure 6 is an illustration of the cross-sectional doping profile at the end of the process.
  • FIG. 1 A p-type substrate 10 is shown in Figure 1.
  • An n-well 15 is formed in substrate 10 using conventional techniques.
  • a layer of pad oxide 20 is grown over substrate 10 and a photoresist mask 25 is patterned over the layer of pad oxide 20. Growth of pad oxide layer 20 is optional.
  • Mask 25 is used
  • buried layer 30 which in this case is p-type. It is to be understood that although the formation of a p-type buried layer is shown and described, an n-type buried layer could instead be formed.
  • Buried layer 30 is formed by implanting a dopant by using the photoresist mask 25.
  • boron (B) can implanted preferably to a depth of .1 to .5 microns. This can be accomplished by using a dosage between 5 x 10 and 2 x 10 atoms/cm . A dosage of 2 x 10 atoms/cm is preferred.
  • the energy level should be between 60 and 220 keV with 140 keV being the preferable amount.
  • p-well 35 can be implanted as shown in Figure 2.
  • aluminum (Al) is implanted into buried layer 30 using the same photoresist mask 25.
  • the Al can be implanted to any depth in the substrate, but a depth between .05 and .2 microns is preferred.
  • the Al should be implanted at a dosage between 1 x 10 13 and 5 x 101 atoms/cm 1 and at an energy level between 30 keV and 160 keV.
  • the implanting is performed at a dosage of 2 x 10 atoms/cm and at 50keV.
  • the aluminum is implanted at a lower energy level than is boron. This is done in order to increase p-well thickness for a fixed sinker drive, which is discussed later in more detail.
  • a rapid thermal anneal (RTA) step is performed for 10 to 120 seconds at 1000-1200 degrees Celsius. Preferably, RTA is performed for 20 seconds at 1100 degrees Celsius.
  • RTA rapid thermal anneal
  • Photoresist 25 is removed, oxide layer 20 is etched away and an n- type epitaxial layer 40 is grown over the substrate 10.
  • Oxide layer 20 may be etched using such chemistries as CF 4 + H 2 , CHF3 + 0 2 , CHF3 - --2 F 6' or CHF3 + CF 4 .
  • Epitaxial layer 40 is preferably grown to a thickness of 0.5-10 microns. During this step some diffusion of boron and aluminum occurs.
  • a layer of pad oxide 42 is grown over epitaxial layer 40.
  • nitride layer 45 is deposited over pad oxide layer 42 and then masked and etched in order to define active regions of epitaxial layer 40.
  • the regions of epitaxial layer 40 not covered by nitride layer 45 are subjected to localized oxidation of silicon (LOCOS) forming oxide regions such as 44 (of course, other oxidation methods may also be used).
  • Region 44 is preferable grown to a thickness of 1 micron.
  • the LOCOS step is done simultaneously with a sinker drive step in which a collector region (not shown) is formed. Sinker drive is preferably performed at 950 degrees Celsius for approximately 560 minutes. It is during this sinker drive step that most of the p-well diffusion occurs, resulting in the structure shown in Figure 4.
  • aluminum is a faster diffuser than boron and therefore diffuses a greater distance.
  • Figure 5 shows the amount of diffusion that results after epitaxial layer 40 is grown.
  • Figure 6 shows how much diffusion has taken place after the sinker drive step has been performed. As these experimental results show, p-well 42 has extended to a depth of approximately 4.5 microns in substrate 10, while simultaneously approaching the surface of epitaxial layer 40.
  • an n-well can be formed together with a n-type buried layer by using a fast diffusing impurity (such as phosphorous) for the n-well implant, and a slow diffusing implant (such as arsenic) for the n-type buried layer implant.
  • a fast diffusing impurity such as phosphorous
  • a slow diffusing implant such as arsenic

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

Un procédé de formation à auto-alignement et sans masque d'un caisson du type P est réalisé par implantation d'un diffuseur rapide de type P dans une couche enterrée de type P+, avant d'effectuer la croissance épitaxiale. Le caisson de type P est ainsi auto-aligné avec la couche enterrée P+ dans la mesure où un seul masque est utilisé pour les définir tous deux, ce qui élimine la nécessité d'un masque de caisson de type P séparé. Le diffuseur rapide, tel que l'aluminium (Al), se diffuse vers la surface de silicium au cours des différentes étapes thermiques du procédé, telles que la croissance épitaxiale, l'oxydation à couche épaisse, la diffusion d'élément d'implantation, la diffusion finale après implantation, etc. Le dosage de l'aluminium utilisé et les paramètres d'entraînement thermique déterminent le niveau de dopage du caisson de type P. Un caisson de type N peut être formé de manière analogue dans une couche enterrée de type N selon une technique à auto-alignement.
EP95911124A 1994-03-15 1995-02-27 Dispositif a semi-conducteur a caisson de type p auto-aligne dans une couche enterree de type p Withdrawn EP0698283A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US21362194A 1994-03-15 1994-03-15
US213621 1994-03-15
PCT/US1995/002467 WO1995025342A1 (fr) 1994-03-15 1995-02-27 Dispositif a semi-conducteur a caisson de type p auto-aligne dans une couche enterree de type p

Publications (1)

Publication Number Publication Date
EP0698283A1 true EP0698283A1 (fr) 1996-02-28

Family

ID=22795815

Family Applications (1)

Application Number Title Priority Date Filing Date
EP95911124A Withdrawn EP0698283A1 (fr) 1994-03-15 1995-02-27 Dispositif a semi-conducteur a caisson de type p auto-aligne dans une couche enterree de type p

Country Status (3)

Country Link
EP (1) EP0698283A1 (fr)
KR (1) KR960702939A (fr)
WO (1) WO1995025342A1 (fr)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4032372A (en) * 1971-04-28 1977-06-28 International Business Machines Corporation Epitaxial outdiffusion technique for integrated bipolar and field effect transistors
EP0397014A3 (fr) * 1989-05-10 1991-02-06 National Semiconductor Corporation Caisson P dopé à l'aluminium et au bore
EP0500233A2 (fr) * 1991-02-14 1992-08-26 National Semiconductor Corporation Structure de transistor bipolaire et méthode de fabrication BICMOS IC

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9525342A1 *

Also Published As

Publication number Publication date
KR960702939A (ko) 1996-05-23
WO1995025342A1 (fr) 1995-09-21

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