EP0687354A1

EP0687354A1 - Improved semiconductor bridge explosive device

Info

Publication number: EP0687354A1
Application number: EP94909624A
Authority: EP
Inventors: Kenneth E. Willis; Martin G. Richman; William David Fahey; John G. Richards
Original assignee: Quantic Industries Inc
Current assignee: Quantic Industries Inc
Priority date: 1993-02-26
Filing date: 1994-02-23
Publication date: 1995-12-20
Anticipated expiration: 2014-02-23
Also published as: EP0687354B1; WO1994019661A1; CA2156190A1; DE69422026T2; ATE187551T1; AU6240194A; KR960701351A; JP2004077117A; DE69422026D1; JPH10504634A; JP3701286B2; EP0687354A4; JP3484517B2

Abstract

This invention discloses a method of fabricating an electroexplosive device which utilizes a semiconductor bridge (292) as an ignition element. The semiconductor bridge (292) is electrically connected to a metal header (100) by a small, low resistance contact to the extension of bridge material and through an insulating silicon substrate (270) to a eutectic bond (260) created by gold plating (350) on the metal header (100) and the silicon. The second electrode (360) of the bridge circuit is connected via wire bonds (130) to one or two conducting pins (110) which penetrate the metal header (100) and are insulated by surrounding glass (120). The design allows the use of standard semiconductor assembly methods. Since small pads of electrical material are used for electrical contact, the die size is small. A redundant connection via two conducting pins (110) insulated from the header (100) to one electrode (360) of the semiconductor bridge allows a post assembly test of the integrity of the wire bonds.

Description

IMPROVED SEMICONDUCTOR BRIDGE EXPLOSIVE DEVICE

INTRODUCTION Technical Field

The present invention relates to a method for producing electroexplosive devices which utilize a semiconductor bridge (SCB) as the ignition element.

Background

Military weapons systems and automotive air bag systems are typically activated by an electroexplosive device (EED) . The EED usually employs a small metal bridgewire to ignite a contained explosive mixture. An electric current typically in the range of from about 1 amps to about 7 amps is passed through the bridgewire. Internal resistance heats the bridgewire to a temperature in excess of about 900° K. The hot bridgewire ignites - an energetic powder, triggering the primer which in turn ignites the propellant or explosive in the system. The system may incorporate a pyrotechnic mixture, a propellant or an explosive powder.

A problem with the bridgewire type EED is a sensitivity to externally generated electric currents. High levels of electromagnetic energy from sources such as radio waves, static electricity, lightning or radar may induce an electric current within the bridgewire sufficient to cause an undesired, premature ignition. The invention of the semiconductor bridge for electroexplosive devices was disclosed in U.S. Patent No. 3,366,055 by Hollander, Jr. Several embodiments were described by Hollander which encompass all current materials used to fabricate SCBs. A semiconductor bridge circuit as described by Hollander, Jr. will initiate the explosive reaction within the primer when a current is applied. The SCB circuit is significantly less susceptible to induced electric currents and the resultant possibility of accidental or premature ignition is reduced.

A semiconductor bridge circuit comprises a circuit formed on a semiconductor material such as silicon. A heavily doped silicon region of an n-type dopant such as phosphorous is vaporized when a current of sufficient amperage is applied. The silicon vapor is electrically heated and permeates the adjacent energetic powder mixture. Through localized convection and condensation, the energetic powder is heated to its ignition temperature leading to the desired explosive reaction being initiated.

Figure 1 shows in cross-sectional representation an EED 10 for a semiconductor bridge circuit 12 as known in the prior art. The housing 20 encases a semiconductor device 12 formed from a semiconductor material such as silicon. The SCB device includes a heavily doped bridge 13 which vaporizes when a threshold current is applied. The primer housing 20 positions the bridge 13 in close proximity to a charge 14 of an energetic powder such as lead azide. The EED 10 comprises a pair of metallic feed through leads 16 which pass through a ceramic header 18. A conventional glass to metal seal bonds the feed through leads 16 to the header 18. A metallic casing 20 made, for example, of aluminum surrounds the ceramic header 18 and a charge holder 22. Wire bonds 24 electrically interconnect the metal feed through leads 16 to bond pads 26 formed on opposite sides of the surface of the semiconductor bridge device 12, with one bonding pad located on each side of the bridge and connecting to the lead wire on the surface of the die. When a voltage is applied across feed through leads 16, current flows through the bridge 13. The bridge vaporizes forming a plasma cloud within the energetic powder 14. The electric current further heats the plasma vapor such that local convection and condensation heat the energetic powder 14 to ignition. The entire process from application of voltage to ignition takes place in less than about 20 micro-seconds.

A problem with the primer housing 10 of the prior art are (1) the ceramic header 18 is brittle and subject to fracture when the explosive device is handled roughly, and (2) the wire bonds 24 are in contact with the primer charge 14. The primer charge is compacted to maximize the explosive energy. Another problem is that compaction of the powder 14 applies stresses to the wire bonds 24 potentially leading to the wires either breaking or pulling loose from either the feed through leads 16 or from the bond pads 26. This package is not a preferred structure. Forming ceramic headers with metal feed-throughs is a relatively expensive process adding to the cost of the device. This is particularly true if the casing 20 must be hermetically sealed against the ceramic 18. Further, if large electrical pads are used to achieve low resistance connections, it increases the die 12 area and therefore the size and cost of the device. The advantages of the SCB type initiator over the bridgewire include lower electrical energy requirements, less susceptibility to accidental or premature initiation and more rapid and precise firing times. However, methods used to attach the semiconductor bridge die to the EED header have demonstrated poor reliability and have been costly to produce. The SCB circuit is formed on a brittle semiconductor substrate. The package housing the device must provide both mechanical and environmental protection to the device. The components making up the electronic package must also be compatible with the SCB device, the energetic powder, and the attachment materials. The electrical connections to the die must withstand pressure from powder loading and consolidation.

Several patents have focused on methods for attaching the SCB to a header in order to lower cost and improve reliability. One method for fabricating the SCB to achieve efficient attachment to a header is disclosed in U.S. Patent No. 4,708,069 to Bickes, Jr., et al. , and in Sandia National Labs Report No. SAND 86-2211 edited by Bickes, Jr., both of which are incorporated herein by reference. Bickes is distinguished from Hollander by using " a pair of spaced pads connected by a bridge, the area of each of said pads being much larger than the area of said bridge " as shown in Figure 2. These large pads 30 are used to achieve electrical contact with a metalized layer 34 covering the pads. The large pad size described in Bickes was used to achieve a low resistance connection to the polysilicon bridge material 32. This low resistance contact allowed a low impedance bridge, typically about 1 ohm which is common in the art, to be used which further reduced susceptibility to RF energy.

Subsequently, in U.S. Patent No. 5,029,529, Mandigo discloses a method of attaching an SCB die in an electrical primer housing which eliminates one lead wire to the die (Figure 3) which is an apparent improvement over Bickes, et al . An electrically conducting die attach means 72 is used to attach the SCB die 52 to a copper alloy primer button 40. The electrical pulse to fire the bridge follows a conductive path 74 through the silicon based device 52 and through a conductor or shunt 76 attached to the side of the die 52. The attachment method disclosed by Mandigo was used with an electrical primer 70 which is constructed from a cup 42 which forms one electrode for the external current source and a button 40 which forms the second electrode. This configuration requires an interposed insulator 54 and a conducting path from the cup 42 to the die 52 created by a wire 44 attached to the die and a conducting element 48 which is attached to the cup. This application requires a more complex assembly than conventional EEDs because it is used in gun ammunition; it is relevant to this disclosure only because of the method of achieving a conducting path through the silicon die 74 by doping the silicon.

The attachment method of Mandigo suffers from three disadvantages. First, the shunt 76 must be attached on the side of the die after the die is cut from the wafer; this process is not easily performed with standard semiconductor processing technology. Second, a single wire 44 connects the bridge to the conducting case, which is subject to failure. Third, the method utilizes the large pads of Bickes, et al. with the attendant disadvantages discussed above.

SUMMARY OF THE INVENTION Therefore, in accordance with the invention, there is provided an electronic package incorporating a semiconductor bridge type initiator circuit which does not have the disadvantages of a ceramic header type package or large connecting pads. It is an advantage of the present invention that the package components are manufactured from a standard TO (transistor outline) package widely used in the semiconductor industry and available at low cost. It is another advantage of the invention that in one embodiment of the invention the lead wires are configured to minimize the potential for breakage and subsequent device failure. By using two wires connected at one end to one bonding pad on the die and at the opposite wire ends to separate and redundant pins insulated from the header, the device can be tested before and after loading the explosive powder. This test is accomplished by checking for the presence of a very low resistance between the redundant insulated pins. Any imperfection in the bonds or wire will increase the measured resistance so as to detect the flaw. Yet another advantage of the invention is that small pads of electrical material can be used to connect the bridge, as opposed to the large pads of Bickes' , thereby reducing the amount of silicon per die which in turn produces higher yields, lower cost per die, increased structural rigidity, and resistance to fracture during powder pressing. It is another advantage of the invention that automated assembly methods developed for the semiconductor industry can be used in assembly, thereby improving reliability and reducing cost. It is another advantage of the invention that a eutectic bond between the bridge die and the metal header dissipates heat effectively, thereby reducing vulnerability to spurious induced currents in the bridge. This bonding method also provides more mechanical strength to resist fracture from pressing the explosive powder onto the header.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional side view of a prior art semiconductor bridge device.

Figure 2a is a top view of a second prior art semiconductor bridge device.

Figure 2b is a cross-sectional side view of the second prior art semiconductor bridge device shown in Figure 2a.

Figure 3 is a cross-sectional side view of a third prior art semiconductor bridge device. Figure 4a is a top view of the present invention, showing the semiconductor bridge device, connecting wires, and package, but excluding the explosive material and top lid of the package. Figure 4b is a side view of the invention taken along the cross-sectional line "A" of Figure 4a.

Figure 5 is a cross-sectional side view of the assembled apparatus of the present invention. Figure 6 is a cross-sectional side view of the semiconductor bridge die of the present invention taken along the cross-sectional line "A" of Figure 7. Figure 7 is a top view of the semiconductor bridge die of the present invention.

Figure 8a is a top view of an alternative embodiment of the semiconductor bridge die.

Figure 8b is a cross-section taken along line A-A of Figure 8a showing the substrate, the wrap around conducting layers, and the bridge of the alternative embodiment of the semiconductor bridge die.

Figure 8c is a bottom view of the alternative embodiment of the semiconductor bridge die.

Figure 9a is a cross-section of a portion of the wafer after formation of the bridge thereon and grooves therein.

Figure 9b is a top view of the wafer shown in Figure 9a, showing the location of the contact pads on the bridge.

Figure 10a is a bottom view of a ceramic substrate which is a mounting surface for the header of Figure 11. Figure 10b is a top view of the ceramic substrate. In one embodiment, it provides the electrical connections between the pins and the conducting layers on the back surface of the semiconductor bridge die. Figure 11 is a top view of the alternative embodiment illustrating the relationship of the semiconductor bridge die, the header, metallization patterns, and pins.

The above figures are not to scale. DESCRIPTION OF SPECIFIC EMBODIMENTS Figure 4 illustrates an EED header assembly 200 adapted to house a semiconductor bridge device 150 in accordance with an embodiment of the invention. The transistor outline (TO) header 100 is made of a steel alloy and is gold plated, as is common practice in the industry. The semiconductor bridge 150 is constructed in accordance with the methods of Hollander, but utilizes small pads of the electrical material which extend beyond the bridge. The electrical material is silicon which is doped so as to make it highly conductive. When assembled, the silicon in the die and gold plating on the header form a eutectic bond when heated, hence providing a good electrical, thermal and mechanical contact to the header, creating one side of the circuit through ground pin 140. The other side of the SCB circuit is redundantly connected to separate feed-through pins 110 by separate wire bonds 130. Feed-through pins 110 are isolated from the header body 100 and from each other by the glass insulators 120.

Since wire bonds 130 are the weakest element of the circuit, an advantage of this invention is that these bonds are redundant, and allow for nondestructive testing after assembly to confirm their integrity. After loading the explosive powder, the resistance between the redundant conductors 110 should remain very low if no damage to the wires or bonds have occurred. Thus, the slightest weakness, dislocation or breakage in the wire or the bonds can be detected by a small positive resistance measured during the test. In other words, one may connect the two leads of an ohmmeter to each of the pins 110. An open circuit or significant positive resistance indicates that one or both of the wire bonds 130 are damaged. A closed circuit indicates a functional device.

Figure 5 shows the rest of the EED assembly which is attached to the header assembly described above. A loading sleeve 170 is resistance welded to the header 100. The explosive powder 200 is then loaded and pressed into the sleeve 170. Finally, a cover 180 is welded over the entire EED to create a hermetic seal.

It is a significant advantage of the invention that all of the above assembly processes can be performed with automated equipment readily available in the semiconductor industry. In particular, the process of placing the die on the header, creating the eutectic bond between the die and the header, attaching the connecting wires between the die and the pins, and welding the load sleeve can be performed in a totally automated manner. Figures 6 and 7 (not to scale) describe in greater detail the structure of the SCB die 150 and its attachment to the TO header 100. In this embodiment, the electrical material is heavily doped silicon which covers an area comparable to the bridge size. Therefore, the overall size of the die 270 can be small, approximately 50 mils by 50 mils or less. The substrate material 270 is approximately 5 mils thick and is intrinsic (relatively insulating) silicon with resistivity of approximately 100-200 ohm centimeters.

The SCB is fabricated by the following process. First, a field oxide insulating layer 280 is grown over the surface of the die. The edges of the field oxide 280 are approximately contiguous with the edge of the die 270.

Next, a masking step etches away the field oxide 280 to expose areas 292, 294 and 295, which will form the material of the bridge 292 and connecting pads 294 and 295 to the bridge 292. These exposed areas 292, 294 and 295 are doped with phosphorus to an approximate concentration of 10¹⁹ to 10²⁰ atoms/cc to yield a resistivity of approximately .8 milliohm-cm with a depth of dopant approximately 2 microns. This doping process forms the conducting region 300.

This bridge construction will yield a 1 ohm bridge, which is a standard in the art, if the W/L ratio is approximately 4. Similarly, a resistance of 2 ohms, which is common for automotive air bag initiators, is achieved when W/L is approximately 2. The length L of the bridge determines the voltage at which the bridge will function. For example, a length of 50 microns results in an operating voltage of about 20 volts. The top surface area of each of said pads 294 and 295 is relatively small compared to the bridge 292, preferably not more than twice the top surface area of the bridge 292. Next, a metallization layer is deposited over pads 294 and 295. (A separate masking layer is used to expose pads 294 and 295.) In the preferred embodiment, the metallization layer comprises a first platinum suicide layer 330, followed by a titanium tungsten alloy 340 and an overplate of gold 350. The gold layer 350 provides for easy wire bonding to wire bonds 130.

In the preferred embodiment, platinum suicide layer 330 is approximately 600 Angstroms thick. This layer is created by the deposition of platinum on the silicon, then sintering for approximately 30 minutes at approximately 615 degrees centigrade. Finally, the remaining pure platinum is etched away leaving only the platinum suicide. The titanium/tungsten alloy layer 340 is approximately 1000 Angstroms thick and is about 85% tungsten and 15% titanium. It is vapor deposited.

Next, a contact (or via) hole 310 is etched through the silicon substrate 270. The back of the substrate is masked, and the contact hole is etched from the back of the substrate to the front. This hole will be 2-3 mils in diameter at the top and 4-5 mils in diameter at the bottom. As can be seen in Figure 7, the bridge 292 and pads 294 and 295 do not overlap the contact hole 310 and do not extend as far as the edge of the oxide 280 or substrate 270.

The final gold layer 350 is plated to a thickness of approximately 1.5-2 microns thick over the pads; it also completely fills the contact hole 310. A mask is first applied to the metallization layers 330, 340 and 350 to define separate bonding pads 355 and 360. Gold is then sputtered through the mask onto the front surface of the substrate, and also plated onto the front surface. Gold is also separately plated onto the back surface.

In this manner, one silicon pad 294 is connected to the bridge 292 and is also connected to the header 100 by metal pad 355. In other words, an electrical connection is made from pad 294 through the substrate to the header; metal pad 355 is the only electrical connection between that side of the doped silicon bridge material and the header. The other side of the doped silicon bridge layer is connected to metal pad 360, which is insulated from the substrate 270. Pad 360 is subsequently connected to wires 130.

Thereafter, the wafer is then etched to form individual SCB dies 150. The SCB die is attached to the header surface 100 through a eutectic bond 260 created by depositing a layer of gold 250 on top of the header and bonding the substrate 270 to the gold using conventional techniques, such as those described in the book VLSI Technology by S. M. Sze (2nd Edition) . The die's small size and eutectic bond assures that the die will survive the pressure from pressing against the explosive powder. Wire bonds 130 are then attached to the die as described previously.

An improved method of attaching a semiconductor bridge to the header of an electro-explosive device is now described. The method can result in a semiconductor bridge die 500 as shown in Figures 8a, 8b, and 8c. As described earlier, an electrical current through a bridge of a die can be used in an electro-explosive device to initiate an explosive powder.

In one embodiment, the bridge 510 may be made of heavily doped silicon as described in U.S. Patent No. 3,366,055 to Hollander which is hereby incorporated by reference. In an alternative embodiment, the bridge 510 is made of a thin tungsten layer deposited by chemical vapor deposition as described in U.S. Patent No. 4,976,200 to Benson et al . which is hereby incorporated by reference. For conciseness, this attachment method will be only described as it applies to a doped silicon bridge. However, the method is also applicable to the tungsten/silicon bridge.

Figure 8 illustrates an embodiment of the die 500. A number of the die 500 can be fabricated from a silicon wafer 5 to 15 cm in diameter and 0.2 to 0.4 mm thick. Favorable results can be achieved when the intrinsic silicon wafer has a resistivity of about 100 ohm-cm or higher. The bridge 510 can be a heavily doped silicon achieving a relatively low resistivity of about 10^"3 ohm-cm.

Figure 9a is a cross-section of part of the silicon wafer. The silicon wafer is oxidized, then implanted with n-type dopant atoms such as phosphorus using a conventional 100,000 volt electron beam technique. The Hollander patent describes other suitable n-type dopants.

Favorable results have been achieved when the dopant concentration is about 10¹⁹ to 10²¹ cm^"3. One preferred dopant concentration is about 10²⁰ cm^"3. In one embodiment, the doped silicon wafer is elevated to a temperature of about 1050°C for approximately 20 minutes resulting in a diffusion depth of about 1 to 3 microns. The diffusion should be in a furnace under an inert atmosphere such as argon gas. After diffusion, hydrofluoric acid removes the oxide on the silicon wafer.

Conventional photolithography defines a pattern for making bridge 510. The mask (not shown) defines an array of patterns so that each die 500 has a length and width of somewhere between 0.5 to 1.0 mm.

Although the exact dimensions are not critical, each die should be sufficiently large for handling with conventional automated assembly equipment yet small enough to maximize the yield of dies per wafer. After the bridge 510 is fabricated, a saw cuts parallel grooves 550 into the front of the wafer (Figures 9a and 9b) . The bridge 510 can be a reference for aligning the saw. In one embodiment, the grooves 550 have a depth of 0.1 mm, a width of 0.1 mm, and are spaced apart 0.5 to 1 mm in the geometry shown in Figures 9a and 9b. As shown in Figure 9a, the depth of each groove 550 is less than the thickness of the wafer. After the grooves 550 are formed, conventional photolithography is used to protect area 510 from a etch process. The remainder of the wafer is etched to a depth of 2 to 4 microns. This fully exposes the silicon and forms a mesa, that is, the bridge 510 of heavily doped silicon.

Conventional photolithography techniques expose areas for contact pads 590 for etching. The silicon wafer is then exposed to a palladium electron beam process. Deposited palladium reacts with the exposed silicon in areas 590 forming a palladium suicide layer. An ultrasonic bath lifts the non- reacted palladium off the wafer leaving palladium suicide contact pads 590. A mask then covers the bridge 510 and exposes the rest of the wafer. A conventional titanium/tungsten layer is sputtered on the exposed areas to a depth of about 0.1 to 0.2 microns. This forms an ohmic contact. This is followed by a sputtered gold layer of about the same depth. Gold is selectively plated for conducting layers 580 and contact pads 590 as shown in Figure 8. A suitable gold plating thickness is about 6 to 8 microns.

The next process step removes a gold layer from the front of the wafer. As shown in Figures 8a and 8b, each conducting layer 580 extends around the edge 535 into the bottom 545 of a groove 550 (Figure 9a) . The front of the wafer is etched for 5-10 seconds removing 0.1 to 0.2 microns of gold. A wet etch removes the exposed titanium/tungsten.

Although a thin gold layer is removed, a thick layer of gold remains on the desired surfaces of groove 550.

The wafer is then turned over for processing of the back surface. The back of the wafer can be alternately sandblasted and etched until the gold plating extending into the bottom 545 of each groove 550 is visible from the back of the wafer. A suitable material for sandblasting is aluminum oxide particles of about 18 micron average diameter. Any oxide layer is then etched off the wafer.

A nickel-chromium sputter and a gold sputter is then applied, each having a thickness of about 0.1 to 0.2 microns. Gold is plated to a thickness of 0.5 to 2 microns forming a "wrap around conductor layer" extending from the front to the back surface of the wafer. As shown in Figures 8a and 8b, each conducting layer 580 ultimately contacts bridge 510 at a contact pad 590, goes around an edge 535 and extends to a back surface 530 of the die 500.

It should be noted that the conducting layer 580 can be of aluminum or gold. Gold is preferred, however, for soldering the die 500 to a ceramic substrate 600 (Figure 10) . The next step is to mask and etch away the metallization over a strip 560 (Figure 8c) on the back of the wafer so as to restrict the conducting layers 580 to surfaces 530 on the back surface of the die. The wafer is then turned back over. A saw separates the wafer into individual die 500 by cutting grooves that are perpendicular to the parallel grooves 550 cut earlier. Each die 500 is ready for mounting on a ceramic substrate 600 as shown in Figures 10a (i.e. bottom view) and 10b (i.e. top view), which will be in turn mounted on the header 100 (Figure 11) .

As shown in Figure 10, the ceramic substrate 600 includes a metallization pattern 630 to make the proper electrical connections. Solder or conductive epoxy makes the electrical connection between the pins 110 and the metallization pattern 630. The metallization pattern 640 on the back of ceramic substrate 600 is soldered to the header 100 and spaced from pin connecting recesses 620 in areas 610 and 615 (Figure 10a) to avoid shorting the metallization pattern 630 to the header 100. The metallization pattern 630 electrically connects the pins 110 to the conducting layers 580 on the back surfaces 530 of the die 500.

Figure 11 illustrates a header 100 attached to the ceramic substrate 600 and electrically connected to pins 110. The final assembly is made by soldering or using conducting epoxy between (1) the surface of the header 100 and the metallization pattern 640; (2) the pins 110 and the metallization pattern 630; and (3) the metallization pattern 630 and the conducting layers 580 on back surfaces 530 of the die 500. The header 100 can be now loaded with explosive powder 14 to make an electro¬ explosive device as described earlier. The invention now being fully described, it will be apparent to one of ordinary skill in the art that many changes and modifications can be made thereto without departing from the spirit or scope of the appended claims.

Claims

WHAT IS CLAIMED IS

1. A semiconductor bridge explosive device in which said device is mounted on an electrically conducting header, said device comprising

an electrically insulating substrate mounted on said header,

a contact hole in a portion of said insulating substrate extending from the surface of said substrate to the bottom of said substrate,

a heavily doped silicon layer disposed in a portion of said insulating substrate, said portion not including said contact hole or the edges of said insulating substrate, said silicon layer defining first and second spaced pads connected by a bridge,

a metallic electrode material disposed over said silicon layer and substrate, said electrode material defining separate first and second electrodes,

said first electrode being in electrical contact with the first pad of said silicon layer and in electrical contact with said header through said contact hole, wherein an electrical connection is made from the first pad through the substrate to the header, said first electrode being the only electrical connection between said first pad and the header,

said second electrode being in electrical contact with the second pad of said silicon layer, and

an explosive material in contact with said bridge.

The device of claim 1, wherein the top surface area of each of said pads is not more than twice than the top surface area of said bridge.

3. The device of claims 1 or 2, wherein said header includes two conducting pins extending through said header, said pins being insulated from the header body, and each of said pins connected by separate metallic wires to said second electrode.

4. The device of claim 3 further comprising a third pin in electrical contact with the header body.

5. The device of claim 4, wherein said device is mounted within a transistor outline (TO) package.

6. The device of claim 1, wherein the portion of said electrode material in contact with said pads further comprises a bottom layer including a platinum suicide compound, a middle layer comprising an alloy including titanium and tungsten, and a top layer comprising a gold alloy.

7. The device of claim 6, wherein the top surface area of each of said pads is not more than twice than the top surface area of said bridge.

8. The device of claims 6 or 7, wherein said

, header includes two conducting pins extending through said header, said pins being insulated from the header body, and each of said pins connected by separate metallic wires to said second electrode.

9. The device of claim 8 further comprising a third pin in electrical contact with the header body.

10. The device of claim 9, wherein said device is mounted within a transistor outline (TO) package.

11. The device of claim 1, wherein said substrate is comprised of intrinsic silicon.

12. The device of claim 11, wherein the top surface area of each of said pads is not more than twice than the top surface area of said bridge.

13. The device of claims 11 or 12, wherein said header includes two conducting pins extending through said header, said pins being insulated from the header body, and each of said pins connected by separate metallic wires to said second electrode.

14. The device of claim 13 further comprising a third pin in electrical contact with the header body.

15. The device of claim 14, wherein said device is mounted within a transistor outline (TO) package.

16. The device of claim 11, wherein the portion of said electrode material in contact with said pads further comprises a bottom layer including a platinum suicide compound, a middle layer comprising an alloy including titanium and tungsten, and a top layer comprising a gold alloy.

17. The device of claim 16, wherein the top surface area of each of said pads is not more than twice than the top surface area of said bridge.

18. The device of claims 16 or 17, wherein said header includes two conducting pins extending through said header, said pins being insulated from the header body, and each of said pins connected by separate metallic wires to said second electrode.

19. The device of claim 18 further comprising a third pin in electrical contact with the header body.

20. The device of claim 19, wherein said device is mounted within a transistor outline (TO) package.

21. A semiconductor bridge explosive device in which said device is mounted on an electrically conducting header, said device comprising

an electrically insulating substrate mounted on said header,

a heavily doped silicon layer disposed in a portion of said insulating substrate, said silicon layer defining first and second spaced pads connected by a bridge,

said first electrode being in electrical contact with the first pad of said silicon layer and in electrical contact with said header, wherein an electrical connection is made from the first pad through the substrate to the header, said first electrode being the only electrical connection between said first pad and the header,

said second electrode being in electrical contact with the second pad of said silicon layer, said header including two conducting pins extending through said header, said pins being insulated from the header body, and each of said pins connected by separate metallic wires to said second electrode, and

an explosive material in contact with said bridge.

22. The device of claim 21, wherein the top surface area of each of said pads is not more than twice than the top surface area of said bridge.

23. The device of claims 21 or 22, wherein the portion of said electrode material in contact with said pads further comprises a bottom layer including a platinum suicide compound, a middle layer comprising a compound including titanium and tungsten, and a top layer comprising a gold compound.

24. The device of claim 23 further comprising a third pin in electrical contact with the header body.

25. The device of claim 24, wherein said device is mounted within a transistor outline (TO) package.

26. The device of claim 21, wherein said substrate is comprised of intrinsic silicon.

27. The device of claim 26, wherein the top surface area of each of said pads is not more than twice than the top surface area of said bridge.

28. The device of claims 26 or 27, wherein the portion of said electrode material in contact with said pads further comprises a bottom layer including a platinum suicide compound, a middle layer comprising a compound including titanium and tungsten, and a top layer comprising a gold compound.

29. The device of claim 28 further comprising a third pin in electrical contact with the header body.

30. The device of claim 29, wherein said device is mounted within a transistor outline (TO) package.

31. A semiconductor bridge die adapted for mounting to a header, comprising: an insulating substrate having a top and a bottom; a bridge in a portion of the substrate defining first and second spaced apart contact pads at the top; a first conducting layer which wraps around the substrate from the first contact pad to the bottom; a second conducting layer which wraps around the substrate from the second contact pad to the bottom; and an explosive material contacting the bridge.

32. The die of claim 31, wherein the surface area of each of the contact pads is not more than twice than the top surface area of the bridge.

33. The die of claims 31 or 32, further comprising a second substrate with spaced apart first and second conductive areas and a header including two conducting pins insulated from each other and extending through the header, one pin being connected to the first conductive area and the other pin being connected to second conductive area.

34. The die of claim 33, wherein the bridge is connected to the first and the second conductive area.

35. The die of claim 34, wherein the die is mounted within a transistor outline (TO) package.

36. The die of claim 31, wherein the portion of the material in contact with the pads further comprises a bottom layer including a platinum silicide compound, an intermediate layer comprising an alloy including titanium and tungsten, and a top layer comprising a gold alloy.

37. The die of claim 36, wherein the top surface area of each of the pads is not more than twice than the top surface area of the bridge.

38. The die of claims 36 or 37, further comprising a second substrate with spaced apart first and second conductive areas and a header including two conducting pins insulated from each other and extending through the header, one pin being connected to the first conductive area and the other pin being connected to second conductive area.

39. The die of claim 38, wherein the bridge is connected to the first and the second conductive area.

40. The die of claim 39, wherein the die is mounted within a transistor outline (TO) package.

41. The die of claim 31, wherein the substrate is comprised of intrinsic silicon.

42. The die of claim 41, wherein the top surface area of each of the pads is not more than twice than the top surface area of the bridge.

43. The die of claims 41 or 42, further comprising a second substrate with spaced apart first and second conductive areas and a header including two conducting pins insulated from each other and extending through the header, one pin being connected to the first conductive area and the other pin being connected to second conductive area.

44. The die of claim 43, wherein the bridge is connected to the first and second conductive area.

45. The die of claim 44, wherein the die is mounted within a transistor outline (TO) package.

46. The die of claim 41, wherein the portion of the first or second conducting layer in contact with the pads further comprises a bottom layer including a platinum silicide compound, a intermediate layer comprising an alloy including titanium and tungsten, and a top layer comprising a gold alloy.

47. The die of claim 46, wherein the top surface area of each of the pads is not more than twice than the top surface area of the bridge.

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48. The die of claims 46 or 47, further comprising a second substrate with spaced apart first and second conductive areas and a header including two conducting pins insulated from each

15 other and extending through the header, one pin being connected to the first conductive area and the other pin being connected to second conductive area.

49. The die of claim 48, wherein the bridge is

20 connected to the first and second conductive area.

50. The die of claim 49, wherein the die is mounted within a transistor outline (TO) package.

25 51. A method of making a semiconductor device, including the steps of: forming an active device region on the top of a substrate, the region including at least one contact pad;

30 cutting at least one groove into the top of the substrate; depositing a first conductive material on the top of the substrate, the first conductive material being on contact with the contact pad and filling the groove; removing the material from the back of the substrate until the first conductive material is accessible from the back; and depositing a second conductive material on the back of the substrate so that the second conductive material contacts the first conductive material.

52. The method of claim 51, wherein the active device region comprises a semiconductor bridge igniter.

53. The method of claim 52, wherein the semiconductor bridge igniter further comprises a tungsten/silicon layer .

54. The method of claims 51, 52 or 53, further comprising the step of using the boundaries of the active device region to define the location and spacing of the groove.

55. The method of claims 51, 52, 53 or 54, further comprising the steps of masking and etching the first and second conductive layers to define a conductive region electrically connected to the contact pad.

56. The method of claims 54 or 55, wherein the active device region includes at least two contact pads.

57. The method of claim 56, further including a pair of parallel grooves cut into the top of the substrate.