EP0681741A1 - Electronic chip carrier package and method of making thereof - Google Patents
Electronic chip carrier package and method of making thereofInfo
- Publication number
- EP0681741A1 EP0681741A1 EP95901084A EP95901084A EP0681741A1 EP 0681741 A1 EP0681741 A1 EP 0681741A1 EP 95901084 A EP95901084 A EP 95901084A EP 95901084 A EP95901084 A EP 95901084A EP 0681741 A1 EP0681741 A1 EP 0681741A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- dielectric
- leads
- layer
- chip carrier
- frame layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
A method and design for packaging electronic chip devices, especially devices intended for radio frequency (RF) and microwave frequencies above 900 MHz is disclosed. An array of metal leads (100) are bonded between two layers of a sheet polymer composite that have been cut to form frames (40, 130) in such a way that the metal leads (100) extend from outside to inside of the single frame shape formed by a pressure and heat bonding step. The polymer composite frame serves the dual purpose of holding the leads in a desired configuration for later assembly and testing steps both inside and outside of its area, and of providing a microwave quality, low insertion loss, low permittivity and electrical insulation function between leads and ground planes. This dual purpose is provided in a uniquely cost-effective way that makes it of particular value for packaging high frequency electronic components intended for the growing consumer and commercial applications market.
Description
ELECTRONIC CHIP CARRIER PACKAGE AND METHOD OF MAKING THEREOF
Background of the Invention:
Field of the Invention
The invention re. es to an improved chip carrier package and method of making the same such that the carrier is suitable for high radio frequency and microwave applications while maintaining low loss, low permittivity and low cost. The present invention finds particular utility in those applications requiring frequencies above 900 MHz.
Discussion of the Prior Art
The chip carrier industry has been aware for some time of the need for and design constraints of an alternative to high permittivity ceramic chip packages or molded plastic pack; ges for packaging high frequency digital and analog chip devices for the growing requirements r -omπr ial ar.<^ consumer applications.
Ceramic packages with leads are produced cost~_.-ectively by thick or thin film metallization of a ceramic layer which is then cofired with a cover piece of ceramic green sheet to form the frame with leads. Typically, the ceramics have
relatively high permittivity and the metal leads formed from firing powdered metal with glass frits have relatively high losses at high frequencies.
Molded plastic packages incorporating punched metal leads carried in a lead frame design have been used for many years for low cost packaging of digital electronic devices for the well known dual-in-line package (DIP). These packages normally use injection moldable thermoset composites to result in a package that will survive assembly operations such as soldering. While the leads in these packages can be low loss, the electrical loss of the dielectric at high frequencies limits their usefulness in microwave applications. In addition, such packages do not incorporate a conductive ground plane close to the die.
Chip devices or dies designed for high speed or high frequency applications are usually built on gallium arsenide (GaAs) substrates typically only about 100 micrometers thick. To realize planned performance at or above 900 MHz, the mounting surface must be a conductive ground plane. GaAs dies are typically mounted to the floor of a costly metal housing with gold-tin or gold-silicon solder.
The cost of such packages is, therefore, unacceptably high. Moreover, there is no convenient way to pretest the die before the package is committed to it so there is a risk of a relatively high failure rate when commercially produced.
Summary of the Invention:
The above-discussed and other problems and deficiencies of the prior art are overcome or alleviated by the novel chip carrier package and method of manufacture thereof of the present invention. The present invention is intended for, and effective in overcoming deficiencies of, prior art chip carriers with respect to high frequency and microwave applications. Moreover, the method of constructing the chip carrier package of this invention is extremely cost effective and so, is economically desirable.
In accordance with the present invention, the chip carrier is constructed by providing a metallic base plate appropriately dimensioned and shaped to accept and
interconnect with a first layer frame of dielectric material having a low permittivity. Generally, the base plate will have a raised central portion which can be of any desired shape; the first frame layer of dielectric material then being shaped to fit over the raised portion in a cooperating manner. A lead frame, having been previously manufactured, and having an outer perimeter and finger-like leads extending inwardly therefrom, is placed upon the first frame layer of dielectric material so that the inner ends of the leads overlay the dielectric material.
It should be noted at this point that a line connecting the inner ends of the leads would define a space having a shape, preferably square or rectangular, similar to the shape of the raised portion of the base plate.
Once the lead frame is placed in position, a second frame layer of dielectric material is placed so as to sandwich the ends of the leads between the first and second frame layers of dielectric material. The second frame layer of dielectric material is shaped substantially similarly to the first frame layer and defines a void having the same shape as the space defined by the inner ends of the leads but having slightly larger dimensions, preferably square or rectangular.
After the base, first dielectric frame layer, lead frame and second dielectric frame layer are properly assembled, the entire structure is clamped and then heated to a temperature sufficient to soften the dielectric and thereby embed the leads in the dielectric material. This step is followed by a speedy cooling step to prevent the dielectric material from deforming in the areas not contacted by leads.
The chip carrier can subsequently be cut free from the lead frame by any of a number of conventional methods, such as punching. Leads are then available for desired bending and/or mounting. It will be appreciated that other types of mounting arrangements for carriers, for example, plated through hole pins, etc. and many different configurations of chip carriers can be produced using the method of the invention.
As is clear from the foregoing, the resultant electronic chip carrier package comprises an array of metal leads bonded between two layers of a sheet polymer composite (e.g., filled fluoropolymer dielectric) that have been precut to form frames in such a way that the metal leads extend from outside to inside of the single frame shape formed by a pressure and heat bonding step. The polymer composite frame serves the dual purpose of holding the leads in a desired configuration for later assembly and testing steps both inside and outside of its area, and of providing a microwave quality, low insertion loss, low permittivity and electrical insulation function between leads and ground planes. This dual purpose is provided in a uniquely cost-effective way that makes it of particular value for packaging high frequency (e.g., greater than 900 MHz) electronic components intended for growing consumer and commercial applications market.
The above-discussed and other features and advantages of the present invention will be appreciated and understood by those skilled in the art from the following detailed description and drawings.
Brief Description of the Drawings:
Referring now to the drawings wherein like elements are numbered alike in the several FIGURES:
FIGURE 1 is an exploded, perspective view of the chip carrier of the invention;
FIGURE 2 is a top plan view of the assembled chip carrier with the lead frame still attached;
FIGURE 2a is a cross-section of FIGURE 2 taken along section line a-a.; FIGURE 2b is a cross-section of FIGURE 2 taken along section line b-b; FIGURE 3 is a perspective view of the completed chip carrier package of the invention;
FIGURE 4 is a top plan view of another embodiment of the invention showing five RF leads with widened sections outside of the package and 3 DC leads;
FIGURE 5 is a top plan view of another embodiment featuring a small space between the metallic base and the first dielectric layer;
FIGURE 5a is a cross-sectional view of FIGURE 5 taken along section lines a-a;
FIGURE 6 is a top plan view of a further embodiment; and
FIGURE 6a is a sectional view of FIGURE 6 taken along section lines a-a; . FIGURE 6b is an enlarged side view of FIGURE 6 taken along section lines a-a.
FIGURE 7 is a perspective view of a dual in-line type of chip carrier package made by the invention.
FIGURE 7a is a side view of FIGURE 7. FIGURE 7b is an end view of FIGURE 7.
FIGURE 7c is a top plan view of FIGURE 7.
FIGURE 8 is a perspective view of another embodiment of the invention where the entire carrier is enclosed in covering material.
FIGURE 8a is a side view of FIGURE 8. FIGURE 8b is an end view of FIGURE 8.
FIGURE 8c is a top plan view of FIGURE 8.
DESCRIPTION OF THE PREFERRED EMBODIMENT:
Referring to FIGURE 1, one of skill in the art can ascertain that the lowest of the exploded parts of the figure is a base plate 10, which can be metallic or made of a conductive polymer such as a PTFE material partially plated with a conductive resin such as silver-epoxy resin composite. In the preferred embodiment, the metal used is copper but can be any conductive metal.
The base metal is coined to have a raised plateau area 30 of about 0.025 inch (0.64 mm) in thickness and a border region 20 of about 0.013 inch (0.33 mm) in thickness. The shape of the plateau area 30 is, as mentioned above, complimentary to the shape of the first dielectric frame layer 40. Most preferably, the raised plateau 30 of the base metal is in the shape of a square or rectangle when viewed from the top.
The preferred dielectric material comprises a filled fluoropolymeric material. Preferably the fluoropolymeric matrix comprises polytetrafluoroethylene (PTFE) with glass microfiber filler. The fluoropolymer matrix may also contain a suitable inorganic filler material such as ceramic powder (Ti02, Si02 or alumina). Materials of this type are commonly available from Rogers Corporation of Rogers, Connecticut, under the trademark RT/Duroid with a more preferred material comprising glass microfiber reinforced PTFE sold under the trademark RT/Duroid 5870. The most preferred material however, is a variant of RT/Duroid 5870 called Ultralam GH where cladding is not applied to the dielectric material by the manufacturer of the material. Utilizing the most preferred material both reduces cost of purchase of the material and provides for a superior product. The superiority of Ultralam GH is due to the better bonding properties of the unclad material. This particular material was chosen because of its known desirable electrical properties such as low permittivity, low loss, microwave compatibility, high temperature capability and ease of fabrication. The thickness of the dielectric material used, in order to meet space constraints and design impedance values is as little .as 250 μm for each frame layer. The thickness of the dielectric material can, however, be as large as 5 mm (5000 μm). After the base metal 10 is coined to the desired shape and thickness, the dielectric material, first layer, is cut into a frame 40, by a programmed router or a punch and die set, the latter being preferred, to be of a complimentary shape to the plateau 30 on the base material. In the preferred embodiment, the dielectric material is square or rectangularly shaped on its outer perimeter 50 and is punched
out in like shape to form its inner perimeter 60. The inner perimeter 60 is dimensioned to receive the plateau 30 of the base 10. In the embodiment shown in FIGURE 1, the first PTFE frame layer 40 has outer perimetrical dimensions of 190 x 230 mils (4.826 x 5.842 mm), inner perimetrical dimensions of 110 x 150 mils (2.794 x 3.810 mm) and a thickness of 20 mils (508 μm).
A lead
is then provided having an outer perimetrical frame portion 80, usually in the ε of a square or rectangle. From the outer portion 80, a predetermined ;ι imber of leads 100 extend inwardly and terminate where the inner ends 110 thereof define a predetermined shape 120. The shape defined by the inner ends 110 of the leads 100 will be substantially similar to the shape of the plateau 30 on the base metal 10 and the shape of the inner perimeter 60 of the first frame layer of dielec' .c material. More specifically, the shape defined by the inner ends 110 of the leads 100 has the same dimensions as the inner perimeter 60 of the first dielectric frame layer. This allows for placing the lead frame flatly on top of the first dielectric frame layer 40 such that the leads extend from beyond the outer perimetrical dimension 50 of this frame layer to, exactly, the inner perimetrical dimension 60 thereof. The lead material can be any conductive material depending upon the desired application with respect to parameters such as impedance, etc. Most preferred by the present inventors is .005 inch (127 μm) thick copper, beryllium-copper alloy, iron-nickel-cobalt alloy or iron-nickel alloy (alloy 42). In the embodiment of FIGURE 1 the leads themselves, individually, are 15 x 5 mils (381 x 127 μm) with spacing between each lead being as small as 10 mils (254 μm). However, the desirable thickness range is from 100 to 250 μm. This thickness range is sufficient to allow the leads to retain their shape in handling and so that they can be formed for matched impedance connection to the board on which the package will be mounted. The length of the leads extending outside of the carrier is also important to the operation of the chip carrier. A minimum distance of .030 inch from the edge of the dielectric material 50 and 140 from which the lead emerges to its termination point 90 after bending is required. Therefore, one must
take into account the thickness of the base plate and the thickness of the first dielectric frame layer 40 along with the type of mounting to be used when determining the length of lead to be used.
Subsequently, a second frame layer 130 of dielectric material is placed upon the leads. The dimensions of the second frame layer 130, referring still to the embodiment in FIGURE 1, are 190 x 230 mils (4.826 x 5.842 mm) outside dimension and 140 x 180 mils (3.556 x 4.572 mm) inside dimension. It will be appreciated that the outside dimension of the second dielectric frame layer is identical to the first frame layer but the inside dimensions differ. A brief review of FIGURE 2 will reveal that this allows for the inner ends 110 of the leads to be exposed for later connection to a chip by beam lead welds or wire bonds. In most cases, the width of the exposed leads are .015 inch, however, the acceptable range is up to .030 inch.
Once all of the components above mentioned are prepared, they are permanently and durably assembled using a direct bonding process. A direct bonding process was chosen as the method of assembly since this process fuses the dielectric in the sheet composites to each other and to the metal used in the package. Fusing the dielectric creates a sufficiently strong bond for reliable use of the product. Moreover, the use of direct bonding eliminates the compromises attendant the use of adhesives. Adhesives raise costs of production to unacceptable levels and they can compromise the thermal and electrical properties of the package. To accomplish the direct bonding, a clamp and a rapid heating/rapid cooling process are used. The purpose of having the temperature change rapidly is to ensure good adhesion between the surfaces and uniform embedding of the leads in the dielectric layers, without producing a lateral flow of material thus distorting the frame and widening the wall. It was determined by the inventors hereof that a 150 psi (1 MPa) pressure, applied by a frictionless clamping force, a rapid rise in temperature to about 388° C, holding the temperature at that level for a period of about 10 to 25 minutes and then rapid cooling was sufficient to embed and seal the leads in the
dielectric material yet avoid deformation of the package. This operation is most preferably executed in an aluminum fixture (not shown) designed to maintain each of the component parts in register. There was significant concern, before positive testing of the bonding method, over whether sufficient material flow would be developed to completely seal and embed the leads and whether there would not also be lateral flow which would distort the frame and widen the wall. Unexpectedly, however, as set forth above, the parameters used did accomplish the required sealing/embedding of the leads and experiments done to ascertain the degree of sealing and embedment revealed that complete embedment and sealing were achieved without unacceptable distortion of the dielectric frame layers.
After bonding and excising of the lead frame, the final chip carrier package is shown gene;, 'y at 132 in FIGURE 3. The above described method of producing the high RF and microwave chip carrier 132 provides a very cost effective and novel product where conductor losses and dielectric losses are both minimal, permittivity is low and conductor dielectric geometry can be designed for matched impedance without resorting to very small lead widths and thicknesses.
One of skill in the subject art will immediately appreciate that the method and basic design parameters of the invention described herein can be used to provide many different kinds and shapes of chip carriers; and by no means is the invention considered to be limited to the exact embodiments disclosed herein. The above description is only the most preferred embodiment and it must be understood that variations are within the scope of this invention.
One variation of significant importance is that the metal base plate 10 can be replaced by the dielectric material which is partially covered (in the area under the die which is the plateau region 30), with a conductive resin, preferably silver-epoxy resin composition. This can be done in the present invention or in prior art packages and can greatly reduce the cost of providing an adequate ground plane for the Gallium arsenide (GaAs) die.
It is also within the ambit of this disclosure to produce multi-layer packages and multi-die packages.
FIGURE 4 is a variation of the preferred embodiment. FIGURE 4 shows five Rf leads 100' and three DC leads 100" ; other than this difference from the embodiment in FIGURE 1 the device is the same. A base plate, first dielectric layer, lead frame and second dielectric layer are all used to form the embodiment of FIGURE 4. The difference is that the leads are shaped differently for impedance matching. This is an example of one of the many alternative lead designs that can be provided. FIGURE 5 depicts an alternative embodiment of the present invention, generally used in connection with direct broadcast satellites, where the raised plateau portion 30 of base metal 10 is smaller than the inner perimetrical dimension 60 of the first dielectric frame layer 40, whereby a gap 67 is formed between the two components in the region where they would normally engage. The gap formed is .005 inch wide and functions to provide flow space for the solder alloy (typically gold-tin eutectic), used to attach the die to the raised plateau, so it does not short circuit the leads.
FIGURE 6 depicts a further embodiment of the invention which is a replacement for a multichip type of chip carrier wherein the overall construction is elongated. Visible in the figure are base plate 10, first dielectric frame layer 40, leads 100 and second dielectric frame layer 130. It should be noted that in this embodiment, no raised plateau region (designated as 30 in other figures) has been provided. This benefits the particular utility of this carrier by allowing layers under the chips; that is, the package is used for a small circuit board already populated with several chips.
FIGURE 7 is a replacement for a conventional Dual-in-line package (DIP) which has been made by the method disclosed and claimed herein. Visible on the edge of FIGURE 7 are base plate 10, first dielectric frame layer 40 and second dielectric frame layer 130; leads are also depicted as 100. The embodiment in this
figure is additionally covered with a metal or dielectric cover layer 170. The chief benefit of such a layer is to protect the package contents from contamination or handling damage. FIGURES 7a, 7b and 7c are similarly numbered and show the different plan views of FIGURE 7. FIGURE 8 depicts yet another embodiment of this invention with the primary difference being that the entire carrier has been placed inside of a separate cover for even greater weather resistance.
In FIGURE 8 a mounting plate 180 is shown in place of base plate 10. Mounting plate 180 laterally extends beyond the chip carrier frame to allow the carrier to be attached to a board with fasteners. ~ The embodiment also includes a top cover 190. This ^πbodiment is generally used for high power applications. FI RES 8a, 8b anc c show the various plan views of FIGURE 8.
While preferred embodiments have been shown and described, various modifications and substitutions may be made thereto without departing from the spirit and scope of the invention. Accordingly, it is to be understood that the present invention has been described by way of illustration and not limitation.
What is claimed is:
Claims
CLAIM 1. Method of making a high radio frequency or microwave chip carrier package comprising the steps of: a) providing a base plate; b) providing a first dielectric frame layer similar in shape and dimension to an outer perimetrical dimension of the base plate and having an open center portion; c) placing said first dielectric frame layer upon the base plate; d) providing a lead frame means, said lead frame including a plurality of leads arranged in a preselected pattern, said leads each having a first end and a second end, said first ends collectively terminating at an outer frame and said second ends terminating at and defining an inner space; e) arranging said lead frame so that said second ends of said leads terminate proximally to the inner perimetrical dimension of the first dielectric layer and so that the leads are supported on said first dielectric frame layer; f) providing a second dielectric frame layer having a shape corresponding to the first dielectric frame layer with an outside perimetrical dimension conesponding to the first dielectric frame layer and an inner perimetrical dimension, which is larger than the inner perimetrical dimension of the first dielectric frame layer; g) stacking the second dielectric frame layer upon the above elements such that said second layer is in line with said first frame layer; h) subjecting all of the aforesaid elements to pressure and elevated temperature in order to bond the base plate, first dielectric frame, lead frame and second dielectric frame; i) separating the outer portion of the lead frame from the leads; whereby a high radio frequency or microwave chip carrier is produced.
CLAIM 2. Method of claim 1 wherein step (h) further includes the step of: maintaining a preselected temperature for a predetermined time period followed by rapid cooling.
CLAIM 3. Method as claimed in claim 1 wherein the base plate is metallic.
CLAIM 4. Method as claimed in claim 1 wherein the base plate is selected from the group consisting of copper, beryllium-copper alloy, brass, iron-nickel alloy, and iron-nickel-cobalt alloy.
CLAIM 5. Method as claimed in claim 1 wherein the base plate is a fluoroplymeric composite with a plating of a electrically conductive composite thereon.
CLAIM 6. Method as claimed in claim 1 wherein the dielectric material is a filled fluoropolymeric material.
CLAIM 7. Method as claimed in claim 5 wherein the dielectric material is Polytetrafluoroethylene.
CLAIM 8. Method as claimed in claim 5 wherein the PTFE is filled with an inorganic filler material.
CLAIM 9. Method as claimed in claim 6 wherein the inorganic filler material is ceramic powder.
CLAIM 10. Method as claimed in claim 7 wherein the ceramic powder is selected from the group consisting of Si02, Ti02 and alumina.
CLAIM 11. Method as claimed in claim 6 wherein the filler material is glass microfiber.
CLAIM 12. Method as claimed in claim 6 wherein the filler material is glass microfiber and ceramic filler.
CLAIM 13. Method as claimed in claim 1 wherein the dielectric material is machined to a predetermined shape using a programmed router.
CLAIM 14. Method as claimed in claim 1 wherein the dielectric material is machined to a predetermined shape using a punch and die set.
CLAIM 15. A method as claimed in claim 1 wherein the lead frame material is selected from the group consisting of copper, beryllium-copper alloy, brass, iron- nickel alloy, and iron-nickel-cobalt alloy.
CLAIM 16. A method as claimed in claim 1 wherein the pressure exerted upon the component parts is by a frictionless clamping device.
CLAIM 17. Method as claimed in claim 16 wherein the pressure exerted is about 150 psi (1 MPa) of pressure.
CLAIM 18. Method as claimed in claim 2 wherein the rapidly rising temperature peaks at about 388° C and remains at that temperature for 10 to 25 minutes.
CLAIM 19. Method as claimed in claim 1 wherein step h includes a rapid heating of the elements.
CLAIM 20. Method of making a high radio frequency or microwave chip carrier package as claimed in claim 1 wherein the base plate also includes a raised plateau which engages with the opening in the first dielectric frame layer.
CLAIM 21. Method of making a high radio frequency or microwave chip carrier package as claimed in claim 1 wherein each layer is prefabricated as an anay of one or more rows and columns joined by webs of the layer materials, to be subsequently severed after a single bonding step to produce many units from one bonding step.
CLAIM 22. A high frequency radio or microwave chip carrier package comprising: a) a base plate; b) a first dielectric frame layer similar in shape and dimension to an outer perimetrical dimension of the base plate and having an open center portion; c) lead frame means having a plurality of leads ananged in a preselected pattern, said leads each having a first end and a second end, said first ends collectively terminating at an outer frame and said second ends terminating at and defining an inner space wherein the second ends terminate proximally to the inner primetrical dimension of the first dielectric frame layer and a portion of said leads proximal to the second ends thereof are supported by the first dielectric frame layer; and d) a second dielectric frame layer with an outside perimetrical dimension conesponding to the first dielectric frame layer and an inner perimetrical dimension which is larger than the inner perimetrical dimension of the first dielectric frame layer; whereafter all of the above elements are stacked in order of appearance and bonded using pressure and high temperature.
CLAIM 23. A high frequency radio or microwave chip carrier package as claimed in claim 22 wherein the base plate is metallic.
CLAIM 24. A high frequency radio or microwave chip carrier package as claimed in claim 22 wherein the base plate is selected from the group consisting of copper, beryllium-copper alloy, brass, iron-nickel alloy, and iron-nick-cobalt alloy.
CLAIM 25. A high frequency radio or microwave chip carrier package as claimed in claim 22 wherein the base plate is a fluoropolymeric composite with a plating of a electrically conductive composite thereon.
CLAIM 26. A high frequency radio or microwave chip carrier package as claimed in claim 22 wherein the dielectric material is a filled fluoropolymeric material.
CLAIM 27. A high frequency radio or microwave chip carrier package as claimed in claim 22 wherein the base plate is a fluoropolymeric composite with a plating of a electrically conductive composite thereon.
CLAIM 28. A high frequency radio or microwave chip carrier package as claimed in claim 22 wherein the PTFE is filled with an inorganic filler material.
CLAIM 29. A high frequency radio or microwave chip carrier package as claimed in claim 22 wherein the inorganic filler material is ceramic powder.
CLAIM 30. A high frequency radio or microwave chip carrier package as claimed in claim 22 wherein the ceramic powder is selected from the group consisting of SI02, TI02 and alumina.
CLAIM 31. A high frequency radio or microwave chip carrier package as claimed in claim 22 wherein the filler material is glass microfiber.
CLAIM 32. A high frequency radio or microwave chip carrier package as claimed in claim 22 wherein the filler material is glass microfiber and ceramic filler.
CLAIM 33. A high frequency radio or microwave chip carrier package as claimed in claim 22 wherein the dielectric material is machined to a predetermined shape using a programmed router.
CLAIM 34. A high frequency radio or microwave chip carrier package as claimed in claim 22 wherein the dielectric material is machined to a predetermined shape using a punch and die set.
CLAIM 35. A high frequency radio or microwave chip carrier package as claimed in claim 22 wherein the lead frame material is selected from the group consisting of copper, beryllium-copper alloy, brass, iron-nickel alloy, and iron-nickel-cobalt alloy.
CLAIM 36. A high frequency radio or microwave chip carrier package as claimed in claim 22 wherein the pressure exerted upon the component parts is by a frictionless clamping device.
CLAIM 37. A high frequency radio or microwave chip carrier package as claimed in claim 22 wherein the pressure exerted is about 150 psi (1 MPa) of pressure.
CLAIM 38. A high frequency radio or microwave chip carrier package as claimed in claim 22 wherein the base plate also includes a raised plateau which engages with the opening in the first dielectric frame layer.
CLAIM 39. A high frequency radio or microwave chip carrier package as claimed in claim 22 wherein each layer is prefabricated as an anay of one or more rows and columns joined by webs of the layer materials, to be subsequently severed after a single bonding step to form many units from one bonding step.
CLAIM 40. A bonded chip carrier package for high frequency radio and microwave applications produced by a process including the steps of: a) providing a base plate; b) providing a first dielectric frame layer similar in shape and dimension to an outer perimetrical dimension of the base plate and having an open center portion; c) placing said first dielectric frame layer upon the base plate; d) providing a lead frame means, said lead frame including a plurality of leads arranged in a preselected pattern, said leads each having a first end and a second end, said first ends collectively terminating at an outer frame and said second ends terminating at and defining an inner space; e) ananging said lead frame so that said second ends of said leads terminate proximally to the inner perimetrical dimension of the first dielectric layer and so that the leads are supported on said first dielectric frame layer; f) providing a second dielectric frame layer having a shape conesponding to the first dielectric frame layer with an outside perimetrical dimension corresponding to the first dielectric frame layer and an inner perimetrical dimension, which is larger than the inner perimetrical dimension of the first dielectric frame layer; g) stacking the second dielectric frame layer upon the above elements such that said second layer is in line with said first frame layer; h) subjecting all of the aforesaid elements to pressure and elevated temperature in order to bond the base plate, first dielectric frame, lead frame and second dielectric frame; i) separating the outer portion of the lead frame fr α the leads; whereby a high radio frequency or microwave chip carrier is produced.
CLAIM 41. Method of making a high radio frequency or microwave chip carrier package comprising the steps of: a) providing a first dielectric frame layer; b) providing a lead frame means, said lead frame including a plurality of leads ananged in a preselected pattern, said leads each having a first end and a second end, said first ends collectively terminating at an outer frame and said second ends terminating at and defining an inner space; c) arranging said lead frame so that said second ends of said leads terminate concentrically with an axis of said first dielectric layer and so that the leads are supported on said first dielectric frame layer; d) providing a second dielectric frame layer having a shape conesponding to the first dielectric frame layer with an outside perimetrical dimension conesponding to the first dielectric frame layer and an inner perimetrical dimension, which is larger than the perimetrical dimension defined by the second ends of the leads; e) stacking the second dielectric frame layer upon the above elements such that said second layer is in line with said first frame layer; f) subjecting all of the aforesaid elements to pressure and elevated temperature in order to bond the first dielectric frame, lead frame and second dielectric frame; g) separating the outer portion of the lead frame from the leads; whereby a'high radio frequency or microwave chip carrier is produced.
CLAIM 42. A high frequency radio or microwave chip carrier package comprising: a) a first dielectric frame layer; b) lead frame means having a plurality of leads ananged in a preselected pattern, said leads each having a first end and a second end, said first ends collectively terminating at an outer frame and said second ends terminating concentrically with the first dielectric frame layer and a portion of said leads proximal to the second ends thereof are supported by the first dielectric frame layer; and c) a second dielectric frame layer with an outside perimetrical dimension conesponding to the first dielectric frame layer and an inner perimetrical dimension which is larger than the space defined by the second end of the leads; whereafter all of the above elements are stacked in order of appearance and bonded using pressure and high temperature.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16275093A | 1993-11-29 | 1993-11-29 | |
| US162750 | 1993-11-29 | ||
| PCT/US1994/012460 WO1995015007A1 (en) | 1993-11-29 | 1994-10-31 | Electronic chip carrier package and method of making thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP0681741A1 true EP0681741A1 (en) | 1995-11-15 |
| EP0681741A4 EP0681741A4 (en) | 1996-06-05 |
Family
ID=22586989
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP95901084A Withdrawn EP0681741A4 (en) | 1993-11-29 | 1994-10-31 | Electronic chip carrier package and method of making thereof. |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0681741A4 (en) |
| JP (1) | JPH08506454A (en) |
| WO (1) | WO1995015007A1 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0870061A (en) * | 1994-08-30 | 1996-03-12 | Mitsubishi Electric Corp | High frequency integrated circuit and its manufacture |
| US6820046B1 (en) * | 1999-01-19 | 2004-11-16 | Texas Instruments Incorporated | System for electrically modeling an electronic structure and method of operation |
| US6639305B2 (en) * | 2001-02-02 | 2003-10-28 | Stratedge Corporation | Single layer surface mount package |
| DE10223035A1 (en) | 2002-05-22 | 2003-12-04 | Infineon Technologies Ag | Electronic component with cavity housing, in particular high-frequency power module |
| US7298046B2 (en) * | 2003-01-10 | 2007-11-20 | Kyocera America, Inc. | Semiconductor package having non-ceramic based window frame |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2423662A1 (en) * | 1973-05-18 | 1974-12-05 | Raytheon Co | SEMICONDUCTOR COMPONENTS, IN PARTICULAR FOR MICROWAVES |
| JPS5933852A (en) * | 1982-08-19 | 1984-02-23 | Toshiba Corp | Manufacture of semiconductor device |
| JPS60251636A (en) * | 1984-05-28 | 1985-12-12 | Nec Kansai Ltd | Semiconductor device |
| GB2174538A (en) * | 1985-04-24 | 1986-11-05 | Stanley Bracey | Semiconductor package |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02174144A (en) * | 1988-12-26 | 1990-07-05 | Sumitomo Electric Ind Ltd | Package for semiconductor device |
| US5258575A (en) * | 1990-05-07 | 1993-11-02 | Kyocera America, Inc. | Ceramic glass integrated circuit package with integral ground and power planes |
| JP2978533B2 (en) * | 1990-06-15 | 1999-11-15 | 株式会社日立製作所 | Semiconductor integrated circuit device |
| US5331511A (en) * | 1993-03-25 | 1994-07-19 | Vlsi Technology, Inc. | Electrically and thermally enhanced integrated-circuit package |
| US5381037A (en) * | 1993-06-03 | 1995-01-10 | Advanced Micro Devices, Inc. | Lead frame with selected inner leads coupled to an inner frame member for an integrated circuit package assemblies |
-
1994
- 1994-10-31 JP JP7515074A patent/JPH08506454A/en active Pending
- 1994-10-31 WO PCT/US1994/012460 patent/WO1995015007A1/en not_active Application Discontinuation
- 1994-10-31 EP EP95901084A patent/EP0681741A4/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2423662A1 (en) * | 1973-05-18 | 1974-12-05 | Raytheon Co | SEMICONDUCTOR COMPONENTS, IN PARTICULAR FOR MICROWAVES |
| JPS5933852A (en) * | 1982-08-19 | 1984-02-23 | Toshiba Corp | Manufacture of semiconductor device |
| JPS60251636A (en) * | 1984-05-28 | 1985-12-12 | Nec Kansai Ltd | Semiconductor device |
| GB2174538A (en) * | 1985-04-24 | 1986-11-05 | Stanley Bracey | Semiconductor package |
Non-Patent Citations (4)
| Title |
|---|
| IEEE/Computer Productivity and Automation, Vol. 10, December 1977, pp. 58-68, J.W. BALDE ET AL.: "New Chip Carrier Package Concepts" XP002000206 * |
| PATENT ABSTRACTS OF JAPAN vol. 10, no. 117 (E-400), 2 May 1986 & JP-A-60 251636 (KANSAI NIPPON DENKI KK), 12 December 1985, * |
| PATENT ABSTRACTS OF JAPAN vol. 8, no. 119 (E-248), 5 June 1984 & JP-A-59 033852 (TOKYO SHIBAURA DENKI KK), 23 February 1984, * |
| See also references of WO9515007A1 * |
Also Published As
| Publication number | Publication date |
|---|---|
| WO1995015007A1 (en) | 1995-06-01 |
| JPH08506454A (en) | 1996-07-09 |
| EP0681741A4 (en) | 1996-06-05 |
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