EP0679221A1

EP0679221A1 - Electronic counting circuit for the timed measurement of a digital signal

Info

Publication number: EP0679221A1
Application number: EP94929459A
Authority: EP
Inventors: Frank-Thomas Eitrich
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 1993-10-26
Filing date: 1994-10-12
Publication date: 1995-11-02
Anticipated expiration: 2014-10-12
Also published as: DE59405643D1; DE4336390A1; EP0679221B1; WO1995012063A1; JP3759605B2; US5684757A; JPH08506401A

Abstract

An electronic counting circuit for the timed measurement of a digital signal of any periodic signal form in which the digital signal consists of a series of grouped periodic events by means of which the time between the input of two events signalling the beginning and end of a given state is to be determined. To this end, a first counter (10) is counted at a rate (t1) maintained by a gatte logic (16) only for the time determined by a first event (E1) and a final event (E4) of a group of events and further events (E2; E3) between said events (E1; E4) are blanked.

Description

Electronic counter circuit for time measurement of a digital signal

The invention relates to an electronic counter circuit for the temporal measurement of a digital signal of any periodic signal form, the digital signal consisting of a series of group-wise periodic events.

State of the art

It is known to use electronic counter circuits in many fields of technology. These serve to quantitatively record a process that is constantly repeated. The counting function is triggered by applying an event-dependent clock frequency to the input of a counter belonging to the counter circuit and counts with an event-independent counting frequency. If one. Event evaluation is to take place, a gate logic upstream, with which individual clock pulses can be specifically hidden. The result of this is that the counter counts correspondingly more slowly and thus an event-dependent evaluation of the counter reading is possible.

When measuring a time length of a signal, it is known to apply a clock signal with a fixed frequency to the input of a counter belonging to a counter circuit. By means of a gate logic, this clock signal is only switched through to the counter during the signal time of interest and is otherwise hidden. The counter therefore does not count while the clock signal is being faded out. If the counter reading is reset to a predetermined reset value during the signal time of no interest, the counter reading corresponds approximately to the length of time of the signal. Without a reset to the reset value, the counter reading difference corresponds to the temporal length of the signal. However, if this known counter circuit is to be used, for example, when measuring a digital signal of any periodic signal form over time, it is disadvantageous that if the counter reading of the counter is to be used for a further evaluation of events determining the duration of the digital signal, particularly short reactions due to a large number of events to be registered are only possible through very extensive circuits or program structures. Advantages of the invention

In contrast, the electronic counter circuit with the features mentioned in claim 1 has the advantage that a temporal measurement of a digital signal of any periodic signal form is possible with simple circuit modules that are easy to implement. The fact that a first counter is counted with a counting clock, which is put through a gate logic only for the time determined by a first event and a last event of an event group, and further events lying between these events are masked out very advantageously possible after a. First synchronization of the counter circuit automatically processes almost every periodic digital signal without further intervention after initialization and at the same time, even in the event of faulty signals, indicate a current counter reading which corresponds to the actual length of the digital signal currently being applied. The counter reading of the counter can advantageously be stored so that when a next time length of a digital signal is determined, it can be tapped for further control functions. Overall, this simplifies the electronic counter circuit, since the display and further processing of the counter reading are largely freed from real-time-critical tasks that require a particularly short response time. Further advantageous embodiments of the invention result from the other features mentioned in the subclaims.

drawing

The invention is explained in more detail below in exemplary embodiments with reference to the associated drawings. Show it:

1 shows an overview of a possible digital signal;

FIG. 2 shows a block diagram of a time measurement of a digital signal;

Figure 3 is a block diagram of a first embodiment of Figure 2;

Figure 4 is a block diagram of a second

Design variant of Figure 2 and

FIG. 5 shows a block diagram of a third embodiment variant of FIG. 2.

Description of the embodiments

In FIG. 1, the example of a segment encoder shows a camshaft of a six-cylinder internal combustion engine, the possible course of a digital signal. A segment signal transmitter is arranged on a camshaft of the internal combustion engine, that has segments distributed over the circumference. An event period P is shown, within which a certain number of events E is detected. Events E are generated by positive and negative edges of the segments arranged on the sensor wheel by means of a suitable sensor detection. Each of the six cylinders ZI to Z6 is assigned a segment or a segment gap on the encoder wheel. The first cylinder ZI is characterized by the assignment of events E1 to E4. This means that a signaling of the occurrence of the event E1 can trigger a control, not shown here, for example an ignition control, which relates to the cylinder ZI. The cylinder Z2 is characterized in the same way by the event E4 and E5 and the other cylinders by the corresponding events caused by the segments. The events to be assigned to each cylinder form an event group. Since both the 360 ° and the 720 ° angle of the camshaft must be observed in the engine control system, at least one intermediate event must be detected in at least two segments or segment gaps assigned to the cylinders, here E2 and E3, so that the 360 ° or 720 ° angle can be distinguished. Since the events E2 and E3 are only necessary for certain control purposes, as already mentioned, it is necessary to hide them between the events E1 and E4, for example in a segment time measurement. If events E2 and E3 were not hidden, the digital signal curve marked here with S would be evaluated. It is therefore not possible to assign a segment time length to the associated cylinder. In the further explanation of the electronic counter circuit, reference is now made to the sequence of events E shown by way of example in FIG. 1.

FIG. 2 shows an electronic counter circuit which has a counter 10 which is counted with a counting cycle C2 at the input 12. The counting cycle C2 is generated by a counter 14, which is counted with a counting cycle to dependent on the number of events E, and a gate logic 16 and an external counting cycle t1. It is thus achieved that, by influencing the control signal C1, the counter 10 experiences a certain change in the counter reading of its counter reading Q2, so that the known external counter clock t1 and the difference between the counter reading Q2 at the beginning of the control signal Cl and at the end of the Control signal Cl can be inferred to the time in which the control signal Cl is present.

The counter 14 counts the events E, starting with an external synchronization signal t3. The external synchronization signal t3 can be taken at the same time as the event El by suitable measures on the segment sensor wheel of the camshaft. can be detected. The synchronization signal t3 sets the counter 14 to a reset value, which is preferably zero. Starting from this reset value, the counter 14 begins to count the number of events during the event period P. The number of expected events E during the event period P is known to the counter 14 as the value D1. The counter state of the counter 14 is read into the gate logic 16, which provides the counter clock C2 as a function of the counter state. Since the counting cycle C2 is only to be present for the time in which the digital signal S is to be present for a cylinder Z or thus a segment, events E2 and E3 are to be masked out in the example shown in FIG.

A variant of the suppression of events E2 and E3 is illustrated in FIG. The same parts as in FIG. 2 are provided with the same reference symbols and are not explained again here. The number of expected events E are made available by a register 18 in the form of the value D1 to the counter 14. The counter 14 begins with the synchronization signal t3 to count the number of events E, which is predetermined by the clock frequency tO. The counter reading Q1 of the counter 14, which changes with each occurrence of a next event E, is transferred to a table 20. Table 20 is designed, for example, as a read-only memory or programmable memory. The expected events E1 to En are stored in the table, the table 20 being set up in such a way that it knows that the Event E1 is the beginning of the segment to be assigned to cylinder 1 and event E4 is to be assigned the end of the segment to cylinder 1 and the beginning of the segment to cylinder 2. In this form, each of the expected events E within the event period P is encoded in table 20. Since the counter reading Q1 of the counter 14 changes depending on the occurrence of the next event E, the table 20 can assign each counter reading Ql to the corresponding segment of a cylinder Z. As a result, table 20 provides a control signal C1 which corresponds exactly to the length in which a segment to be assigned to a cylinder Z is detected by the sensor providing events E. The gate logic 16 then forms the counter clock C2 from the external counter clock T1 and the control signal C1, so that the counter 10 runs through a range of values in accordance with the information given to the control signal C1. The range of values passed through is then available as counter reading Q2 and can be used, for example, for a cylinder-dependent control, in particular an ignition-time control, or a valve control. Cyclic repeatability of the time measurement of the individual segments within the event period P is ensured via the synchronization signal t3 and the register 18. Due to the known value D1 of the expected events from the register 18, it is possible to switch the electronic counter circuit only once with the synchronization signal t3 act, since the counter 14 automatically resets to its reset value, preferably the value zero, when the expected number of events is reached.

FIG. 4 shows a further variant of a possibility of masking out the events E2 and E3 which are not required for a segment time determination. The same parts as in Figure 1 are again provided with the same reference numerals and not explained again. The table 20 is replaced here by a relative memory 22, which takes over the function of the table 20 and a comparator 24 at the same time, that is, assigns the changing counter reading Q1 of the counter 14 to the respective segments of the cylinders Z. This makes it possible to dispense with the synchronization signal t3.

According to a further embodiment variant, not shown in FIGS. 3 and 4, it is possible to link the clock to, which depends on the occurrence of the events E, with the counter clock C2, so that the table 20 or the relative memory 22 always shows the behavior of the counter 10 predetermined at the next expected event E. This makes it possible to make the timing behavior of the table 20 and the gate logic 16 or of the relative memory 22 and the gate logic 16 very uncritical, so that slower logic and subcircuits can also be used. FIG. 5 shows a further variant of masking out the events E2 and E3 which are not required for determining the segment time. The value D1 of the number of expected events E is provided here from a table 26, into which the counter reading Q3 of a counter 28 is read. Table 26 informs counter 14 of the number of events E to be omitted in the counting cycle to which is dependent on the occurrence of events E. The counter 14 thus counts the events to be omitted internally, without changing its counter reading Q1, and changes it only when the corresponding number of events has been omitted. The counter 28 is fed back by a control signal C3 so that it can change its counter reading Q3 according to the number of events E that have actually occurred. The number of expected events within an event period P or an event group is read into counter 28 as value D3 from a register 30. The counter 28 counts the event group and uses the counter reading Q3 in the table 26 to tell how many events are to be omitted in the event group currently present. This variant ensures that the counter 10 is controlled jointly by the counters 14 and 28, in that the counting cycle C2 depends on their current counter status Q1 or Q3.

In the variants shown in FIGS. 3 to 5, the circuit complexity for tables 20 and 26 is proportionally dependent on the number of Events E per event period P or from the number of time measurements, that is to say the segments per event period P. This circuit complexity can be reduced by the fact that in the case of a seamless time measurement between the individual segments, that is to say event E4 in the example shown, the end of indicates the segment to be assigned to cylinder 1 and indicates the beginning of the segment to be assigned to cylinder Z2, which triggers the end of the first measuring process immediately the beginning of the next measuring process. The counter reading Q2 of the counter 10 which is displayed at the end of each segment can optionally be temporarily stored for further evaluations, or the counter readings Q2 at the end of each segment can be accumulated.

Overall, it is clear that the circuits shown in FIGS. 2 to 5 can process each periodic digital sensor signal S independently without further intervention after an initial initialization by the synchronization signal t3. By means of the plausibility checks by the table 20 or the relative memory 22, a large part of the possible signal errors can be filtered out from the event clock tO and the synchronization signal t3. Faulty signals that reach the counter circuit despite the plausibility check do little damage, since individual errors are corrected by register 18 or 30 at the latest after the next synchronization. Furthermore, a rapid detection of a possible failure of the event clock tO is complete a resulting counter overflow of the counter 10 is possible.

The invention can be used, for example, in the following two applications.

In the first application, the external counting clock tl is used to count at a predetermined frequency, with the count Q2 corresponding to the length of time of this segment at the end of each segment ZI, Z2, ..., Z6 (see FIG. 1).

In the second application, the gate logic 16 is modified so that the counter clock C2 is varied such that the counter 10 reaches a predetermined value at the end of each segment ZI, Z2, ..., Z6 (cf. FIG. 1). This counting cycle is regulated according to the known PLL principle (phase locked loop).

Claims

claims

1. Electronic counter circuit for temporal measurement of a digital signal, any periodic signal form, the digital signal consisting of a series of group-wise periodic events, characterized in that a first counter (10) is counted with a counting clock (tl) which is put through by a gate logic (16) only for the time which is determined by a first event (El) and a last event (E4) of an event group and further events (E2; E3) between these events (El; E4) are hidden become.

2. Electronic counter circuit according to claim 1, characterized in that the gate logic (16) has means which put through the counting clock (tl) in a division ratio to the first counter (10), so that for each event (El; E2; E3 ,, ..) a predetermined counter reading (Q2) of the first counter (10) is reached.

3. Electronic counter circuit according to one of the preceding claims, characterized in that the counter reading (Q2) of the counter (10) with each last event (E4) of an event group is temporarily stored in a register.

4. Electronic counter circuit according to one of the preceding claims, characterized in that the counter (10) is set to a reset value, preferably zero, with a synchronization event (t3).

5. Electronic counter circuit according to one of the preceding claims, characterized in that the gate logic (16) is assigned a second counter (14) which counts the number of events (E) during an event period (P) and each event group.

6. Electronic counter circuit according to one of the preceding claims, characterized in that the second counter (14) the number of events to be expected (E) is known.

7. Electronic counter circuit according to one of the preceding claims, characterized in that the number of events (E) corresponding counter reading (Ql) of the second counter (14) is checked by a table (20) that only the through the first and last events (El; E4) of each event group.

8. Electronic counter circuit according to one of the preceding claims, characterized in that the table (20) is formed as a read-only memory.

9. Electronic counter circuit according to one of the preceding claims, characterized in that the table (20) is designed as a programmable memory.

10. Electronic counter circuit according to one of the preceding claims, characterized in that the table (20) is formed as a relative memory (22).

11. Electronic counter circuit according to one of the preceding claims, characterized in that the second counter (14) is assigned a third counter (28) which counts the number of event groups and whose counter reading (Q3) is loaded into a table (26), which notifies the second counter (14) of the number of events (E) to be omitted from the event group just counted.

12. Electronic counter circuit according to one of the preceding claims, characterized in that the events (E) are generated by an angle encoder and correspond to cyclic angle information of an aggregate.

13. Electronic counter circuit according to one of the preceding claims, characterized in that the unit is the camshaft of an internal combustion engine.

14. Electronic counter circuit according to one of the preceding claims, characterized in that the unit is the crankshaft of an internal combustion engine.

15. Electronic counter circuit according to one of the preceding claims, characterized in that the electronic counter circuit is used in a control unit of an internal combustion engine for emulating the camshaft.

16. Electronic counter circuit according to one of the preceding claims, characterized in that the electronic counter circuit is used in a control unit of an internal combustion engine for emulating the crankshaft.