EP0668557B1 - Data reorganization circuit and method - Google Patents

Description

The present invention relates to circuits allowing to provide data in a second predetermined order arriving at the circuit in a predetermined first order.

Such circuits generally use a memory to dual access, i.e. a memory in which you can write using an input bus and a first address bus and in which we can read, practically simultaneously with writes, using an output bus and a second bus addresses.

In classic data reorganization circuits, we start by filling the memory according to a first order before starting to empty it in a second order. In effect, since the data entry and exit orders are generally distinct and arbitrary, we do not know, at the time where we want to read a data, if the latter has effectively been written. So, a disadvantage of such a circuit is that it has a response delay, or latency, equal to number of write cycles it takes to fill memory.

An object of the present invention is to provide a dual access memory reorganization circuit, which authorizes the reading of the memory at the precise moment when at less data that can be read is present in the memory.

By achieving this object, the invention allows, according to the data entry and exit orders, read data in memory before it is filled.

This object is achieved thanks to a reorganization process data, including the steps of writing data in a dual access memory in a predetermined first order and read the data into memory in a second predetermined order. Each time a current data is written, a register is incremented by an increment whose optimal value equals 1 plus the difference between the entry rank of the data and the output rank of this data, and zero if the difference is negative, the actual value of this increment being such that the sum of the increments used until writing of the current data is less than or equal to the sum optimal values of these increments. Reading data is allowed only if the content of the register is not zero and the register is decremented on each reading.

According to an embodiment of the present invention, the method comprises the step of prohibiting the writing of data between the time when writing a data packet ends and the instant when the reading of this data packet ends.

The present invention also relates to a circuit for data reorganization, including dual access memory coupled to a system to write data in a first predetermined order using a first bus and to read these data in a second predetermined order using a second bus. A register is connected to the circuit to authorize memory reads only if the contents of the register is not zero. Means are provided to decrement the content of the register each time a data item is read from memory. A address decoder on the first bus provides a increment whose optimal value is equal to 1 plus the difference between the input rank of the current data presented on the first bus and the output rank of this data, and zero if the difference is negative, the actual value of this increment being such that the sum of the increments used until writing of the current data is less than or equal to the sum optimal values of these increments. A summator adds the increment in the content of the register with each writing.

According to an embodiment of the present invention, the circuit includes a write counter incremented at each writing of a data and reset to zero at the end of each reading of a data packet, and means to inhibit writes as long as the write counter is at its maximum value.

la figure 1 représente un mode de réalisation schématique d'un dispositif de réorganisation de données selon la présente invention ;

la figure 2 représente un chronogramme permettant d'illustrer le fonctionnement du circuit de la figure 1 ;

la figure 3 représente un macrobloc d'une image numérique constituant des données pouvant être traitées par un circuit de réorganisation selon l'invention ;

la figure 4 représente une insertion d'un circuit de réorganisation selon l'invention dans une chaíne de traitement de données d'image comprimées selon une norme MPEG ;

les figures 5A à 5D servent à illustrer quatre types de réorganisation effectués par un circuit selon l'invention dans le cadre d'un traitement de macroblocs d'image comprimés selon une norme MPEG ; et

la figure 6 représente un mode de réalisation de mémoire à double accès particulièrement avantageux dans le domaine du décodage MPEG.

These objects, characteristics and advantages as well as others of the present invention will be explained in the following description of particular embodiments given without limitation by means of the attached figures, among which:

Figure 1 shows a schematic embodiment of a data reorganization device according to the present invention;

2 shows a timing diagram to illustrate the operation of the circuit of Figure 1;

FIG. 3 represents a macroblock of a digital image constituting data which can be processed by a reorganization circuit according to the invention;

Figure 4 shows an insertion of a reorganization circuit according to the invention in a processing chain of compressed image data according to an MPEG standard;

FIGS. 5A to 5D serve to illustrate four types of reorganization carried out by a circuit according to the invention within the framework of a processing of image macroblocks compressed according to an MPEG standard; and

FIG. 6 represents an embodiment of dual access memory which is particularly advantageous in the field of MPEG decoding.

In FIG. 1, data to be reorganized are written in a dual-access memory 10 by a write bus DW. The write addresses of this data are selected by a bus WA write addresses. Data written to memory 10 are read on a DR read bus at selected addresses by an RA read address bus. Each writing in memory 10 is validated by a write clock W, and each reading is validated by a reading clock R.

In the example in Figure 1, the write addresses WA and the RA read addresses are supplied by a circuit command 12 which determines the reorganization of the data. Through example, the write addresses WA are incremented by unit as we write the data and the RA read addresses vary in any fixed manner for determine the reading (or output) order of the data that are written to memory 10.

Generally, the data is reorganized by packets of constant length. The memory 10 is for example intended to contain a data packet and addresses of writing WA and reading RA evolve according to sequences of period equal to the number of data in a packet.

The problem which the invention aims to solve is the synchronization of the transmission of RA read addresses on the emission of write addresses WA so as to read a given as soon as his exit turn has arrived.

For this, the invention provides a register 14 which contains the number N of data available for reading in the memory 10, i.e. the number of data that can be read in the correct order. This number N is updated each time writing data into memory 10 by adding to the number N an increment X. For this, for example, register 14 is validated by the write signal W and the input of the register 14 receives, via an adder 16, the sum of the output of the register and of the value X (WA) supplied by a decoder 18. The decoder 18 associates an X value with each write address WA. Each increment X is equal to 1 plus the difference between the input rank of the data currently written and the rank output of this same data. If this difference is negative, the increment X is zero.

The values of the increments X as defined above are optimal values X _opt . For the circuit to function, it suffices that the sum of the increments used up to the data currently written is less than or equal to the sum of the corresponding optimal increments. In any case, the total sum of the X increments used for a data packet is equal to the number of data in the packet.

The content of register 14 is decremented by one to each reading in memory 10. For this, we supply by example the read signal R at a decrementing input of the register 14. Register 14 can be a down counter receiving the read signal R on a decrementing input, the signal W on a load validation input, and the output of the adder 16 on a loading input.

The control circuit 12 receives the content of the register 14 to determine the activation of control signals RDYW and RDYR. The RDYW signal is used to indicate to a circuit of writing, not shown, that the reorganization circuit is ready or not to receive data. If the RDYW signal is activated, the write circuit successively activates the signal writing W as it presents the data on the DW bus. The write addresses WA are incremented by the control circuit 12 at the rate of the write signal W.

The RDYR signal is used to indicate to a read circuit, not shown, that the reorganization circuit is ready or not to provide data. When the RDYR signal is active, the reading circuit successively activates the reading line R as it reads the data on the bus DR. Each time the read signal R is activated, the command 12 changes the RA read address to provide the data read in the correct order. The succession of addresses RA reading is predefined according to the order in which we want to read the data in memory 10. These addresses are for example stored in a memory addressed by a counter which is incremented by the read signal R.

The RDYR signal is active when the number N contained in register 14 is not zero. So the RDYR signal is by example provided by an OR gate receiving all the bits of the register 14.

The RDYW signal is active as soon as a data packet has was extracted from memory 10. To generate this RDYW signal, we uses, for example, a 12-1 write counter that counts the number of data written to memory 10. The RDYW signal is for example supplied by an RS flip-flop, not shown, set to 0 when the number of data written NW is equal to the number of data of a packet, and set to 1 if the number N of data available in memory 10 is zero and the number of data written NW is equal to the number of data in a packet. Activation of the RDYW signal sets the number of data written NW to 0.

FIG. 2 represents a timing diagram illustrating the operation of the circuit of FIG. 1 using an example of reorganization of packet of eight data 1 to 8. In this example, the data are to be written according to the succession:
1, 2, 3, 4, 5, 6, 7, 8
and the data must leave memory 10 according to the succession:
2, 1, 4, 3, 5, 8, 6, 7.
Thus, the output ranks of words 1 to 8 are respectively:
2, 1, 4, 3, 5, 7, 8, 6.

The X values associated with each written data are
0, 2, 0, 2, 1, 0, 0, 3.

At an instant t ₀ , the memory 10 is empty, the number N is zero and the signal RDYW is activated. The write signal W is then successively activated to write the eight data in the memory 10.

The number N is zero until we write the data 2, i.e. data of input rank 2 and rank output 1. The number N is then incremented by 2 and the signal RDYR is activated, which causes successive activations of the read signal R to read data from memory 10 by example, at the frequency of the write signal. We first read the data 2, the number N goes to 1, then data 1, the number N goes to 0, causing the RDYR signal to be deactivated.

When data 4 is written in memory 10, the number N is incremented by 2, this increment occurring in the example of figure 2 when the number N has become zero after reading data 1. RDYR signal is again activated and data reading resumes.

We read data 4, the number N goes to 1, then we read data 3. In the meantime, we wrote data 5 and the number N has been incremented by 1. At the time of reading data 3, the number N goes to 1, we read the data 5, the number N goes to 0 by deactivating the RDYR signal.

The number N is incremented by 3 when writing the data 8, the last data in the package. The RDYW signal is deactivated and the RDYR signal is activated. We read successively data 8, 6 and 7, the number N going to 2, then to 1 and finally at 0.

When data 7 has been read, memory 10 is empty. The RDYW signal is activated again, which allows the writing of a new packet of eight data.

We observe that the latency time of the reorganization circuit according to the invention, that is to say the offset between the end of writing a package and the end of reading it is three read cycles, which corresponds to the maximum value increment X.

Of course, a reorganization circuit according to the invention can be provided for carrying out several reorganizations that we choose thanks to a FCT bus (figure 1) which determines the decoding function of decoder 18 and the function for generating reading addresses RA of the control circuit 12.

A reorganization circuit according to the invention is particularly useful for filtering in coding or decoding of picture blocks according to MPEG standards. In such coding or decoding circuits, the data is processed by this so-called macroblocks corresponding to blocks image size of 16x16 pixels.

Figure 3 illustrates an example format, noted 4: 2: 0, of an MPEG macroblock. This macroblock includes a luminance block formed of four blocks Y0 to Y3 of 8x8 pixels and a chrominance block formed of two blocks U and V of 8x8 pixels. Another possible format is the format noted 4: 2: 2 where the chrominance block includes two 8x16 pixel blocks. A macroblock of the format 4: 2: 0 consists of a packet of 384 pixels of 8 bits.

Figure 4 schematically represents part of MPEG decoder circuit performing macroblock filtering. A commonly decoded macroblock MBc is supplied to a circuit inverse discrete cosine transform (DCT) 20.

The output of circuit DCT 20 is summed by a adder 22 at the output of a filter 24, called a half-pixel filter, to obtain a reconstructed macroblock MBr. The filter 24 receives MBp macroblocks, called predictive macroblocks, from of a previously reconstructed image. Arrival order pixels at filter 24 is different from the output order of pixels of the DCT circuit. Therefore, it is necessary to provide for the output of the filter 24 a reorganization circuit 26 which is advantageously a reorganization circuit according to the invention. The write signal W and the signal RDYW are exchanged between the circuit 26 and the filter 24. The read signal R and the signal RDYR are exchanged between circuit 26 and DCT circuit 20.

The data provided by filter 16 and by the DCT circuits are on 16 bits, each corresponding to a pair pixels.

In addition, the DCT circuit provides macroblocks under interlaced or progressive form regardless of whether the predictor macroblocks provided to filter 24 can also be supplied in interlaced or progressive form. So, we have four possible reorganization possibilities which are selected by the FCT bus.

FIGS. 5A to 5D are intended to illustrate examples of each of these reorganizations. They represent tables of the X increments associated with each pair of pixels of a macroblock written in the memory 10 of the reorganization circuit. These figures are considered to be an integral part of this description.

FIG. 5A illustrates a reorganization of macroblocks in the case where the macroblocks are supplied by the filter 24 under progressive form and supplied to adder 22 also under progressive form.

The pairs of pixels supplied by the filter 24 arrive, for example, by columns of 16 pairs of pixels by scanning from top to bottom and from left to right, first the blocks of luminanoe Y then the chrominance blocks U and V. More precisely, the luminance blocks Y arrive by alternating a column of block Y0 and a column of block Y2 then, once the blocks Y0 and Y2 arrived, alternating a column from block Y1 and a column from block Y3. The chrominance blocks U and V arrive by alternating a pair of pixels U and a pair of pixels V. The pairs of pixels are written in the circuit of reorganization in their order of arrival.

Pixel pairs are read back, for example, by columns of 8 pairs of pixels from top to bottom and from left to right, so as to supply completely successively blocks Y0, Y1, Y2, Y3, U and V, which is partially illustrated by arrows.

It can be seen in the table of FIG. 5A that the greatest value of X is 57, which means that the latency of the reorganization circuit is, in this case, 57 cycles of read on 192 pairs of written pixels.

FIG. 5B represents a reorganization of macroblocks in the case where the macroblocks are supplied in the form progressive by the filter 24 while the adder 22 receives in interlaced form. Pixel pairs are written in the reorganization circuit 26 in the same way as above.

The pairs of pixels are read in columns of so as to provide the pairs of pixels of odd lines of successive blocks Y0, Y2, Y1, Y3, then the pairs of pixels of even lines of successive blocks Y0, Y2, Y1, Y3. Blocks of chrominance are replayed in the same way as in the case of the Figure 5A.

Note that the latency in this case is 64 reading cycles.

Figure 5C illustrates a reorganization in the case where the filter 24 provides macroblocks in interleaved form and where they are supplied to the adder 22 in progressive form.

The pairs of pixels supplied by the filter 24 arrive in columns of 8 pairs of pixels by scanning from top to bottom and from left to right the odd luminanoe blocks (Y0 (1) to Y3 (1)), the even luminance blocks (Y0 (2) to Y3 (2)), the odd chrominance blocks (U (1) and V (1)), and finally the blocks chrominance pairs U (2) and V (2). An odd block, affected by (1), contains only the pairs of pixels of odd lines of the corresponding complete block and an even block, assigned with (2), does not contains only the pairs of pixels of even rows of the block complete matching. Each of the odd and even blocks (of luminance and chrominance) happens in the same way as the corresponding complete block in Figure 5A, except that each odd or even block contains only 4 pairs of pixels in its columns.

Pixel pairs are re-read to provide by columns of 8 pairs of pixels successively the blocks complete Y0, Y1, Y2, Y3, U and V. The reading order is partially represented by surrounded numbers. For example, for reconstitute the first column of the YO block, we read the first to fourth pairs of pixels alternately in blocks Y0 (1) and Y0 (2). The blocks U and V are reconstructed so similar.

Note that the latency of the reorganization circuit in this case is 58 read cycles.

Figure 5D illustrates a reorganization in the case where the filter 24 provides macroblocks in interlaced form which must be supplied to adder 22 in interleaved form.

The blocks are written in the reorganization circuit according to what has been described in relation to FIG. 5C and are replayed in the same order. In fact, the reorganization circuit is not useful in this case. All X increments are at 1 and the latency is one read cycle.

In this application to a processing circuit MPEG, as for the general case, the reorganization circuit forbidden to start writing a new data packet (new macroblock) until the previous package has been read. Thus, data cannot be provided in stream continuous in the reorganization circuit.

A classic solution to avoid this drawback would consist in using a buffer memory preceding the circuit reorganization, the capacity of which corresponds to the number of data written during the latency of the reorganization circuit.

MPEG processing is particularly suitable for the use of two reorganization circuits according to the invention connected in parallel to process the pixels to be written in continuous flow. For example, the first reorganizes the blocks of luminance Y0 to Y3, and the second the chrominance blocks U and V, which is easy to predict because the luminance and chrominance correspond to well differentiated packets (the chrominance pixels are not mixed with the luminance pixels, both in and out). The memory used then corresponds to a macroblock and there is no need to increase this memory by adding a buffer memory.

FIG. 6 represents a particularly embodiment advantage of dual access memory to use in a reorganization circuit according to the invention adapted to a MPEG image processing. This memory includes 12 memories 16-word first-in / first-out (FIFO) buffer 16 bits each. The DW write bus is connected to all inputs of these FIFO memories and the read bus DR is connected to all the outputs of these FIFO memories. The address bus writing WA includes, for example, 12 lines selecting each of the FIFO memories in write mode, and the address bus of RA reading includes, for example, 12 lines selecting each of the FIFO memories in read mode.

Each of the FIFO memories is intended to contain the pairs of pixels of even rank or pairs of pixels of rank odd of each 8x8 pixel block of a macroblock. Of this way, the pixel pairs can be provided in the correct order in each of the four cases previously described using a particularly simple addressing and a structure of inexpensive dual access memory.

Claims (4)

1. A data reorganization process, including the following steps:

   writing words in a dual-port memory (10) in a first predetermined order;

   reading-out the words from the memory in a second predetermined order;

   characterized in that it comprises the following steps:

   each time a current word is written, incrementing a register (14) by an increment (X) whose optimum value is equal to 1 plus the difference between the input rank of the word and the output rank of this word, said increment being zero if the difference is negative, the effective value of said increment being such that the sum of the increments that are used until the current word is written is lower than, or equal to, the sum of the optimum values of these used increments;

   authorizing reading of the words only if the content of the register is non-zero; and

   decrementing the register at each read.
2. The reorganization process of claim 1, characterized in that it includes the step of inhibiting the writing of words between the time when the writing of a packet of words is ended and the time when the reading of this packet is ended.
3. A data reorganization circuit, including a dual-port memory (10) coupled to a system to write words in a first predetermined order with a first bus (DR, WA) and to read said words in a second predetermined order with a second bus (DR, RA), characterized in that it comprises:

   a register (14) connected to the reorganization circuit to authorize the reading of the memory only if the content of the register is non-zero;

   circuitry (R) for decrementing the content of the register each time a word is read in the memory;

   a decoder (18) for decoding addresses present on the first bus to provide an increment (X) whose optimum value is equal to 1 plus the difference between the input rank of the current word provided on the first bus and the output rank of this word, and whose value is zero if the difference is negative, the effective value of this increment being such that the sum of the increments used until the writing of the current word is lower than, or equal to, the sum of the optimal values of these used increments; and

   an adder (16) for adding the increment to the content of the register at each write.
4. The reorganization circuit of claim 3, characterized in that it includes a write counter (12-1) that is incremented each time a word is written, and reset at the end of each reading of a packet of words, and circuitry for inhibiting writing as long as the write counter is at a maximum value.

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