Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B7/00—Radio transmission systems, i.e. using radiation field
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04H—BROADCAST COMMUNICATION
  • H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
  • H04H20/65—Arrangements characterised by transmission systems for broadcast
  • H04H20/67—Common-wave systems, i.e. using separate transmitters operating on substantially the same frequency

Definitions

• This invention relates in general to simulcast transmission systems, and more particularly to a method and apparatus for synchronizing transmissions of a simulcast transmission system.
• a number of methods have been proposed or are in use today for automatically synchronizing the message transmissions of transmitters utilized in simulcast transmission systems.
• One such method includes a master transmitter centrally located within a plurality of secondary transmitters disposed in an annular fashion around the central transmitter. The innermost annular ring of transmitters was synchronized to the master transmitter, while the remainder of the system transmitters were disabled. The next adjacent annular band of transmitters was then synchronized to the innermost annular band and the process was repeated until every annular band in the system was synchronized.
• Such a synchronizing arrangement guaranteed that adjacent annular bands were properly synchronized, however, such a system cannot estimate the variations in delay which were introduced because a common signal source for making the delay measurements was not used.
• the propagation delay times must be measured for the plurality of transmitters in order to account for propagation delay differences, however ,even when the delays are measured, jitters received at each transmitter resulted in indecisiveness in locating bit edges. That is, although the bit widths were restored to their proper duty cycle, the simulcast bit synchronization will be less than the accuracy required because of uncertainty in locating the bit edges at the transmitters.
• synchronized clocks were incorporated at the plurality of transmitters.
• the data to the plurality of transmitters was sent faster than real time transmission on a narrow band radio frequency (RF) channel and when the data was received, it was stored in buffers at each of the plurality of transmitters until it was time for the simulcast transmission of the stored data.
• the synchronized clocks at the plurality of transmitters are required to be extremely accurate, and when all the synchronized clocks indicated a predetermined time, the data was simultaneously transmitted by the plurality of base sites. The problem of jitters was removed because the data was locally generated at the plurality of transmitters.
• a simulcast system has a transmitter controller capable of measuring propagation delays to a plurality of base sites and calculating propagation delay differences from the measured propagation delays for each of a plurality of base sites.
• the transmitter controller also receives and transmits data to each of the plurality of base sites.
• the plurality of base sites have transmitters capable of transmitting data as radio frequency transmission at substantially the same time.
• the transmitter controller comprises a transmitter which transmits the propagation delay differences, and a start command to the plurality of base sites for initiating simulcast retransmission of the data.
• the plurality base sites comprise receivers which receive the propagation delay differences, the propagation delay differences being determined for delaying the retransmission of data in each of the plurality of base sites.
• the base site receivers receive data from the transmitter controller to be retransmitted by the plurality of base sites.
• a memory at the base site stores the received data and the base site receivers receive the start command.
• a timer delays retransmission of the stored data from the receipt of the start command by the propagation delay difference calculated for each base site to enable the retransmission of the data at substantially the same time by the plurality of base sites.
• a method for synchronizing data transmissions in a simulcast system comprising a plurality of base sites coupled to a transmitter controller capable of measuring propagation delays from the transmitter controller to the plurality of base sites and calculating propagation delay differences for each of the plurality of base sites, the transmitter controller capable of receiving and transmitting data to each of the plurality of base sites, the plurality of base sites capable of transmitting data as radio frequency transmission at substantially the same time, the method comprising the steps of:
• FIG. 1 is an electrical block diagram of a data transmission system in accordance with the preferred embodiment of the present invention.
• FIG. 2 is an electrical block diagram of a terminal for processing and transmitting message information in accordance with the preferred embodiment of the present invention.
• FIGS. 3-5 are timing diagrams illustrating the transmission format of the signaling protocol utilized in accordance with the preferred embodiment of the present invention.
• FIGS. 6 and 7 are timing diagrams illustrating the synchronization signals utilized in accordance with the preferred embodiment of the present invention.
• FIG. 8 is an electrical block diagram of a data communication receiver in accordance with the preferred embodiment of the present invention.
• FIG. 9 is an electrical block diagram of a threshold level extraction circuit utilized in the data communication receiver of FIG. 8.
• FIG. 10 is an electrical block diagram of a 4-level decoder utilized in the data communication receiver of FIG. 8.
• FIG. 11 is an electrical block diagram of a symbol synchronizer utilized in the data communication receiver of FIG. 8.
• FIG. 12 is an electrical block diagram of a 4-level to binary converter utilized in the data communication receiver of FIG. 8.
• FIG. 13 is an electrical block diagram of a synchronization correlator utilized in the data communication receiver of FIG. 8.
• FIG. 14 is an electrical block diagram of a phase timing generator utilized in the data communication receiver of FIG. 8.
• FIG. 15 is a flow diagram illustrating the synchronization correlation sequence in accordance with the preferred embodiment of the present invention.
• FIG. 16 is an electrical block diagram of a simulcast system for processing and transmitting information in accordance with the preferred embodiment of the present invention.
• FIG. 17 is a flow diagram illustrating the synchronization sequence for synchronizing the plurality of base sites in accordance with the preferred embodiment of the present invention.
• FIG. 1 is an electrical block diagram of a data transmission system
• a data transmission system 100 such as a paging system, in accordance with the preferred embodiment of the present invention.
• messages originating either from a phone, as in a system providing numeric data transmission, or from a message entry device, such as an alphanumeric data terminal are routed through the public switched telephone network (PSTN) to a paging terminal 102 which processes the numeric or alphanumeric message information for transmission by one or more transmitters 104 provided within the system.
• PSTN public switched telephone network
• the transmitters 104 preferably in simulcast, transmit the message information to data communication receivers 106. Processing of the numeric and alphanumeric information by the paging terminal 102 and the protocol utilized for the transmission of the messages is described below.
• FIG. 1 Processing of the numeric and alphanumeric information by the paging terminal 102 and the protocol utilized for the transmission of the messages is described below.
• FIG. 2 is an electrical block diagram of the paging terminal 102 utilized for processing and controlling the transmission of the message information in accordance with the preferred embodiment of the present invention.
• Short messages such as tone-only and numeric messages which can be readily entered using a Touch-Tone telephone, are coupled to the paging terminal 102 through a telephone interface 202 in a manner well known in the art.
• Longer messages such as alphanumeric messages which require the use of a data entry device, are coupled to the paging terminal 102 through a modem 206 using any of a number of well known modem transmission protocols.
• a controller 204 handles the processing of the message.
• the controller 204 is preferably a microcomputer, such as an MC68000 or equivalent, which is manufactured by Motorola Inc., and which runs various pre-programmed routines for controlling such terminal operations as voice prompts to direct the caller to enter the message, or the handshaking protocol to enable reception of messages from a data entry device.
• the controller 204 references information stored in the subscriber database 208 to determine how the message being received is to be processed.
• the subscriber database 208 includes, but is not limited to, such information as addresses assigned to the data communication receiver, message type associated with the address, and information related to the status of the data communication receiver, such as active or inactive for failure to pay the service charges.
• a data entry terminal 240 is provided which couples to the controller 204, and which is used for such purposes as entry, updating and deleting of information stored in the subscriber data base 208, for monitoring system performance, and for obtaining such information as service charge information.
• the subscriber database 208 also includes such information as to what transmission frame and to what transmission phase the data communication receiver is assigned, as will be described in further detail below.
• the received message is stored in an active page file 210 which stores the messages in queues according to the transmission phase assigned to the data communication receiver. In the preferred embodiment of the present invention, four phase queues are provided in the active page file 210.
• the active page file 210 is preferably a dual port, first in first out random access memory, although it will be appreciated that other random access memory devices, such as hard disk drives, can be utilized as well.
• the message information stored in each of the phase queues is recovered from the active page file 210 under control of controller 204 using timing information such as provided by a real time clock 214, or other suitable timing source.
• the recovered message information from each phase queue is sorted by frame number and is then organized by address, message information, and any other information required for transmission, and then batched into frames based upon message size by frame batching controller 212.
• the batched frame information for each phase queue is coupled to frame message buffers 216 which temporarily store the batched frame information until a time for further processing and transmission.
• Frames are batched in numeric sequence, so that while a current frame is being transmitted, the next frame to be transmitted is in the frame message buffer 216, and the next frame thereafter is being retrieved and batched.
• the batched frame information stored in the frame message buffer 216 is transferred to the frame encoder 218, again maintaining the phase queue relationship.
• the frame encoder 218 encodes the address and message information into address and message code words required for transmission, as will be described below.
• the encoded address and message code words are ordered into blocks and then coupled to a block interleaver 220 which interleaves preferably eight code words at a time for transmission in a manner well known in the art.
• the interleaved code words from each block interleaver 220 are then serially transferred to a phase multiplexer 221, which multiplexes the message information on a bit by bit basis into a serial data stream by transmission phase.
• the controller 204 next enables a frame sync generator 222 which generates the synchronization code which is transmitted at the start of each frame transmission.
• the synchronization code is multiplexed with address and message information under the control of controller 204 by serial data splicer 224, and generates therefrom a message stream which is properly formatted for transmission.
• the message stream is next coupled to a transmitter controller 226, which under the control of controller 204 transmits the message stream over a distribution channel 228.
• the distribution channel 228 may be any of a number of well known distribution channel types, such as wire line, an RF or microwave distribution channel, or a satellite distribution link.
• the distributed message stream is transferred to one or more transmitter stations 104, depending upon the size of the communication system.
• the message stream is first transferred into a dual port buffer 230 which temporarily stores the message stream prior to transmission.
• the message stream is recovered from the dual port buffer 230 and coupled to the input of preferably a 4-level FSK modulator 234.
• the modulated message stream is then coupled to the transmitter 236 for transmission via antenna 238.
• FIGS. 3, 4 and 5 are timing diagrams illustrating the transmission format of the signaling protocol utilized in accordance with the preferred embodiment of the present invention. As shown in FIG.
• the signaling protocol enables message transmission to data communication receivers, such as pagers, assigned to one or more of 128 frames which are labeled frame 0 through frame 127. It then will be appreciated that the actual number of frames provided within the signaling protocol can be greater or less than described above. The greater the number of frames utilized, the greater the battery life that may be provided to the data communication receivers operating within the system. The fewer the number of frames utilized, the more often messages can be queued and delivered to the data communication receivers assigned to any particular frame, thereby reducing the latency, or time required to deliver messages. As shown in FIG. 4, the frames comprise a synchronization code (sync) followed preferably by eleven blocks of message information which are labeled block 0 through block 10. As shown in FIG.
• sync synchronization code
• each block of message information comprises preferably eight address, control or data code words which are labeled word 0 through word 7 for each phase. Consequently, each phase in a frame allows the transmission of up to eighty-eight address, control and data code words.
• the address, control and data code words are preferably 31,21 BCH code words with an added thirty-second even parity bit which provides an extra bit of distance to the code word set. It will be appreciated that other code words, such as a 23,12 Golay code word, could be utilized as well.
• Unlike the well known POCSAG signaling protocol which provides address and data code words that utilize the first code word bit to define the code word type as either address or data, no such distinction is provided for the address and data code words in the signaling protocol utilized with the preferred embodiment of the present invention. Rather, address and data code words are defined by their position within the individual frames.
• FIGS. 6 and 7 are timing diagrams illustrating the synchronization code utilized in accordance with the preferred embodiment of the present invention.
• the synchronization code comprises preferably three parts, a first synchronization code (sync 1), a frame information code word (frame info) and a second synchronization code (sync 2).
• the first synchronization code comprises first and third portions, labeled bit sync 1 and BS1, which are alternating 1,0 bit patterns which provides bit synchronization, and second and fourth portions, labeled "A" and its complement “A bar", which provide frame synchronization.
• the second and fourth portions are preferably single 32,21 BCH code words which are predefined to provide high code word correlation reliability and which are also used to indicate the data bit rate at which addresses and messages are transmitted.
• the table below defines the data bit rates which are used in conjunction with the signaling protocol.
• a fourth "A" value is also predefined for future use.
• the frame information code word is preferably a single 32,21 BCH code word which includes within the data portion a predetermined number of bits reserved to identify the frame number, such as 7 bits encoded to define frame number 0 to frame number 127.
• the structure of the second synchronization code is preferably similar to that of the first synchronization code described above.
• the second synchronization code is transmitted at the data symbol rate at which the address and messages are to be transmitted in any given frame. Consequently, the second synchronization code allows the data communication receiver to obtain "fine" bit and frame synchronization at the frame transmission data bit rate.
• the signaling protocol utilized with the preferred embodiment of the present invention comprises 128 frames which include a predetermined synchronization code followed by eleven data blocks which comprise eight address, control or message code words per phase.
• the synchronization code enables identification of the data transmission rate, and insures synchronization by the data communication receiver with the data code words transmitted at the various transmission rates.
• FIG. 8 is an electrical block diagram of the data communication receiver 106 in accordance with the preferred embodiment of the present invention.
• the heart of the data communication receiver 106 is a controller 816, which is preferably implemented using an MC68HC05HC11 microcomputer, such as manufactured by Motorola, Inc.
• the microcomputer controller hereinafter call the controller 816, receives and processes inputs from a number of peripheral circuits, as shown in FIG. 8, and controls the operation and interaction of the peripheral circuits are achieved by using software subroutines.
• the use of a microcomputer controller for processing and control functions is well known to one of ordinary skill in the art.
• the data communication receiver 106 is capable of receiving address, control and message information, hereafter called "data" which is modulated using preferably 2-level and 4-level frequency modulation techniques.
• the transmitted data is intercepted by an antenna 802 which couples to the input of a receiver section 804.
• Receiver section 804 processes the received data in a manner well known in the art, providing at the output an analog 4-level recovered data signal, hereafter called a recovered data signal.
• the recovered data signal is coupled to one input of a threshold level extraction circuit 808, and to an input of a 4-level decoder 810.
• the threshold level extraction circuit 808 is best understood by referring to FIG. 9, and as shown, comprises two clocked level detector circuits 902, 904 which have as inputs the recovered data signal.
• Level detector 902 detects the peak signal amplitude value and provides a high peak threshold signal which is proportional to the detected peak signal amplitude value, while level detector 904 detects the valley signal amplitude value and provides a valley threshold signal which is proportional to the detected valley signal amplitude value of the recovered data signal.
• the level detector 902, 904 signal outputs are coupled to terminals of resistors 906, 912, respectively.
• the opposite resistor terminals 906, 912 provide the high threshold output signal (Hi), and the low threshold output signal (Lo), respectively.
• the opposite resistor terminals 906, 912 are also coupled to terminals of resistors 908, 910, respectively.
• resistor 908, 910 terminals are coupled together to form a resistive divider which provides an average threshold output signal (Avg) which is proportional to the average value of the recovered data signal.
• Resistors 906, 912 have resistor values preferably of 1R
• resistors 908, 910 have resistor values preferably of 2R, realizing threshold output signal values of 17%, 50% and 83%, and which are utilized to enable decoding the 4-level data signals as will be described below.
• a clock rate selector 914 is preset through a control input (center sample) to select a 128X clock, i.e.
• the 128X clock is generated by 128X clock generator 844, as shown in FIG. 8, which is preferably a crystal controlled oscillator operating at 204.8 KHz (kilohertz).
• the output of the 128X clock generator 844 couples to an input of frequency divider 846 which divides the output frequency by two to generate a 64X clock at 102.4 KHz.
• the 128X clock allows the level detectors 902, 904 to asynchronously detect in a very short period of time the peak and valley signal amplitude values, and to therefore generate the low (Lo), average (Avg) and high (Hi) threshold output signal values required for modulation decoding.
• the controller 816 After symbol synchronization is achieved with the synchronization signal, as will be described below, the controller 816 generates a second control signal (Center Sample) to enable selection of a IX symbol clock which is generated by symbol synchronizer 812 as shown in FIG. 8.
• the 4-level decoder 810 operation is best understood by referring to FIG. 10.
• the 4-level decoder 810 comprises three voltage comparators 1010, 1020, 1030 and a symbol decoder 1040.
• the recovered data signal couples to an input of the three comparators 1010, 1020, 1030.
• the high threshold output signal (Hi) couples to the second input of comparator 1010
• the average threshold output signal (Avg) couples to the second input of comparator 1020
• the low threshold output signal (Lo) couples to the second input of comparator 1030.
• the outputs of the three comparators 1010, 1020, 1030 couple to inputs of symbol decoder 1040.
• the symbol decoder 1040 decodes the inputs according to the table provided below.
• the MSB output from the 4-level decoder 810 is coupled to an input of the symbol synchronizer 812 and provides a recovered data input generated by detecting the zero crossings in the 4-level recovered data signal.
• the positive level of the recovered data input represents the two positive deviation excursions of the analog 4-level recovered data signal above the average threshold output signal, and the negative level represents the two negative deviation excursions of the analog 4-level recovered data signal below the average threshold output signal.
• the operation of the symbol synchronizer 812 is best understood by referring to FIG. 11.
• the 64X clock at 102.4 KHz which is generated by frequency divider 846, is coupled to an input of a 32X rate selector 1120.
• the 32X rate selector 1120 is preferably a divider which provides selective division by 1 or 2 to generate a sample clock which is thirty-two times the symbol transmission rate.
• a control signal (1600/3200) is coupled to a second input of the 32X rate selector 1120, and is used to select the sample clock rate for symbol transmission rates of 1600 and 3200 symbols per second.
• the selected sample clock is coupled to an input of 32X data oversampler 1110 which samples the recovered data signal (MSB) at thirty-two samples per symbol.
• the symbol samples are coupled to an input of a data edge detector 1130 which generates an output pulse when a symbol edge is detected.
• the sample clock is also coupled to an input of a divide-by-16/32 circuit 1140 which is utilized to generate IX and 2X symbol clocks synchronized to the recovered data signal.
• the divide-by- 16/32 circuit 1140 is preferably an up/down counter.
• the output generated by AND gate 1150 causes the count of divide-by-16/32 circuit 1140 to be advanced by one count in response to the pulse which is coupled to the input of divide-by-16/32 circuit 1140 from the data edge detector 1130, and when the pulse coupled to the input of AND gate 1150 arrives after the generation of a count of thirty-two by the divide-by- 16/32 circuit 1140, the output generated by AND gate 1150 causes the count of divide-by-16/32 circuit 1140 to be retarded by one count in response to the pulse which is coupled to the input of divide-by-16/32 circuit 1140 from the data edge detector 1130, thereby enabling the synchronization of the IX and 2X symbol clocks with the recovered data signal.
• the symbol clock rates generated are best understood from the table below.
• the IX and 2X symbol clocks are generated at 1600, 3200 and 6400 bits per second and are synchronized with the recovered data signal.
• the 4-level binary converter 814 is best understood by referring to FIG. 12.
• the IX symbol clock is coupled to a first clock input of a clock rate selector 1210.
• a 2X symbol clock also couples to a second clock input of the clock rate selector 1210.
• the symbol output signals (MSB, LSB) are coupled to inputs of an input data selector 1230.
• a selector signal (2L/4L) is coupled to a selector input of the clock rate selector 1210 and the selector input of the input data selector 1230, and provides control of the conversion of the symbol output signals as either 2-level FSK data, or 4- level FSK data.
• 2-level FSK data conversion (2L) is selected, only the MSB output is selected which is coupled to the input of a parallel to serial converter 1220.
• the IX clock input is selected by clock rate selector 1210 which results in a single bit binary data stream to be generated at the output of the parallel to serial converter 1220.
• clock rate selector 1210 When the 4-level FSK data conversion (4L) is selected, both the LSB and MSB outputs are selected which are coupled to the inputs of the parallel to serial converter 1220.
• the 2X clock input is selected by clock rate selector 1210 which results in a serial two bit binary data stream to be generated at 2X the symbol rate, which is provided at the output of the parallel to serial converter 1220.
• the serial binary data stream generated by the 4- level to binary converter 814 is coupled to inputs of a synchronization word correlator 818 and a demultiplexer 820.
• the synchronization word correlator is best understood with reference to FIG. 13.
• Predetermined "A” word synchronization patterns are recovered by the controller 816 from a code memory 822 and are coupled to an "A" word correlator 1310.
• an "A" or "A-bar” output is generated and is coupled to controller 816.
• the particular "A" or "A-bar” word synchronization pattern correlated provides frame synchronization to the start of the frame ID word, and also defines the data bit rate of the message to follow, as was previously described.
• the serial binary data stream is also coupled to an input of the frame word decoder 1320 which decodes the frame word and provides an indication of the frame number currently being received by the controller 816.
• power is supplied to the receiver portion by battery saver circuit 848, shown in FIG. 8, which enabled the reception of the "A" synchronization word, as described above, and which continues to be supplied to enable processing of the remainder of the synchronization code.
• the controller 816 compares the frame number currently being received with a list of assigned frame numbers stored in code memory 822. Should the currently received frame number differ from an assigned frame number, the controller 816 generates a battery saving signal which is coupled to an input of battery saver circuit 848, suspending the supply of power to the receiver portion. The supply of power will be suspended until the next frame assigned to the receiver, at which time a battery saver signal is generated by the controller 816 which is coupled to the battery saving circuit 848 to enable the supply of power to the receiver portion to enable reception of the assigned frame.
• a predetermined "C” word synchronization pattern is recovered by the controller 816 from a code memory 822 and is coupled to a "C” word correlator 1330.
• a "C” or “C-bar” output is generated which is coupled to controller 816.
• the particular "C” or “C-bar” synchronization word correlated provides "fine" frame synchronization to the start of the data portion of the frame.
• the start of the actual data portion is established by the controller 816 generating a block start signal (Blk Start) which is coupled to inputs of a word de-interleaver 824 and a data recovery timing circuit 826.
• the data recovery timing circuit 826 is best understood by referring to FIG. 14.
• a control signal (2L / 4L) is coupled to an input of clock rate selector 1410 which selects either IX or 2X symbol clock inputs.
• the selected symbol clock is coupled to the input of a phase generator 1430 which is preferably a clocked ring counter which is clocked to generate four phase output signals (01-04).
• a block start signal (BLK START) is also coupled to an input of the phase generator 1430, and is used to hold the ring counter in a predetermined phase until the actual decoding of the message information is to begin.
• the phase generator 1430 begins generating clocked phase signals which are synchronized with the incoming message symbols.
• the clocked phase signal outputs are coupled to inputs of a phase selector 828.
• the controller 816 recovers from the code memory 822, the transmission phase number to which the data communication receiver is assigned. The phase number is transferred to the phase select output (0 Select) of the controller 816 and is coupled to an input of phase selector 828.
• a phase clock, corresponding to the transmission phase assigned, is provided at the output of the phase selector 828 and is coupled to clock inputs of the demultiplexer 820, block de-interleaver 824, and address and data decoders 830 and 832, respectively.
• the demultiplexer 820 is used to select the binary bits associated with the assigned transmission phase which are then coupled to the input of block de-interleaver 824, and clocked into the de-interleaver array on each corresponding phase clock.
• the de-interleaver array is an 8x32 bit array which de-interleaves eight interleaved address, control or message code words, corresponding to one transmission block.
• the de-interleaved address code words are coupled to the input of address correlator 830.
• the controller 816 recovers the address patterns assigned to the data communication receiver, and couples the patterns to a second input of the address correlator.
• the message information associated with the address is then decoded by the data decoder 832 and stored in a message memory 850 in a manner well known to one of ordinary skill in the art.
• a sensible alert signal is generated by the controller 816.
• the sensible alert signal is preferably an audible alert signal, although it will be appreciated that other sensible alert signals, such as tactile alert signals, and visual alert signals can be generated as well.
• the audible alert signal is coupled by the controller 816 to an alert driver 834 which is used to drive an audible alerting device, such as a speaker or a transducer 836. The user can override the alert signal generation through the use of user input controls 838 in a manner well known in the art.
• the message information is coupled to the input of data decoder 832 which decodes the encoded message information into preferably a BCD or ASCII format suitable for storage and subsequent display.
• the stored message information can be recalled by the user using the user input controls 838 whereupon the controller 816 recovers the message information from memory, and provides the message information to a display driver 840 for presentation on a display 842, such as an LCD display.
• FIG. 15 is a flow chart describing the operation of the data communication receiver in accordance with the preferred embodiment of the present invention.
• step 1502 when the data communication receiver is turned on, the controller operation is initialized, at step 1504. Power is periodically applied to the receiver portion to enable receiving information present on the assigned RF channel.
• step 1508 When data is not detected on the channel in a predetermined time period, battery saver operation is resumed, at step 1508.
• the synchronization word correlator begins searching for bit synchronization at step 1510.
• bit synchronization is obtained, at step 1510, the "A" word correlation begins at step 1512.
• the message transmission rate is identified as described above, at step 1516, and because frame synchronization is obtained, the time (Tl) to the start of the frame identification code word is identified, at step 1518.
• step 1514 When the non-complemented "A” word is not detected, at step 1514, indicating the non-complemented “A” word may have been corrupted by a burst error during transmission, a determination is made whether the complemented "A" bar” is detected, at step 1520. When the "A bar” word is not detected at step 1512, indicating that the "A-bar” word may also have been corrupted by a burst error during transmission, battery saver operation is again resumed, at step 1508. When the "A-bar" word is detected, at step 1520, the message transmission rate is identified as described above, at step 1522, and because frame synchronization is obtained, the time (T2) to the start of the frame identification code word is identified, at step 1524.
• decoding of the frame identification word occurs, at step 1526.
• the frame ID detected is not one assigned to the data communication receiver, at step 1528, battery saving is resumed, at step 1508, and remains so until the next assigned frame is to be received.
• the message reception rate is set, at step 1530.
• An attempt to bit synchronize at the message transmission rate is next made at step 1532.
• bit synchronization is obtained, at step 1533, the "C" word correlation begins at step 1534.
• frame synchronization is obtained, and the time (T3) to the start of the message information is identified, at step 1538.
• step 1536 When the non-complemented "C” word is not detected, at step 1536, indicating the non-complemented “C” word may have been corrupted by a burst error during transmission, a determination is made whether the complement "C bar" is detected, at step 1540. When the "C bar” word is not detected at step 1540, indicating that the "C-bar” word may also have been corrupted by a burst error during transmission, battery saver operation is again resumed, at step 1508. When the "C-bar" word is detected, at step 1540, frame synchronization is obtained, and the time (T4) to the start of the message information is identified, at step 1542. At the appropriate time, message decoding can begin at step 1544.
• the reliability of synchronizing with synchronization information that is subject to burst error corruption is greatly enhanced.
• the use of a predetermined synchronization code word as the first synchronization code word, and a second predetermined synchronization code word which is the complement of the first predetermined synchronization code word allow accurate frame synchronization on either the first or the second predetermined synchronization code word.
• additional information such as the transmission data rate, can be provided, thereby enabling the transmission of message information at several data bit rates.
• FIG. 16 is an electrical block diagram of a simulcast system for processing and transmitting information in accordance with the preferred embodiment of the present invention.
• the transmitter stations 104 shown in FIG. 2, are coupled to a transmitter controller 226.
• the transmitter controller 226 preferably comprises a high speed modem 227 for transmitting data at a speed faster than the speed of real-time transmission on a narrow band RF channel. It will be appreciated by one of ordinary skill in the art that the high speed modem 227 time compresses the data before transmission to the plurality of base sites 1602, 1604, 1606, 1608 to achieve this high speed transmission.
• the transmitter controller 226 also includes an oscillator 225 for establishing a time stability or time reference of the transmitter controller 226.
• a stability factor usually referred to as N parts-per- million (PPM) or N parts-per-billion (PPB), where N refers to the accuracy of the oscillator as the number of clock cycles.
• the transmitter controller 226 is coupled by the distribution channel 228 to the plurality of base sites 1602, " 4, 1606, 1608 which are shown only as example.
• the distribution channel 228 is shown divided into four distributor channels 1642-8 coupled to each of the base sites 1602, 1604, 1606, 1608, respectively.
• the plurality of base sites 1602, 1604, 1606, 1608 comprise base site controllers 1612, 1614, 1616, 1618 coupled to transmitters 1622-28 which have predefined coverage areas, for example, coverage areas 1632, 1634.
• the base site controllers 1612, 1614, 1616, 1618 also comprise modems 1603, 1605, 1607, 1609 for receiving the high speed data, and oscillators 1611, 1613, 1615, 1617 for establishing a time stability in the plurality of base sites 1602, 1604, 1606, 1608.
• the base site controllers 1612, 1614, 1616, 1618 are preferably digital signal processors or microcomputers, such as an MC68000 or equivalent, which are manufactured by Motorola Inc., and which run various pre-programmed routines for controlling such base station operations for transmitting and receiving data, or the handshaking protocol to enable the retransmission of the data at a predetermined time as will be discussed below.
• the transmitter controller measures each of the propagation delays for transmitting data to each of the plurality of base sites, step 1702. Subsequent to measuring the propagation delays for transmitting data to each of the plurality of base sites, the transmitter controller calculates (computes) any propagation delay differences for each of the plurality of base sites, step 1704. For example, the transmitter controller determines the maximum measured propagation delay and subtracts all other measured propagation delays to established the propagation delay differences of each base site. This simple method would then include a propagation delay difference of zero for the base site having the maximum measured propagation delay.
• the transmitter controller is capable of sorting the plurality of propagation delay differences to ensure that each base site receives the propagation delay difference calculated between the transmitter controller and that base site.
• the base sites receive and store the propagation delay differences at each of the respective base sites, step 1708.
• the transmitter controller receives data to be transmitted to the plurality of base sites and transmits the received data to the plurality of base sites, step 1712.
• the data is preferably transmitted by high speed modems at speeds faster than the speed of RF transmission on a narrow band RF channel, a technique well known to one of ordinary skill in the art.
• the data is time-compressed by well known techniques before it is transmitted to the plurality of base sites.
• the plurality of base sites receive the data, step 1714, and store the received data in memory at each of the plurality of base sites, step 1716.
• Each of the plurality of base sites has the capability of decompressing the time compressed data received from the transmitter controller.
• the transmitter controller generates a start command which is transmitted in simulcast to the plurality of base sites, step 1718.
• the transmitter controller before transmitting the start command, delays or waits a period of time to ensure that the plurality of base sites receive, decompress and store the data.
• each of the plurality of base sites delays retransmission of the stored data by the propagation delay difference calculated and stored in each base site, step 1722.
• the propagation delay differences are calculated such that when all the base sites receive the start command, all of the propagation delay differences will expire simultaneously to enable simulcast retransmission of the stored data from the plurality of base sites.
• each base site retransmits the data stored in memory, step 1724. The data is retransmitted via RF transmission by the plurality of base sites.
• the simulcast system calculates propagation delay differences from measured propagation delays for each of a plurality of base sites.
• a terminal controller receives and transmits data to each of the plurality of base sites.
• the terminal controller transmits the propagation delay differences and a start command to the plurality of base sites for initiating simulcast retransmission of the data.
• the plurality of base sites receive the propagation delay differences, the propagation delay differences being determined for delaying the retransmission of data in each of the plurality of base sites.
• the base site stores the received data and delays retransmission of the stored data from the receipt of the start command by the propagation delay difference calculated for each base site to enable the retransmission of the data at substantially the same time by the plurality of base sites.
• the data is received and stored at the plurality of base sites, jitters (i.e., bit edge uncertainty) is eliminated.
• This method avoids resolving the difference in time the data is received at the plurality of base sites by storing the received data and waiting a sufficient length of time to ensure that all base sites have received the data to be retransmitted.
• the data is also transmitted to the plurality of base sites without regard to simulcast reception or transmission of data. Also, because the data is transmitted faster than the speed capable using an RF transmission on a narrow band RF channel, by the time the data is simulcast, the base site can start receiving additional data to be retransmitted. In this way, the simulcast transmission system spends far less time to synchronize the plurality of base sites, thus saving valuable air-time for transmitting and retransmitting the data instead of synchronizing the system. What is claimed is:

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• 1993
  • 1993-05-07 CA CA002135795A patent/CA2135795A1/en not_active Abandoned
  • 1993-05-07 KR KR1019940704297A patent/KR950701783A/ko not_active Application Discontinuation
  • 1993-05-07 WO PCT/US1993/004346 patent/WO1993025012A1/en not_active Application Discontinuation
  • 1993-05-07 EP EP93911153A patent/EP0642717A4/de not_active Withdrawn

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