EP0641475A1

EP0641475A1 - Method for displaying different levels of gray and system for implementing such method.

Info

Publication number: EP0641475A1
Application number: EP93910133A
Authority: EP
Inventors: Denis Sarrasin
Original assignee: Commissariat a lEnergie Atomique CEA
Current assignee: Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date: 1992-05-21
Filing date: 1993-05-18
Publication date: 1995-03-08
Anticipated expiration: 2013-05-18
Also published as: DE69304199D1; JP3453141B2; US5638091A; EP0641475B1; FR2691568B1; JPH07507158A; FR2691568A1; DE69304199T2; WO1993023841A1

Abstract

The invention relates to a method for displaying different levels of gray on a matrix screen comprised of pixels arranged along R rows and M columns of images having QS levels of gray and obtained by addition to each pixel during the inscription of image data line by line, during S sub-times (lines or frames, S being at least 2), of a succession of discrete luminance levels selected amongst N such that any gray hue comprised between 0 and (QS-1) may be defined by the addition of S said luminance levels. The invention also relates to a system for implementing such method. Application particularly to the display on micropoint screens.

Description

METHOD FOR DISPLAYING DIFFERENT GRAY LEVELS AND SYSTEM FOR CARRYING OUT SAID METHOD

DESCRIPTION

Technical area

The invention relates to a method for displaying different levels of gray and a system for implementing this method.

The display system of the invention applies, in particular, to microtip screens.

In the present description, the term "shade of gray" covers that of "shades of color".

State of the art

In the display field, the standard addressing methods have been described by T. Leroux, A. Ghis, R. Meyer and D. Sarrasin in an article entitled "Microtips Display Adressing" (SID 91 Digest pages 437 to 439 ). We distinguish in this article two types of addressing:

an analog addressing which consists in sampling an analog source signal (of the video type for example);

- addressing in PWM time modulation (Puise Width Modulation) based on the time switching of the column voltage.

The analog solution can give satisfaction for television applications. However, the current technology for matrix screen control circuits only allows sampling rates of around 5 MHz, which is insufficient for computer applications. Through for example, the "data" clock for a VGA screen (current screen size standard) is around 25 MHz. On the other hand, for IT we have a digital data source. An analog control mode therefore requires an additional step of transformation of the source signal by means of a digital-analog converter.

The digital solution can be obtained using several well-known methods:

PWM type pulse width modulation (Pulse Width Modulation) consists of modulating the duration of the "ON" state with an output circuit that can switch two voltage levels (allowing you to select the "ON" and "OFF" states). of the column considered during the row selection. This type of addressing works well for displaying a small number of shades of gray, for example sixteen. But to correctly transmit a shade of gray. the selection times must remain large in front of the signal rise times. However, for a VGA screen (640 columns, 480 lines) scanned at the frame frequency of 70 Hz, the line selection time is at most 1/70 × 480 # 30 μ s. For sixteen shades of gray, the smallest selection period is therefore 30 μs / 16 # 2 us and for two hundred and fifty six shades: 30 μs / 256 # 120ns. The order of magnitude of the rise times, linked to the output impedance of the column circuits and to the capacity presented by the screen column, is from a hundred to a few hundred nanoseconds. We therefore see that this method can be satisfactory for sixteen shades of gray but certainly not for two hundred and fifty six.

FRC (Frame Rate Control) time modulation consists of performing several scans of the image by successively assigning "ON" or "OFF" states to the same image elements, the eye acting as an integrator. This modulation is also limited in number of shades of gray, because the multiple addressing of the same picture element leads, on the one hand, to high frequencies at the level of the data flow at the input of the circuits and, on the other hand, at too short selection periods on the outputs. In practice, there are screens displaying thirty two shades of gray with this method. However, these are STN (Super Twisted Nematic or Multiplex LCD) type liquid crystal screens whose response times of around 200 to 300 ms allow the total renewal of information from one picture element with durations greater than that of retinal persistence. Such a method is illustrated in European patent applications EP-0-384 403 A2 -SEIKO and EP-0-364 307 A2 -COMPAQ.

One method using multi-level circuits consists in using circuits which can switch N different voltage levels (in practice, N = 8 or N = 16). The analog output multiplexer ensuring the switching of fairly high voltages, its size "silicon" is relatively large. In addition there is one multiplexer per output. It is therefore hardly possible to envisage more than sixteen switchable channels.

Such multi-level circuits can be associated with the FRC method, as described in the article by H. Mano, T. Furukashi and T. Tanaka, entitled "Multicolor Display Control Method for TFT-LCD" (SID 91 Digest pages 547 at 550). This involves using multi-level circuits (analog multiplexers), for example eight, and performing two scans of the screen (frame 1 and frame 2). Frame 1 is representative of the least significant and is obtained by using a first set of eight voltages applied to the multiplexers, the second, representative of the most significant, being done by means of a second set of eight voltages distinct from the first.

Figure 1 illustrates this method by giving an example of a block diagram for sixty four gray levels with two sets of eight different voltage levels.

In this FIG. 1, a source 10 of digital data to be displayed delivers these digital data to three logical multiplexers 11 with two inputs and one output, the bits of weight 1, 2 and 4 being respectively connected to a first input of these multiplexers 11, the weight bits 8, 16 and 32 being respectively connected to the second input of these multiplexers 11.

The three outputs of these multiplexers are respectively connected to three data storage circuits 12 comprising shift registers associated with storage registers.

A generator 15 supplies a first set of eight voltages V _0a to V _{7 a} and a second set of eight voltages V _0b to V _7b which are two by two connected to the inputs of seven "high" multiplexer 14 with two inputs and one output .

A controller 16 connected to the data source 10 delivers a control signal ST which is sent to each of the logic multiplexers 11 and to each of the "high" voltage multiplexers 14.

A circuit 13 for column control of the screen 17 receives on the one hand the outputs of the circuits 12 and, on the other hand, those of the "high" voltage multiplexers 14. This control circuit 13 is formed of eight analog multiplexers with eight inputs and an output. In this figure 1 the line control circuit has not been shown. It can be a conventional circuit, using for example shift registers, making it possible to successively select the lines of the screen one by one.

The data source includes a memory for storing data corresponding to a screen page.

The signal ST, connected to all the multiplexers 11 and 14, with two inputs and one output, is a selection signal multiplexer by frame parity.

Such a method requires sixteen voltage values for sixty four gray levels (and twenty four if it is to be applied to two hundred fifty six levels over three fields) with fairly important details.

For example, for sixty four levels (with data on six bits), we have the weights:

2 ⁰ = 1 2 ¹ = 2 2 ² = 4 2 ³ = 8 2 ⁴ = 16 2 ⁵ = 32 the first frame to translate the weights 1, 2, 4 of this data and the second the weights 8, 16, 32, we have the following luminance levels on screen 17:

L (V _0a ) = 0 L (V _0b ) = 0

L (V _1a ) = 1 × L (V _{1 a} ) L (V _1b) = 8 × L (V _1a )

L (V _2a ) = 2 × L (V _{1 a} ) L (V _1b ) = 16 × L (V _1a ) L (V _3a ) = 3 × L (V _{1 a} ) L (V _1b ) = 24 × L (V _1a )

L (V _4a ) = 4 × L (V _{1 a} ) L (V _1b ) = 32 × L (V _1a ) L (V _5a ) = 5 × L (V _{1 a} ) L (V _1b ) = 40 × L (V _1a ) L (V _6a ) = 6 × L (V _{1 a} ) L (V _1b ) = 48 × L (V _1a ) L (V _7a ) = 7 × L (V _{1 a} ) L (V _1b ) = 56 × L (V _1a ) Such a method leads to a decrease in the contrast of the screen, since half the effective time addressing is devoted to displaying a low weight level. For example for a display of white with two screens for sixty four gray levels, we have:

for frame 1: L (V _a ) = 7 × L (V ₁ )

for frame 2: L (V _b ) = 56 × L (V ₁ ).

The overall yield is therefore only 9/16, which, with two subframes, gives a loss of luminance for the white of approximately 40%.

Presentation of the invention

The subject of the invention is a method of displaying on a matrix screen composed of pixels arranged in R lines and M columns of images capable of comprising a discrete number of Q _s shades of gray, obtained by addition on each pixel, during of a process of recording image data line by line during S sub-time of identical duration (lines or frames; S ≥ 2) of a succession of discrete luminances L (Vi) chosen from N (N≥ 4) with 0≤i≤N-1, each luminance L (Vi) being associated with a voltage Vi applied to the corresponding column, these luminances are such that any gray tint value between 0 and Q _s -1 can be defined by the addition of S of these luminances and more particularly a method such as:

Whatever the addressing phase, therefore of the current sub-time, any luminance among the N possible is selectable:

These luminances are such that if the two extreme luminances L (V ₀ ) corresponding to the minimum luminance and L (V _{N- 1} ) corresponding to the maximum luminance are defined by the following equalities: L (V ₀ ) = αε and L (V _N-1 ) = αK _a + L (V ₀ ) ε being a low value and α a proportionality coefficient equal to (L (V _N-1 ) -L (V ₀ )) / K _a where K _a is a coefficient indexed by a = (N / 4) -1, the N-2 other luminances are then expressed by the following relationships:

L (V _N-2 ) = α (K _a -1) + L (V _o )

L (V _N-3 ) = α (K _a - (S + 1)) + L (V ₀ )

L (V _N-4 ) = α (K _a -2S) + L (V ₀ )

L (V _N-5 ) = αKa _-1 + L (V ₀ )

L (V _N-6 ) = α (K _a-1 -1) + L (V ₀ )

L (V _N-7 ) = α (K _a-1 - (S + 1)) + L (V ₀ )

L (V _N-8 ) = α (K _a-1 -2S) + L (V ₀ )

L (V _N-9 ) = αK _a-2 + L (V ₀ )

.

L (V ₇ ) = αK ₁ + L (V ₀ )

L (V ₆ ) = α (K ₁ -1) + L (V ₀ )

L (V ₅ ) = α (K ₁ - (S + 1)) + L (V ₀ )

^{L (V} 4 = α (K ₁ -2S) + L (V ₀ )

L (V ₃ ) = α · 2S + L (V ₀ )

L (V ₂ ) = α (S + 1) + L (V ₀ )

L (V ₁ ) = α + L (V ₀ ) where K _x , with x ranging from a to 1, are coefficients of (N / 4) -1 respectively assigned to a group of four luminances. K _x being such that: for x = 1, if S is odd K ₁ ≤S ² + 4s

if S is even K1≤S ² + 5s-1 for x ranging from (a-1) to 2

if S is odd K _X ≤K _X-1 + S ² + 2S

if S is even K _X ≤K _X-1 + S ² + 3S -1 and for x = a, whatever S, (Q-1) / S≥K _a ≥ (Q _s -1) / S.

These N selectable luminances are obtained by adjusting the N voltages V ₀ , ...., V _N-1 and make it possible to obtain a selectable number Q (Q≥Q _S ) of gray equal to:

if S is odd, Q = S (aS ² + (2a + 2) · S) + 1

if S is even, Q = S (aS ² + (3a + 2) · Sa)) + 1

and for N = 4 Q = (S + 1) ² with L (V ₀ ) = α ε, L (V ₁ ) = α + L (V ₀ ), L (V ₂ ) = α (S + 1) + L (V ₀ ) and

L (V ₃ ) = α (S + 2) + L (V ₀ ).

Advantageously, the method for implementing the system of the invention comprises the following steps;

- sending, from a source of images to be displayed, a data item in the form of a binary, corresponding to the code of the gray level to be displayed, in a transcoding matrix;

- sending, simultaneously, synchronized signals to a screen controller so that it successively supplies the addresses of the S sub-times either to the transcoding matrix, or to a logic multiplexer device disposed upstream of the analog multiplexer device controlling the screen, this analog multiplexer being connected to a generator of at least N voltages;

- for a given sub-time, sending the address of the voltage to be switched from the transcoding to a set of shift registers associated with storage registers; - transfer of the content of the associated registers in the analog control multiplexers of the screen either directly or through a logical multiplexer device;

- switching of the voltage selected on the column of the screen.

Advantageously, the combination of the tension values is done according to an increasing or decreasing arrangement. One can also, in the case of line sub-time, follow an increasing order for a line parity and a decreasing order for the other line parity.

The invention also relates to a system allowing the implementation of this gray level display method digitally on a matrix screen.

More particularly, this system comprises: - a source of digital data to be displayed;

a screen controller receiving synchronization signals from the data source which successively delivers the addresses of the S sub-times to a transcoding circuit;

- a data storage system;

- a circuit for controlling the columns of the screen;

- a generator of at least N voltages;

characterized in that it further comprises:

the transcoding circuit connected to the digital data source receiving from the latter the binary addresses corresponding to the gray level code to be displayed and in particular delivering the address of the voltage to be switched to a control circuit making it possible to validate 1 among N discrete analog voltages. In a first alternative embodiment, the screen controller is linked to the data storage system. The data storage system includes shift registers associated with storage registers. The screen column control circuit comprises several circuits making it possible to select a voltage from among several discrete voltages, this voltage controlling the column considered in the screen.

In a second variant embodiment, the screen controller is linked directly to the screen control means. The transcoding circuit comprises transcoding sub-matrices each corresponding to a sub-time. The data storage system comprises parallel shift registers each associated with a register and each linked to a transcoding sub-matrix. The screen column control circuit includes circuits allowing a voltage to be selected from among several discrete voltages, this voltage controlling the relevant column of the screen and digital multiplexers linked to the controller and disposed between the associated registers and said circuits.

Advantageously, the system of the invention makes it possible to mix the only time mode (PWM method: division of the line time into S line sub-time) and the mode only in voltage (choice between n output voltages for the column circuit), in a mixed time / voltage mode with a distribution grid which, while avoiding both code "holes" and loss of luminance, makes it possible to achieve a large number of gray levels with a minimum of time and voltage inputs. This system meets several criteria:

- voltage multiplexer limited in number of channels;

- minimization of the number of line sub-times required (to be able to access more complex screens);

- the maximum levels of the voltages used remain close to those of a black / white addressing only, which implies that all the voltages can be applied to any sub-time.

Brief Description of the Drawings - Figure 1 illustrates a system of the prior art which has been described previously;

- Figure 2 illustrates a first variant of the system of the invention;

- Figure 3 illustrates a second variant of the system of the invention;

- Figures 4 and 5 show two curves illustrating the operation of the system according to the invention;

- Figures 6 and 7 illustrate a step in the method of the invention.

Detailed description of embodiments

In known manner, the addressing of a matrix screen of R lines and M columns is carried out line by line (line time = T _R ) during a frame of duration T _t greater than or equal to LT _R. When addressing each line, the information to be displayed on the M pixels (picture elements) of this line is applied simultaneously to the M columns of the screen. In what follows, we will also discuss line sub-time. Indeed, during the selection of the same row, it is envisaged to be able to apply to the columns (therefore to the same pixels) S successive information during S row sub-time of duration equal to TR / S. However, if the use of line sub-time is preferable in the case of microtip screens, the method of the invention applies identically in the case of the use of sub-frames (in the case of TFT-LCD or Thin Film Transistor Type Liquid Crystal Displays).

In the system of the invention, the number of voltages used is equal to the number of levels switchable by the analog output multiplexers. We do not operate by breaking down the data into most significant / least significant bits as for the system of the prior art represented in FIG. 1, but we pass the whole word through a transcoding matrix, which can be for example a PROM (Programmable Read Only Memory), which directly supplies the address of the voltage to be validated on the analog multiplexer of the output considered. We use N voltages which are adjusted so that we can describe the Q _s desired shades of gray.

We can distinguish two variants for the implementation of the device.

A first variant of the system of the invention, as shown in FIG. 2, comprises:

a digital data source 20 to be displayed, connected to a memory 19,

a screen controller 21 delivering S addresses of the sub-times corresponding to the gray-level addressing phases, said controller a screen receiving SS synchronization signals from the data source 20;

- a transc od ag e circuit 22 connected to the digital data source 20, receiving from the latter the binary addresses corresponding to the gray level code to be displayed as well as the address of the current sub-time and delivering for each sub -time the address of the voltage to be switched;

- a data storage system 23, which includes shift registers 28 associated with storage registers 29 (Latches), connected to the transcoding circuit 22 and to the screen controller 21;

a circuit for controlling the columns of the screen 24;

- A generator 25 of N discrete voltages, here eight in number.

During each sub-time, determined by the controller 21, the combination of three bits at the output of each associated register 29 corresponds to the address of a voltage V ₀ to V ₇ . The selected voltage is therefore switched directly to the screen column control circuit 24. This circuit 24 is here produced by several analog multiplexers 26 with eight inputs and one output.

As in the prior art system shown in FIG. 1, the line control circuit, well known to those skilled in the art, has not been shown.

Figure 2 gives an example of a block diagram for Q _s = 64 shades of gray with N = 8 voltages and S = 3 sub-times.

The image information is supplied by the data source 20 in the form of words of d bits (for sixty four shades of gray Q _s = 64 = 2 ^d = ²⁶ ). From synchronization signals SS, the controller 21 supplies a given clock CK, a line sequence end signal LE, a line synchronization clock HL and counting signals SC (sequence counter) which give the number of the sub-time in Classes.

In the case of using sub-time frames, it is necessary to use a page 19 memory. S reads of this memory are carried out, the sequence counter successively decoding the S sub-frames necessary for the formation of the image. The luminance of a picture element coded on d bits, and supplied by the data source 20 is stored in the page memory 19. The latter supplies this word of d bits to the transcoding matrix 22 which produces a word function of the sequence counter on p bits (p such that 2P = N number of voltages selectable by analog output multiplexers).

A shift register with p inputs receives this word of p bits. A clock stroke CK passes it into the first register 28, each clock stroke CK coming to advance it by one box in the registers 28. When all the words corresponding to a display line (one word per column of the screen) have thus been placed in the registers 28, the signal LE is validated and the preceding words pass into the associated registers 29. We can then activate the clock HL and restart the process for the next line while the associated registers 29 present to the analog output multiplexers 26 the p-bit word corresponding to the address of the voltage to be switched (Rq in this case HL = LE).

When all the lines of the screen 27 have been thus described, the sequence counter is incremented and the previous cycle is restarted. The image is formed at the end of the S sub-frames. In the case of line sub-times, there is a need for a line memory 19. The data for a line are loaded into a line memory 19 and then read S times during S line sub-times. In this case, the sequence counter is incremented at each sub-line, that is to say at the rate of the validation of the LE signal, while the HL clock is only activated once every S sub- lines. The data is further processed by the transcoding matrix 22, then by the assembly constituted by the shift registers 28 with associated registers 29 and the analog output multiplexers 26.

In a second variant represented in FIG. 3, several modifications have been made to the system represented in FIG. 2:

the screen controller 21 is directly linked to the control circuit 24 of the screen 27;

the transcoding circuit 22 comprises S transcoding sub-matrices 30 each corresponding to a sub-time;

the data storage system comprises S shift registers 31 in parallel each associated with a register 33 and each linked to a transcoding sub-matrix 30;

the screen control circuit 24 includes the analog multiplexers 26 controlling the screen and digital multiplexers 32 linked to the controller 21 and arranged between the flip-flops associated with the shift registers 31 and the analog multiplexers 26.

In the case of line sub-times, we note that a limit of the previous system, represented in FIG. 2, is the sequential replay of the same data, which requires the presence of a memory and above all the recirculation of "data" information, which leads to multiplying the frequencies both at the level of the transcoding matrix and at that of the clock CK of the shift registers of the screen "driver" circuit (23, 24).

Also in this second variant, the transcoding circuit 22 is constituted by the juxtaposition of S sub-matrices 30 which make it possible to process in parallel the data corresponding to the S sub-time lines. The screen driver assembly 23, 24 consists of S shift register subsets 31 + associated registers 33 of p bits. The data corresponding to the S line sub-times are thus stored in the associated registers 33 and presented to the inputs of the p logic multiplexers 32 among S. In this case the signals HL (line synchronization clock) and LE (end of line sequence) are identical. The logic multiplexers 32, controlled by the line sub-time counter, make it possible to switch the word of the sub-time considered to the analog output multiplexer 26 which thus validates the preselected voltage.

The system of the invention requiring a measurement of the screen brightness for a given adjustment, it is advantageously possible to reserve an area outside the pupil addressed in a similar manner to the rest of the screen and coupled to a photodiode. Such a device, coupled to a controller makes it possible to automatically readjust the various output voltages of the circuits.

In Figures 4 and 5 are shown the amplitude as a function of time signals, obtained on a column output, using row sub-times:

- with N = 8; Q _s = 64; S = 3; K = 21 for Figure 4; - and N = 8; Q _s = 256; S = 6; K = 43 for figure 5.

On these two figures are represented the duration TR of a line time and ranges corresponding to white: B, has different shades of gray: G, to black: N, with three line sub-times for the first curve and six sub- line time for the second.

For the implementation of the two variants described above, the gray level display method according to the invention comprises the following steps:

sending, from an image source 20, a data item in the form of a binary address, corresponding to the gray level code to be displayed, in a transcoding matrix 22;

- simultaneously sending synchronized signals to the screen controller 21 so that it successively supplies the addresses of the S sub-times either to the transcoding matrix 22 or to a logic multiplexer device 32 disposed upstream of the analog multiplexer device 26 controlling the screen, this analog multiplexer being connected to a generator of at least N discrete voltages;

- For a given sub-time, sending of the address of the voltage to be switched from the transcoding to a set of shift registers 31 associated with registers 33 for storage;

transfer of the content of the associated registers 33 into the analog column control multiplexers 26 of the screen either directly or through a logic multiplexer device 32;

- switching of the voltage selected on the column of screen 27. We will now study this step of generating N = 2P discrete voltages.

We note S the number of line sub-times used, Q the number of gray levels and N the number of voltages available on the output multiplexers of the circuits used.

Each voltage level Vi is associated with a level L (vi) of luminance (or of transmission for a passive screen). To perform the temporal sum of S luminance levels and thus reach a large number of grays, it is necessary to assign coefficients to these N luminance levels.

The contrast of a screen being defined as the ratio of maximum luminances / minimum luminances, if we assign the value 0 as the gray coefficient number 0, we assume an infinite contrast. In practice, there is always a residual luminance which is noted ε. Therefore, we denote L (V ₀ ) = αε the minimum luminance.

According to the invention, the number of possible gray levels depends on the number of usable voltages (available on the circuit) and on the number of sub-times. If S is odd, Q = S (aS ² + 2S (a + 1)) + 1

if S is even, Q = S (aS ² + S (3a + 2) -a) + 1

with a = (N / 4) -1.

The case N = 4 is a special case corresponding to a sub-case of N = 8. For N = 4 we take a = 1 by default and the luminances are taken such that:

L (V ₀ ) = αε L (V ₁ ) = α + L (V ₀ ) L (V _N -2) = α (K _a -1) + L (V ₀ )

L (V _N -1) = αK _a + L (V ₀ )

with K _a -1 = S + 1, let K _a = S + 2. The number Q (N = 4) of possible gray is then Q _{(N = 4)} = SK _a + 1 = S (S + 2) + 1 = (S + 1) ² .

The table below gives the number Q of gray selectable as a function of N and S.

Let Q _{s be} the number of grays we wish to display. This number Q _s not necessarily meeting the number Q of gray possible, it is necessary to adapt the value of K _a to Q _s , that is:

K _a > (Q _s -1) / S

the optimum being the smallest possible integer meeting this criterion. If for example we treat the case N = 8 and therefore a = 1, Q _s = 256, we must take S = 6 and Q = 391 with:

K _a ≥ (256-1) / 6 = 42.5 we therefore take: K ₁ ≥ 43.

Furthermore, K _{a must} be less than (Q-1) / S, K _a must be less than 65. We can therefore choose for K _a any value between 43 and 65 and advantageously 43.

Determination of the coefficients K _x

The coefficients K _x with x ranging from 1 to a are assigned to groups of four luminances.

The first group (except N = 4) always has the four coefficients 0, 1, S + 1, 2S, with the following luminance values:

L (V ₀ ) = αε.L (V ₁ ) = α + L (V ₀ ) L (V ₂ ) = α (S + 1) + L (V ₀ )

L (V ₃ ) = α.2S + L (V ₀ ).

The following groups of four luminances are such as:

L (V ₄ ) = α (K ₁ -2S)

L (V ₅ ) = α (K ₁ - (S + 1))

L (V ₆ ) = α (K ₁ -1)

L (V ₇ ) = αK ₁ the relation between S and K ₁ being:

for S odd K ₁ ≤ S ² + 4S

and for S even K ₁ ≤ S ² + 5S-1 In the previous example where N = 8, Q _S = 256 with S = 6, we therefore have the relation:

K ₁ ≤ S ² + 5S-1 = 65

or, since here K ₁ = K _a :

K _a ≤ Q-1 / S = 65

We therefore have double inequality for K _a = K ₁ :

K _a ≥ 43

K _a ≤ 65

The optimum, to minimize the differences between coefficients being to take K _a = 43 which gives in this example:

L (V ₀ ) = 0 = 0

L (V ₁ ) = α = α

L (V ₂ ) = (S + 1) α = 7 α

L (V ₃ ) = 2Sα = 12 α

L (V ₄ ) = (K ₁ -2S) α = 31 α

L (V ₅ ) = (K ₁ - (S + 1)) α = 36 α

L (V ₆ ) = (K ₁ -1) α - 42 α

L (V ₇ ) = K ₁ α = 43 α

Still by way of example. the case Q _S = 64 with N = 8 gives us Q = 64 and S = 3.

K ₁ ≤ S ² + 45 = 9 + 12 = 21

We therefore take K ₁ = 21, with the eight luminance settings such as:

L (V ₀ ) = α ε which is symbolized by 0 L (V ₁ ) = α + L (V ₀ ) """" 1 L (V ₂ ) = 4α + L (V ₀ ) """" 4 L (V ₃ ) = 6α + L (V ₀ ) """" 6 L (V ₄ ) = 15α + L (V ₀ ) """" 15 L (V ₅ ) = 17α + L (V ₀ ) """" 17 L (V ₆ ) = 20α + L (V ₀ ) """" 20 L (V ₇ ) = 21α + L (V ₀ ) """" 21 The Q _S gray levels given in the following table can be obtained by associating with each of these signals, three luminances (one with each of the sub-times T ₀ , T ₁ and T ₂ ).

The groups of four coefficients in general are built on the model K _χ -2S, K _χ - (S + 1), K _x -1 / K _x , with x going from 1 to a.

These coefficients K _x , the number of (N / 4) -1 are respectively assigned to a group of four luminances, K _x being such that:

if S odd: K _x ≤ K _x-1 + S ² + 2S

if S even: K _x ≤ K _x-1 + S ² + 3S-1 Let us consider a new example with Q _S = 256 and N = 16. The table of the possible gray number gives us Q = 357 for S = 4.

So we have a = (N / 4) -1 = 3

and K _a = K ₃ ≥ Q _S -1 / S = 255/4

and therefore K ₃ ≥ 64

and K ₃ ≤ (Q-1) / S = 356/4 = 89

We then take for example K ₃ = 64.

He comes :

L (V ₀ ) = αε

L (V ₁ ) = α + L (V ₀ )

L (V ₂ ) = α (S + 1) + L (V ₀ ) = 5 α + L (V ₀ )

L (V ₃ ) = α.2S + L (V ₀ ) = 8α + L (V ₀ )

L (V ₄ ) = α (K ₁ -2S) + L (V ₀ ) = (K ₁ -8). α + L (V ₀ )

L (V ₅ ) = α (K ₁ - (S + 1)) + L (V ₀ ) = (K ₁ -5). α + L (V ₀ )

L (V ₆ ) = α (K-1) + L (V ₀ )

L (V ₇ ) = αK ₁ + L (V ₀ )

L (V ₈ ) = α (K ₂ -8) + L (V ₀ )

L (V ₉ ) = α (K ₂ -5) + L (V ₀ )

L (V ₁₀ ) = α (K ₂ -1) + L (V ₀ )

L (V ₁₁ ) = α.K ₂ + L (V ₀ )

L (V ₁₂ ) = α (K ₃ -8) + L (V ₀ )

L (V ₁₃ ) = α (K ₃ -5) + L (V ₀ )

L (V ₁₄ ) = α (K ₃ -1) + L (V ₀ )

L (V ₁₅ ) = α.K ₃ + L (V ₀ ) K ₃ being equal to 64, we have the last four luminances:

L (V ₁₅ ) = 6 4 α + L (V ₀ )

L (V ₁₄ ) = 63 α + L (V ₀ )

L (V ₁₃ ) = 59 α + L (V ₀ )

L (V ₁₂ ) = 56 α + L (V ₀ )

K ₁ and K ₂ being determined from K ₃ , we then have multiple choices for K ₁ and K ₂ :

K ₁ ≤ S ² + 5S-1 i.e. K ₁ ≤ 35

K ₂ ≤ K ₁ + S ² + 3S-1 or K ₂ ≤ K ₁ +27

K ₃ ≤ K ₂ + S ² + 3S-1 either 64 ≤ K ₂ +27 or K ₂ ≥ 37 which gives double inequality:

K ₁ ≤ 35

K ₁ +27 ≥ K ₂ ≥ 37

K ₁ must therefore be at most equal to 35 and K ₂ to 62.

We can take for example K ₁ = 24 and K ₂ = 46. Hence the values of the two intermediate groups of luminances:

L (V ₄ ) = 15α + L (V ₀ )

L (V ₅ ) = 19α + L (V ₀ )

L (V ₆ ) = 23α + L (V ₀ )

L (V ₇ ) = 24α + L (V ₀ )

L (V ₈ ) = 38 α + L (V ₀ )

L (V ₉ ) = 41 α + L (V ₀ )

L (V ₁₀ ) = 45α + L (V ₀ )

L (V _{1 1} ) = 46 α + L (V ₀ )

It is clear that by following these different phases, there is a choice between multiple practical solutions, both for the intermediate K _x values, and for the possible luminance combinations for the same gray level when Q> Q _S . This redundancy can be used to minimize residual consumption problems, code reversals, linkages, etc.

To minimize the transitions, the combination of the S values is preferably done in an increasing or decreasing arrangement. In the case of line sub-times, one can follow an increasing order for one line parity and decreasing for the other, so as to minimize the voltage differences both for a uniform gray range and for a random series of levels of Grey.

Thus, in Figure 6 is shown a column signal using an increasing arrangement for successive lines Rj, R (j + 1), R (j + 2) 'R (j + 3), j being the index of the line , and in FIG. 7, a column signal using an increasing then decreasing arrangement.

For a given gray level, when several choices of coefficients are possible, we prefer the combination which minimizes the voltage (or coefficient) differences. For example, in the case N = 8, S = 3, Q _s = 64, the level G = 41 will be obtained by 6, 15, 20 rather than by 0, 20, 21.

Redundancy can also be used by producing several combinations for the same gray and by rotating these different combinations from one column output to the other (in the event of optical effects linked to code reversals).

It can be noted that a command mode making it possible to describe more than 256 gray levels can be useful for obtaining an image with a palette of gray having a response closer to a real image (correction of ɣ).

the application of the method of the invention to a color screen does not modify the preceding description: the term "shades of gray" covers that of "shades of color". The essential difference comes from the data source which provides information in parallel on the three colors red, green and blue. The transition to color for a matrix screen is obtained, in a manner known to those skilled in the art, by means of one of the following two methods:

- the first consists in tripling the column electrodes and placing opposite these columns either a filter or a colored phosphor depending on the type of screen. In this case, the three colors are addressed in parallel and the addressing device must be tripled;

- the second consists in successively validating the red, green and blue phosphors (EFM: switched anode) and in this case, we keep the same structure of "drivers" as for a monochrome screen by adding however a memory map by color (memory of line or weft in accordance with the validation of colors on the line or weft) directly after the data source, a multiplexer allowing to validate the data of the color to be processed. The disadvantage of this mode is the tripling of clock speeds since it is necessary to process the three colors in series, in a time which must remain less than that of the retinal persistence, which is approximately 20 ms.

It is understood that the present invention has only been described and shown as a preferred example and that its constituent elements can be replaced by equivalent elements without, however, departing from the scope of the invention.

Claims

1. A method of displaying different levels of gray on a matrix screen composed of pixels arranged in R rows and M columns of images capable of having Q _S gray levels, characterized in that each image is obtained by addition on each pixel , during a step of recording the image data line by line, during S sub-times of identical duration (lines or frames, S being greater than or equal to 2), of a succession of luminances L (Vj) discrete chosen from N (N ≥ 4) with 0 ≤ i ≤N-1, each luminance L (V _i ) being associated with a voltage V _j applied to the corresponding column, these luminances are such that any hue value gray between 0 and Q _S -1 can be defined by adding S of these luminances; in that whatever the addressing phase, therefore of the current sub-time, any luminance among the N possible is selectable, these luminances are such that if one defines the two extreme luminances L (V ₀ ) corresponding to the luminance minimum and L (V _N-1 ) corresponding to the maximum luminance by the following equalities:

L (V ₀ ) = αε and L (V _N-1 ) = αK _a + L (V ₀ ) ε being a low value and α a proportionality coefficient equal to L (V _N-1 ) -L (V ₀ ) ) / K _a where K _a is a coefficient indicated by a = (N / 4) -1, the N-2 other luminances are then expressed by the following relationships:

L (V _N-2 ) = α (K _a -1) + L (V ₀ )

L (V _N-3 ) = α (K _a - (S + 1)) + L (V ₀ )

L (V _N - ₄ ) = α (K _a -2S) + L (V ₀ ) L (V _N-5 ) = α.K _a-1 + L (V ₀ )

L (V _N-6 ) = α (K _a-1 -1) + L (V ₀ )

L (V _N-7 ) = α (K _a-1 - (S + 1)) + L (V ₀ )

L (V _N-8 ) = α (K _{a- 1} -2S) + L (V ₀ )

L (V _N-9 ) = α.K _a-2 + L (V ₀ )

.

L (V ₇ ) = αK ₁ + L (V ₀ )

L (V ₆ ) = α. (K ₁ -1) + L (V ₀ )

L (V ₅ ) = α (K ₁ - (S + 1)) + L (V ₀ )

L (V ₄ ) = α (K ₁ -2S) + L (V ₀ )

L (V ₃ ) = α.2S + L (V ₀ )

L (V ₂ ) = α (S + 1) + L (V ₀ )

L (V ₁ ) = α + L (V ₀ ) where K _x , with x ranging from a to 1, are coefficients of (N / 4) -1 respectively assigned to a group of four luminances; K _x being such that: for x = 1, if S is odd K ₁ ≤S ² + 4S

if S is even K ₁ ≤S ² + 5S-1 for x ranging from (a-1) to 2

if S is odd K _x ≤K _x-1 + S ² + 2S

if S is even K _x ≤K _x-1 + S ² + 3S-1 and for x = a, whatever S, (Q-1) / S≥K _a ≥ (Q _S -1) / S, and in that these N selectable luminances are obtained by adjusting the N voltages V ₀ , ...., V _N-1 and make it possible to obtain a number Q (Q≥Q _S ) of selectable gray equal to: if S is odd : Q = S (aS ² + (2a + 2) · S) + 1 if S is even: Q = S (aS ² + (3a + 2). Sa)) + 1 and for N = 4: Q = (S + 1) ²

with L (V ₀ ) = αε, L (V ₁ ) = α + L (V ₀ ), L (V ₂ ) = α (S + 1) + L (V ₀ ) and L (V ₃ ) = α ( S + 2) + L (V ₀ ).

2. Method according to claim 1, characterized in that it comprises the following steps:

- sending, from a source of images to be displayed (20) of data in the form of a binary address, corresponding to the gray level code to be displayed, in a transcoding matrix (22);

- sending, simultaneously, synchronized signals to a screen controller (21) so that it successively supplies the addresses of the S sub-times either to the transcoding matrix (22), or to a logic multiplexer device (32) arranged upstream of the analog multiplexer device (26) controlling the screen (27), this analog multiplexer being connected to a generator of at least N voltages;

- For a given sub-time, sending of the address of the voltage to be switched from the transcoding to a set of shift registers (28, 31) associated with storage registers (29, 33);

- transfer of the content of the associated registers (29, 33) in the analog control multiplexers (26) of the screen either directly or through a logical multiplexer device (32);

- switching of the selected voltage on the column of the screen (27).

3. Method according to claim 2, characterized in that the addition of the luminances during the S sub-time is done using combinations of the voltage values according to an increasing or decreasing arrangement.

4. Method according to claim 3, characterized in that in the case of line sub-time we follow an order c ro i s sa nt for a line parity and a decreasing order for the other line parity.

5. System for implementing the method according to any one of the preceding claims, characterized in that it comprises:

- a digital data source (20) to be displayed;

- a screen controller (21) receiving synchronization signals (SS) from the data source, which delivers S sub-time addresses either to a transcoding circuit (22) or to a logic multiplexer device (32) disposed upstream of the analog multiplexer device being connected to a generator of at least N voltages;

- a data storage system (23);

- a circuit for controlling the columns of the screen (24);

- a generator (25) of discrete voltages;

the transcoding circuit (22) connected to the digital data source (20) receiving from the latter the binary addresses corresponding to the gray level code to be displayed and delivering the address of the voltage to be switched to a control circuit ( 24) allowing to validate 1 among N discrete analog voltages.

6. System according to claim 5, characterized in that the screen controller (21) is linked to the data storage system (23), in that the data storage system (23) comprises shift registers ( 28) associated with storage registers (29), and in that the screen column control circuit (24) comprises several circuits (26) making it possible to select a voltage from among several discrete voltages, this voltage controlling the column considered from the screen (27).

7. System according to claim 5, characterized in that the screen controller (21) is linked directly to the screen control means, in that the transcoding circuit (22) comprises corresponding transcoding sub-matrices each in a sub-time, in that the data storage system (23) comprises shift registers (31) in parallel each associated with a register (33) and each linked to a transcoding sub-matrix, and in that the screen column control circuit includes circuits (26) making it possible to select a voltage from among several discrete voltages, this voltage controlling the column considered on the screen, and digital multiplexers (32) linked to the controller and disposed between the associated registers (33) and said circuits (26).