EP0623912A1 - Method and apparatus for the generation of gray scale levels in a passive matrix liquid crystal display - Google Patents

Abstract

A surface with a discernible grey level being obtained by activating a certain proportion of the pixels of this surface, the screen is virtually divided into blocks of pixels all of the same dimensions, and, for each discernible grey level desired, a set of patterns is defined in advance, each representing one block, the various patterns of the same set all having the same proportion of active pixels, for example two out of sixteen for a grey of 2/16th in the scale going from white to black (20-27), but a different arrangement of the inactive pixels and of the active pixels, and, for displaying each pixel of the image, a pattern of the set corresponding to the desired grey level is selected, and the pixel is displayed with the active or inactive state of the point having the same position in the selected pattern. On each redefinition of an image, a different pattern (from 20 to 27) is chosen. Applications: static-image display devices, especially the video phone, the "Minitel", or portable computers. <IMAGE>

Description

The present invention relates to a method for generating a visual appearance of different levels of gray in a liquid crystal display screen with passive pixel matrix incapable of generating really gray points but only an active or inactive state for each pixel, a surface with an apparent level of gray being obtained by activating a certain proportion of the pixels, and the screen being virtually divided into blocks of pixels all of the same dimension, however that dot patterns are defined in advance, patterns each representing a block, each of the patterns corresponding to one of the gray levels due to the fact that it has a number of active points corresponding to this gray level, and a pixel contained in an image block being displayed with the state, active or inactive , of the point having, in a pattern corresponding to the gray level desired for said pixel, the same position as the pixel in the block which contains it.
It also relates to a device for generating the appearance of gray levels in a passive pixel matrix liquid crystal display screen virtually divided into pixel blocks all of the same dimension, comprising a wired combinational circuit, which calculates the state in which a pixel must be displayed as a function of its position in a block and of the gray level desired for this pixel, and which is provided for this purpose with input terminals of pixel coordinates and input terminals "gray" to each receive a bit for defining the gray level. The invention finds an application in still image display devices, in particular videophone, "Minitel", or portable computers.

A method and a device for generating different levels of gray in a crystal display screen liquids is known from document DE 39 06 924. In the system according to this document the screen is divided into blocks each containing several pixels, and a desired gray level is obtained by activating a certain proportion of the pixels of a block according to the desired gray level, and the choice of the position of the pixels which are activated is modified over time by cyclic shifting of the position of the active pixels within a block. Because the shift of the active points is relatively regular, it is to be feared that there will appear new harmful visual effects, different from those which the process of this document eliminates. Furthermore, the circuit proposed for implementing the method is relatively complex and includes a large number of logic elements.

The invention proposes to provide a process that is both simpler and offering more flexibility as regards the determination of the patterns to be displayed for each gray level, and which also allows the use of a circuit comprising fewer elements. logical.
To this end, the method according to the invention is remarkable in that a set comprising a limited number of basic patterns is defined in advance, each of the patterns of a set comprising a number of active dots per pattern equal to a power of two, in that the composition of the basic patterns is such that each position of an active pixel is exclusively used in only one of the basic patterns of the game, and in that one pattern for generating a gray level not provided for in the pattern set is constructed by superimposing several patterns in this set.
The superimposition of two (or more) basic patterns corresponding to two different gray levels makes it possible to generate intermediate gray levels between two gray levels for which there is a basic pattern, and the number of basic patterns can be this fact be reduced, which simplifies the circuit for implementing the method.

$\mathit{\text{P1}}\text{=}\mathit{\text{X0}}\text{⊕}\mathit{\text{Y1}}$

$\mathit{\text{P2}}\text{=}\mathit{\text{X1}}\text{⊕}\mathit{\text{Y0}}\text{⊕}\mathit{\text{Y1}}$

$\mathit{\text{P3}}\text{=}\mathit{\text{X1}}\text{⊕}\mathit{\text{X0}}$

Ces aspects de l'invention ainsi que d'autres aspects plus détaillés apparaîtront plus clairement grâce à la description suivante d'un mode de réalisation non limitatif.

• La figure 1 est un exemple d'un ensemble de seize motifs, pour un niveau de gris de 1/16^e.
• La figure 2 est un exemple d'un ensemble de huit motifs, pour un niveau de gris de 1/8^e.
• La figure 3 est un exemple d'un ensemble de quatre motifs, pour un niveau de gris de 1/4.
• La figure 4 est un exemple d'un ensemble de deux motifs, pour un niveau de gris de 1/2.
• La figure 5 est un exemple d'évolution de la position d'un motif dans une matrice au cours de seize trames successives numérotées de A à P.
• La figure 6 est un schéma d'un dispositif complet.
• La figure 7 est un schéma d'une partie de dispositif, avec un circuit combinatoire câblé, deux demi-circuits de brassage, et un additionneur.
• La figure 8 est un schéma d'un circuit combinatoire câblé selon l'invention.
• La figure 9 est un schéma d'un circuit de brassage selon l'invention.

For a periodic redefinition of the patterns, a set of several different sets of basic patterns is advantageously defined in advance, each of these sets meeting the rule that each position of an active pixel is exclusively used in only one of the patterns of base of the same game, and the periodic redefinition of the patterns is carried out by cyclically selecting all the games of this set in turn.
This makes it possible to avoid that the eye can see the patterns of points, thanks to the fact that a periodic redefinition provides one after the other different patterns that the eye does not have time to discern from each other.
When an area of the same gray level regularly covers several neighboring blocks of pixels in the image, this may cause, by its geometrically repetitive character, the visual appearance of drawings in the area in question.
To avoid this, when the same gray level is desired for two pixels, one of which is located in a block and the other in a neighboring block, for each of these two pixels a set of patterns is selected from different sets .
A device according to the invention is remarkable in that, "n" being an integer and the number of "gray" input terminals being n, said wired combinational circuit comprises a pixel state definition circuit which is provided with two sets of n pixel coordinate input terminals to each receive a pixel coordinate bit and a "black" input for a bit possibly indicating that the pixel is 100% black , and which comprises n "OU-exclusive" gates, each with two inputs each connected to one of the coordinate input terminals, n "AND" gates, each with at least two inputs, one of which is respectively connected to the output of one of the "OR-exclusive" doors and the other is connected to one of the "gray" input terminals, and an "OR" output door which provides on its output the state to be given to the pixel, and has n +1 inputs, of which n are each connected to the output of one of the "AND" gates, and one is connected to the "black" input and, in assigning a rank to each of "OR" gates and to each of the "AND" gates, each output of an "OR" gate is connected to an input of each of the "AND" gates of higher number if there are any.
Such a circuit makes it possible, while remaining relatively simple, to calculate the definition of a pixel on the basis of all different patterns.
Said wired combinational circuit advantageously comprises, in series in the path of certain coordinate bits, an adder circuit with two groups of n inputs and with n outputs, one of the groups of n inputs is connected to n input terminals of coordinates, however that n conductors each carrying a bit indicating a picture number are connected to the other group of n inputs, the n outputs of the adder are connected to one of the input sets of coordinates of the state definition circuit pixel.
This allows you to change the pattern between one image definition and the next.
The combinatorial circuit also advantageously comprises, in series in the path of the coordinate bits, a mixing circuit made up of logic elements modifying the coordinate bits.
It has been found experimentally that the presence of such a mixing circuit considerably reduces the risk of a visual appearance of drawings (artefacts) in a large area with the same gray level.
The number n being even, each brewing half-circuit advantageously consists of two brewing half-circuits, each with n input terminals of coordinates, and n outputs, the least significant bits of each of the coordinates are brought at one of the half-circuits, the most significant bits are brought to the other half-circuit.
The number n being equal to four, each brewing half-circuit is made up of logical elements representing the following Boolean equations, the four inputs being called X0, X1 for the abscissa coordinates, Y0, Y1 for the ordinate coordinates , and the outputs being called P0-P3:

$\mathit{\text{P0}}\text{=}\mathit{\text{X1}}\text{⊕}\mathit{\text{Y0}}$

$\mathit{\text{P1}}\text{=}\mathit{\text{X0}}\text{⊕}\mathit{\text{Y1}}$

$\mathit{\text{P2}}\text{=}\mathit{\text{X1}}\text{⊕}\mathit{\text{Y0}}\text{⊕}\mathit{\text{Y1}}$

$\mathit{\text{P3}}\text{=}\mathit{\text{X1}}\text{⊕}\mathit{\text{X0}}$

These aspects of the invention as well as other more detailed aspects will become more clearly apparent from the following description of a nonlimiting embodiment.

• Figure 1 is an example of a set of sixteen patterns, for a gray level of 1/16 ^th .
• Figure 2 is an example of a set of eight patterns, for a gray level of 1/8 ^e .
• Figure 3 is an example of a set of four patterns, for a gray level of 1/4.
• Figure 4 is an example of a set of two patterns, for a gray level of 1/2.
• FIG. 5 is an example of evolution of the position of a pattern in a matrix during sixteen successive fields numbered from A to P.
• Figure 6 is a diagram of a complete device.
• FIG. 7 is a diagram of a part of a device, with a wired combinational circuit, two patching half-circuits, and an adder.
• Figure 8 is a diagram of a wired combinational circuit according to the invention.
• Figure 9 is a diagram of a patch circuit according to the invention.

• -- une mémoire 39, dans laquelle sont placées des données G0,G1,G2,G3,N définissant pour chaque pixel un niveau de gris,
• -- un circuit combinatoire câblé 42 qui calcule selon le procédé de l'invention l'état d'un pixel en fonction de sa position dans une matrice et en fonction des bits de données G0-G3 et N définissant la teinte désirée pour ce pixel. Une matrice contenant quatre motifs de 4×4 possède 16×16 points et une position est définie par quatre bits de ligne L0-L3 et quatre bits de colonne C0-C3. Ce circuit 42 comporte en pratique quatre circuits en parallèle non représentés pour travailler sur quatre pixels à la fois. Une horloge non représentée a un temps de cycle d'environ 0,7 µS, et le circuit 42 délivre ainsi toutes les 0,7 µS l'état à afficher pour quatre pixels, ce qui demande donc environ 0,18 µS par pixel. Un écran comporte par exemple 320×240 pixels. La redéfinition complète d'un écran pourra donc être réalisée toutes les : 0,18 µS × 320 × 240 = 0,014 s, soit à une fréquence d'environ 70 Hz,
• -- un écran 44 d'affichage à cristaux liquides à matrice de pixels passive,
• -- un circuit de séquencement 45 qui sélectionne tour à tour tous les pixels d'une image et fournit à chaque fois à la mémoire 39 l'adresse afférente ADR, et au processeur 42 ainsi qu'à l'écran 44 les coordonnées C0-C3,L0-L3 du pixel dans l'image. La sortie du processeur 42 est directement reliée à l'écran pour lui fournir l'état OUT du pixel courant, qu'il est capable de mémoriser grâce à l'effet de capacité mentionné plus haut.

Les coordonnées d'un pixel sont définies par les quatre bits de colonne C0-C3 et par les quatre bits de ligne L1-L3. Les bits L0-L1 et les bits C0-C1 définissent la position du pixel dans un bloc, les bits L2-L3 et les bits C2-C3 définissent la position du bloc dans une matrice. Les bornes d'entrée de coordonnées sont désignées par ces références.
Un des quatre circuits constituant le circuit 42 de la figure 6 est représenté plus en détail sur la figure 7. Il comporte :

• un circuit 38 de définition d'état de pixel, qui sera décrit en regard de la figure 8,
• en série dans le chemin des bits de coordonnées C0,C1,L0,L1, un circuit de brassage 35 constitué d'éléments logiques modifiant les bits de coordonnées, qui sera décrit en regard de la figure 9.
• en série dans le chemin des bits de coordonnées C2,C3,L2,L3, un circuit de brassage 36 identique au circuit 35.
• également en série dans le chemin des bits de coordonnées, à la suite du circuit de brassage 36, un circuit additionneur 37 à deux groupes de quatre entrées et à quatre sorties. Le groupe de quatre entrées B0-B3 est relié aux quatre sorties P0-P3 du circuit de brassage 36, cependant que quatre conducteurs T0-T3, à chacun desquels est amené un bit d'un multiplet indiquant un numéro d'image (modulo 16), sont reliés à l'autre groupe de quatre entrées A0-A3, et les quatre sorties S0-S3 de l'additionneur sont reliées à des bornes S0-S3 du circuit combinatoire 38. L'additionneur en question est un modèle courant du commerce.

Le circuit 38 de la figure 7 est représenté plus en détail sur la figure 8. Il est muni de quatre bornes d'entrée de coordonnées S0, S1, S2, S3, pour recevoir chacune un bit de coordonnée modifié par le circuit de brassage 36 et l'additionneur 37, de quatre bornes d'entrée de coordonnées P0, P1, P2, P3, pour recevoir chacune un bit de coordonnée modifié par le circuit de brassage 35, de quatre bornes d'entrée G0, G1, G2, G3 "de gris" pour recevoir chacune un des bits de gris, et d'une entrée N "de noir" pour un bit indiquant éventuellement que le pixel est 100% noir. Il est constitué de quatre portes "OU-exclusif" R0, R1, R2, R3, chacune avec deux entrées, de quatre portes "ET", E0, E1, E2, E3, chacune avec au moins deux entrées (deux pour la porte E0, trois pour la porte E1, quatre pour la porte E2, cinq pour la porte E3), et d'une porte de sortie "OU" R9 avec cinq entrées. Les entrées de la porte "OU-exclusif" R0 sont reliées aux bornes d'entrée de coordonnées S0 et P3, les entrées de la porte "OU-exclusif" R1 sont reliées aux bornes d'entrée de coordonnées S1 et P2, les entrées de la porte "OU-exclusif" R2 sont reliées aux bornes d'entrée de coordonnées S2 et P1, les entrées de la porte "OU-exclusif" R3 sont reliées aux bornes d'entrée de coordonnées S3 et P0. La sortie de la porte "OU-exclusif" numéro zéro (R0) est reliée, inversée, à une entrée de la porte "ET" de numéro zéro (E0) et, non inversée, à chacune des portes "ET" de numéro supérieur E1, E2, E3. La sortie de la porte "OU-exclusif" numéro R1 est reliée, inversée, à une entrée de la porte "ET" de numéro E1 et, non inversée, à chacune des portes "ET" de numéro supérieur E2, E3. La sortie de la porte "OU-exclusif" numéro R2 est reliée, inversée, à une entrée de la porte "ET" de numéro E2 et, non inversée, à la porte "ET" de numéro supérieur E3. La sortie de la porte "OU-exclusif" numéro R3 est reliée, inversée, à une entrée de la porte "ET" de numéro E3. Chacune des sorties des portes "ET" est reliée à une entrée de la porte de sortie "OU" R9, qui fournit sur sa sortie "OUT" l'état à donner au pixel. Chaque entrée de gris respectivement G0, G1, G2, G3 est reliée à une entrée de la porte "ET" de numéro respectivement E3, E2, E1, E0, et l'entrée N de noir est reliée à une entrée de la porte "OU" (R9) de sortie.
Il est clair que si la dimension choisie pour les blocs de pixels était différente le circuit pourrait alors être adapté facilement et qu'un circuit différent pouvant fournir les mêmes équations logiques pourrait aussi être imaginé facilement par l'homme du métier.
Un des deux circuits 35 ou 36 de la figure 7 est représenté plus en détail sur la figure 9. Il est constitué de trois portes "NON-OU-exclusif" R10, R11, R14 à deux entrées et de deux portes "OU-exclusif" R12, R13 à deux entrées. Les deux entrées de la porte R11 sont reliées aux bornes X0, Y1. Les deux entrées de la porte R12 sont reliées aux bornes Y0, Y1. Les deux entrées de la porte R13 sont reliées aux bornes X1, X0. Une entrée de la porte R14 est reliée à la sortie de la porte R12 et l'autre à la borne X1. Les sorties des portes R10, R11, R14, R13 sont reliées respectivement aux bornes P0, P1, P2, P3. Ces éléments logiques représentent les équations booléennes suivantes :

$\mathit{\text{P0}}\text{=}\mathit{\text{X1}}\text{⊕}\mathit{\text{Y0}}$

$\mathit{\text{P1}}\text{=}\mathit{\text{X0}}\text{⊕}\mathit{\text{Y1}}$

$\mathit{\text{P2}}\text{=}\mathit{\text{X1}}\text{⊕}\mathit{\text{Y0}}\text{⊕}\mathit{\text{Y1}}$

$\mathit{\text{P3}}\text{=}\mathit{\text{X1}}\text{⊕}\mathit{\text{X0}}$

En pratique, l'entrée des données dans un écran à cristaux liquides se fait en général par groupes de quatre ou de huit bits en parallèle. En conséquence, il sera avantageusement prévu, dans le circuit combinatoire câblé 42 de la figure 6, quatre (ou huit) dispositifs identiques à celui de la figure 7. Les bus (GO, G1, etc, et C0, C1, etc) amènent alors les données concernant quatre pixels en parallèle, et la sortie OUT est réalisée par un bus à quatre conducteurs.Data is permanently available for displaying an image, for example contained in a memory, and making its gray level correspond to each coordinate of a pixel. The fact that in a passive liquid crystal matrix screen, each displayable pixel is active or inactive without possible intermediate level, whereas an image to be displayed comprises for each pixel the indication of a gray level, a surface with a visual appearance of gray is obtained by activating a certain proportion of the pixels of this area. The state of each screen pixel is periodically redefined, the electrical capacity of a liquid crystal cell allowing it to keep information between two redefinitions.
The screen being virtually divided into blocks of pixels all of the same dimensions, the proportion of active pixels is processed at the level of a block. The process, if it is based on square blocks, can give palettes of five shades for a square of 2 × 2, of ten shades for a square of 3 × 3, of seventeen shades for a square of 4 × 4, etc. We notice that for a square of dimension n × n we obtain (n × n) +1 shades. To obtain for example seventeen shades in a scale going from white to black included, by activating a certain proportion of the pixels in a block, it is necessary to be able to obtain a proportion of active pixels ranging from 0/16 ^e to 16/16 ^e , therefore a block must contain a number of pixels equal to a multiple of sixteen; in the present example a block will contain 4 × 4 pixels.
A set of basic patterns of the same dimension as a block is defined, patterns of which each point represents a pixel, either active or inactive, each of these blocks containing, in the example chosen, sixteen points. A limited set can include, for example, the patterns 0, 20, 30, 40 of the figures 1, 2, 3, 4 respectively. The patterns of such a predefined set correspond to a number of active pixels in a block equal to a power of two: a single active pixel in pattern 0 in Figure 1, two active pixels in pattern 20 in Figure 2, four active pixels in pattern 30 in Figure 3, eight active pixels in pattern 40 in Figure 4 If we superimpose the basic patterns 0, 20, 30, 40 in question, we obtain a complex pattern where fifteen pixels are active, no active pixel of a basic pattern being superimposed on an active pixel of another basic motif. Suppose that the desired hue for a pixel is 11/16 ^th (11 = 8 + 2 + 1). The patterns 40 in Figure 4 (eight active points), 20 in Figure 2 (two active points), 0 in Figure 1 (one active point) will be superimposed to give 11/16 ^e .
For each apparent level of gray desired is set to in advance, not only a set of point patterns, but a set of point pattern sets, in which each redefinition will choose a different set.
Figure 1 shows an example of a set of sixteen patterns, for a gray level of 1/16 ^e . Pattern 0, for example, has an active pixel at the top right, Pattern 1 has an active pixel at coordinates X = 2 and Y = 1 (X and Y being counted from 0 to 3, from top to bottom for Y ), etc. The different patterns in this set all have a single point representing an active pixel, but no pattern has an active pixel placed in the same position as in another pattern. At each redefinition, the set of selected patterns always comprises four patterns having respectively one / two / four / eight active points, and each time that of the patterns of the game which comprises an active pixel is selected from the patterns of the whole of the figure. 1, each of the patterns 0 to 15 being thus selected in turn (after the pattern 15, we resume at the pattern 0).
Figure 2 shows an example of a set of eight patterns, for a gray level of 1/8 ^e . Pattern 20, for example, has an active pixel at coordinates X = 0 and Y = 1 and an active pixel at coordinates X = 3 and Y = 3, Pattern 21 has an active pixel at coordinates X = 1 and Y = 0 and an active pixel at coordinates X = 2 and Y = 2, etc. The different patterns in this set all have two points representing an active pixel but no pattern has an active pixel placed in the same position as in another pattern. Of course, the set cannot include more than eight different patterns fulfilling this condition. At each redefinition, that of the patterns of the game which comprises two active pixels is selected from the patterns of the assembly of FIG. 2, each of the patterns 20 to 27 being thus selected in turn (after the pattern 27, we resume at the pattern 20 ).
Figure 3 shows an example of a set of four patterns, for a gray level of 1/4. Pattern 30, for example, has an active pixel at coordinates X = 0 and Y = 0, at coordinates X = 3 and Y = 1, at coordinates X = 3 and Y = 2, and at coordinates X = 0 and Y = 3. Again the different patterns of this set all have four points representing an active pixel but no pattern has an active pixel placed in the same position as in another pattern. Of course, the set cannot include more than four different patterns. At each redefinition, that of the patterns of the game which comprises four active pixels is selected from the patterns of the assembly of FIG. 3, each of the patterns 30 to 33 thus being selected in turn (after the pattern 33, we resume the pattern 30 ).
Figure 4 shows an example of a set of two patterns, for a gray level of 1/2. The two patterns 40, 41 of this set all have eight points representing an active pixel but no pattern has an active pixel placed in the same position as in another pattern. Of course, the set cannot include more than two different patterns. At each redefinition, that of the patterns of the game which comprises four active pixels is selected from the patterns of the assembly of FIG. 4, each of the patterns 40 and 41 thus being selected in turn.
A pattern, consisting of one or more superimposed basic patterns and corresponding to a given gray level, being selected, a pixel occupying a particular position in one of the pixel blocks is displayed with the state, active or inactive, of the point having the same position in the selected pattern. The following example relates to the simple basic pattern 23, but it is easy to transpose it to any pattern consisting of several superimposed patterns. If the coordinates of the processed pixel, relative to the block of the image which contains it, are for example X = 3 and Y = 1 (X and Y going from 0 to 3), and that the pattern 23 of figure 2 is selected , the point of this selected pattern having the same position as the pixel in its block, ie X = 3 and Y = 1, is the point marked "×", it is white, and the pixel will therefore be displayed inactive. With the same pattern 23 selected, but with pixel coordinates for example X = 1 and Y = 1 relative to the block of the image which contains it, the point having the same position as the pixel in its block is the second from from the left and from the top it's black and the pixel will therefore be displayed active.
As there are a maximum of 16 different patterns throughout Figure 1, the count of redefinitions, for the selection of a pattern in Figure 1, is performed modulo 16, and similarly it is performed modulo 8 for l 'set of patterns in Figure 2, modulo 4 for all of the patterns in Figure 3 and modulo 2 for all the patterns in Figure 3. Thus are selected successively over time, in the sets of Figures 1 at 4, the patterns respectively 0 + 20 + 30 + 40, then 1 + 21 + 31 + 41, then 2 + 22 + 32 + 40, then 3 + 23 + 33 + 41, then 4 + 24 + 30 + 40 and so on until 14 + 26 + 32 + 40 and finally 15 + 27 + 33 + 41 before returning to 0 + 20 + 30 + 40.
The composition of the patterns is such that, at each redefinition, in a set of several basic patterns corresponding to different gray levels, that is to say taken in different figures, there are no active pixels. in the same places as in another motif. We can verify that this condition is fulfilled for each of the possible selections.
Of course one can imagine many other sets of the type of those of Figures 2 to 4. Indeed for example, the number of ways to draw a pattern of the type of those of Figure 2 is one hundred and twenty, the number of Ways to draw a pattern like those in Figure 3 is one thousand six hundred and eighty, and the number of ways to draw a pattern like those in Figure 4 is twelve thousand eight hundred seventy. The number of combinations that can be used is however limited by the condition that in two sets corresponding to two different gray levels, a selected pattern from one set must not have active pixels in the same places as a selected pattern from another set. , but there are still a large number of possible combinations.
In order to select a different pattern for each of the neighboring blocks, when an area of the same gray level regularly covers several blocks of neighboring pixels in the image, a set of pattern matrices each containing several neighboring patterns in the two horizontal and vertical directions is defined in advance for each gray level, the different patterns of the same matrix all having a different arrangement of the points representing inactive pixels and dots representing active pixels. For example, a matrix contains sixteen (4 × 4) patterns here. One thus defines for each number of basic active points (one, two, four, eight) a set of sixteen basic matrices different from each other, each containing sixteen basic patterns with the number of active points required. At each redefinition, a matrix from the set of matrices corresponding to the gray level in question is selected, another matrix from the same set being selected at the next redefinition, and so on. Figure 5 shows sixteen matrices. From one matrix to another the position of a given pattern evolves in the matrix. Despite its similarity to Figures 1 to 3, this figure is different, each of its tiles represents a 4 × 4 pixel pattern. The black tile represents a specific basic pattern. At time A, said determined basic pattern is for example located at the top right of the matrix, at the next time (B) it descends from one position, at the next time (C) it descends from one position down and two to the left, and so on (D, E, F, etc.). In addition, at a given moment, for example at time A and for a basic matrix corresponding to a 1/16 ^e gray, the patterns therefore being taken from FIG. 1, the top line of the matrix A contains for example the patterns 7 + 13 + 10 + 0, line 2 contains patterns 2 + 8 + 15 + 5, line 3 contains patterns 1 + 11 + 12 + 6, line 4 contains patterns 4 + 14 + 9 + 3 . The contents at other times are deduced by displacements as explained above. It has been observed that this way of defining the matrices gives a particularly favorable visual perception. It is certain that other ways can also give favorable results, but in any case a certain thing is that certain definitions of matrices and certain ways moving the patterns gives better results than others.
Of course, here again a matrix corresponding to an intermediate gray level is constructed by superposition of the suitable basic matrices. The screen is virtually divided into 4 × 4 block squares, and at each redefinition a pixel is displayed with the state, active or inactive, of the point having in the selected matrix the same position as the pixel in its 4x4 block square . In fact it simply amounts to operating as with a simple pattern that would have 16 × 16 pixels. However, the organization of a device based on such a method thus has an advantageous tree structure.
A device for generating the appearance of gray levels in a passive pixel matrix liquid crystal display screen is shown in FIG. 6.
It comprises :

• a memory 39 in which data G0, G1, G2, G3, N are placed defining for each pixel a gray level,
• a wired combinational circuit 42 which calculates according to the method of the invention the state of a pixel as a function of its position in a matrix and as a function of the data bits G0-G3 and N defining the desired hue for this pixel . A matrix containing four 4 × 4 patterns has 16 × 16 points and a position is defined by four line bits L0-L3 and four column bits C0-C3. This circuit 42 in practice comprises four parallel circuits not shown to work on four pixels at a time. A clock not shown has a cycle time of approximately 0.7 µS, and the circuit 42 thus delivers every 0.7 µS the state to be displayed for four pixels, which therefore requires approximately 0.18 µS per pixel. A screen has for example 320 × 240 pixels. The complete redefinition of a screen can therefore be performed every: 0.18 µS × 320 × 240 = 0.014 s, i.e. at a frequency of around 70 Hz,
• a liquid crystal display screen 44 with a passive pixel matrix,
• a sequencing circuit 45 which selects all the pixels of an image in turn and each time supplies the memory 39 with the relevant address ADR, and the processor 42 and also the screen 44 with the coordinates C0- C3, L0-L3 of the pixel in the image. The output of processor 42 is directly connected to the screen to provide it with the OUT state of the current pixel, which it is able to memorize thanks to the capacitance effect mentioned above.

The coordinates of a pixel are defined by the four column bits C0-C3 and by the four line bits L1-L3. The bits L0-L1 and the bits C0-C1 define the position of the pixel in a block, the bits L2-L3 and the bits C2-C3 define the position of the block in a matrix. The coordinate input terminals are designated by these references.
One of the four circuits constituting the circuit 42 of FIG. 6 is shown in more detail in FIG. 7. It comprises:

• a pixel state definition circuit 38, which will be described with reference to FIG. 8,
• in series in the path of the coordinate bits C0, C1, L0, L1, a cross-connection circuit 35 made up of logic elements modifying the coordinate bits, which will be described with reference to FIG. 9.
• in series in the path of the bits of coordinates C2, C3, L2, L3, a mixing circuit 36 identical to the circuit 35.
• also in series in the path of the coordinate bits, following the patching circuit 36, an adder circuit 37 with two groups of four inputs and four outputs. The group of four inputs B0-B3 is connected to the four outputs P0-P3 of the patch circuit 36, while four conductors T0-T3, to each of which is brought a bit of a byte indicating a picture number (modulo 16 ), are connected to the other group of four inputs A0-A3, and the four outputs S0-S3 of the adder are connected to terminals S0-S3 of the combinational circuit 38. The adder in question is a current commercial model.

The circuit 38 of FIG. 7 is shown in more detail in FIG. 8. It is provided with four input terminals of coordinates S0, S1, S2, S3, to each receive a bit of coordinate modified by the patching circuit 36 and the adder 37, of four input terminals of coordinates P0, P1, P2, P3, to each receive a coordinate bit modified by the patch circuit 35, of four input terminals G0, G1, G2, G3 "gray" to each receive one of the gray bits, and an entry N "of black" for a bit possibly indicating that the pixel is 100% black. It consists of four "OR-exclusive" doors R0, R1, R2, R3, each with two inputs, of four "AND" doors, E0, E1, E2, E3, each with at least two inputs (two for the door E0, three for door E1, four for door E2, five for door E3), and an exit door "OR" R9 with five inputs. The inputs of the "OU-exclusive" gate R0 are connected to the input terminals of coordinates S0 and P3, the inputs of the "OU-exclusive" gate R1 are connected to the input terminals of coordinates S1 and P2, the inputs of the "OR-exclusive" gate R2 are connected to the input terminals of coordinates S2 and P1, the inputs of the "OU-exclusive" gate R3 are connected to the input terminals of coordinates S3 and P0. The output of gate "OR-exclusive" number zero (R0) is connected, inverted, to an input of gate "AND" of number zero (E0) and, not inverted, to each of the gates "AND" of higher number E1, E2, E3. The output of the "OR-exclusive" gate number R1 is connected, inverted, to an input of the "AND" gate of number E1 and, not inverted, to each of the "AND" gates of higher number E2, E3. The output of gate "OR-exclusive" number R2 is connected, inverted, to an input of gate "AND" of number E2 and, not inverted, to gate "AND" of higher number E3. The output of door "OU-exclusive" number R3 is connected, inverted, to an input of door "AND" of number E3. Each of the outputs of gates "AND" is connected to an input of the output gate "OR" R9, which provides on its output "OUT" the state to give to the pixel. Each gray input G0, G1, G2, G3 respectively is connected to an input of the door "AND" of number E3, E2, E1, E0 respectively, and the input N of black is connected to an input of the door " OR "(R9) output.
It is clear that if the dimension chosen for the blocks of pixels were different, the circuit could then be easily adapted and that a different circuit capable of providing the same logic equations could also be easily imagined by those skilled in the art.
One of the two circuits 35 or 36 of Figure 7 is shown in more detail in Figure 9. It consists of three "NON-OR-exclusive" doors R10, R11, R14 with two inputs and two "OR-exclusive doors "R12, R13 with two inputs. The two inputs of gate R11 are connected to terminals X0, Y1. The two inputs of gate R12 are connected to terminals Y0, Y1. The two inputs of door R13 are connected to terminals X1, X0. One input of door R14 is connected to the output of door R12 and the other to terminal X1. The outputs of the doors R10, R11, R14, R13 are connected respectively to the terminals P0, P1, P2, P3. These logic elements represent the following Boolean equations:

$\mathit{\text{P0}}\text{=}\mathit{\text{X1}}\text{⊕}\mathit{\text{Y0}}$

$\mathit{\text{P1}}\text{=}\mathit{\text{X0}}\text{⊕}\mathit{\text{Y1}}$

$\mathit{\text{P2}}\text{=}\mathit{\text{X1}}\text{⊕}\mathit{\text{Y0}}\text{⊕}\mathit{\text{Y1}}$

$\mathit{\text{P3}}\text{=}\mathit{\text{X1}}\text{⊕}\mathit{\text{X0}}$

In practice, data entry into a liquid crystal display is generally done in groups of four or eight bits in parallel. Consequently, it will be advantageously provided, in the wired combinational circuit 42 of FIG. 6, four (or eight) devices identical to that of FIG. 7. The buses (GO, G1, etc., and C0, C1, etc.) bring then the data relating to four pixels in parallel, and the output OUT is produced by a bus with four conductors.

Claims (8)

Method for generating a visual appearance of different gray levels in a passive pixel matrix liquid crystal display screen incapable of generating really gray dots but only an active or inactive state for each pixel, a surface with an apparent level of gray being obtained by activating a certain proportion of the pixels, and the screen being virtually divided into blocks of pixels all of the same dimension, however that dot patterns are defined in advance, patterns each representing a block, each of the patterns corresponding to one of the gray levels because it has a number of active points corresponding to this gray level, and a pixel contained in an image block being displayed with the state, active or inactive, of the point having, in a pattern corresponding to the gray level desired for said pixel, the same position as the pixel in the block which contains it, characterized in that a game comprising a limited number of basic patterns is defined in advance (0 + 20 + 30 + 40), each of the patterns in a set comprising a number of active dots per pattern equal to a power of two (one, two, four, eight) , in that the composition of the basic patterns is such that each position of an active pixel is exclusively used in only one of the basic patterns of the game, and in that a pattern for generating a gray level not provided for in the pattern set is constructed by superimposing several patterns from this set. Method according to claim 1, in which the patterns are periodically redefined, characterized in that a set of several different sets of basic patterns (0 + 20 + 30 + 40, 1 + 21 + 31 + 41, 2 + 22 + 32 + 40, 3 + 23 + 33 + 41, 4 + 24 + 30 + 40, etc.) is defined in advance, each of these games meeting the rule that each position of an active pixel is exclusively used in a only basic patterns of the same set, and the periodic redefinition of the patterns is carried out by cyclically selecting all the sets of this set in turn. Method according to claim 2, characterized in that when the same gray level is desired for two pixels, one of which is located in a block and the other in a neighboring block, for each of these two pixels a set of patterns is selected from different sets. Apparatus for generating the appearance of gray levels in a passive pixel matrix liquid crystal display screen virtually divided into pixel blocks all of the same size, comprising a wired combinational circuit (42), which calculates the state under which a pixel must be displayed as a function of its position in a block and of the gray level desired for this pixel, and which is provided for this purpose with input terminals of coordinates of a pixel and of input terminals " gray "to each receive a bit for defining the gray level, characterized in that," n "being an integer and the number of input terminals (G0-G3) of" gray "input being n, the so-called wired combinational circuit includes a pixel state definition circuit (38) which is provided with two sets of n terminals (P0-P3 + S0-S3) for entering pixel coordinates to each receive a bit of coordinates a pixel and an entry of "black" (N) for a bit possibly indicating that l The pixel is 100% black, and which includes n "OR-exclusive" gates (R0-R3), each with two inputs each connected to one of the coordinate input terminals (S0, P3, S1, P2, S2, P1 , S3, P0), n "AND" gates (E0-E3), each with at least two inputs, one of which is connected respectively to the output of one of the "OR-exclusive" gates and the other is connected to one of "gray" input terminals (G0-G3), and an "OR" output gate (R9) which provides on its output (OUT) the state to give to the pixel, and has n + 1 inputs, of which n are each connected to the output of one of the "AND" doors, and one is connected to the "black" input and, by assigning a rank to each of the "OR" doors and to each of the "AND" doors, each output of an "OR" door is connected to an input of each of the higher-numbered "AND" doors if there are any. Device according to claim 4, characterized in that it comprises, in series in the path of certain bits of coordinates, an adder circuit (37) with two groups of n inputs and n outputs, one of the groups of n inputs (B0-B3) is connected to n coordinate input terminals (C2, C3, L2, L3), however, that n conductors (T0-T3) each carrying a bit indicating a picture number are connected to the other group of n inputs (A0-A3), the n outputs of the adder (37) are connected to one of the input sets of coordinates of the pixel state definition circuit (38). Device according to one of claims 4 or 5, characterized in that it comprises, in series in the path of the coordinate bits, a mixing circuit (35 + 36) made up of logic elements modifying the coordinate bits. Device according to claim 6, characterized in that, the number of coordinate bits being even, the patch circuit consists of two half-patch circuits (35, 36), each with n input terminals (X1, Y0 , X0, Y1) of coordinates, and n outputs (P0-P3), the least significant bits (CO, C1, L0, L1) of each of the coordinates are brought to one of the half-circuits (35) , the most significant bits (C2, C3, L2, L3) are brought to the other half-circuit (36). Device according to Claim 7, characterized in that, n being equal to four, each brewing half-circuit consists of logic elements (R10-R14) representing the following Boolean equations, the four inputs being called X0, X1 for the abscissa coordinates, Y0, Y1 for the ordinate coordinates, and the outputs being called P0-P3:

$\mathit{\text{P0}}\text{=}\mathit{\text{X1}}\text{⊕}\mathit{\text{Y0}}$

$\mathit{\text{P1}}\text{=}\mathit{\text{X0}}\text{⊕}\mathit{\text{Y1}}$

$\mathit{\text{P2}}\text{=}\mathit{\text{X1}}\text{⊕}\mathit{\text{Y0}}\text{⊕}\mathit{\text{Y1}}$

$\mathit{\text{P3}}\text{=}\mathit{\text{X1}}\text{⊕}\mathit{\text{X0}}$

Images