EP0623866A2 - Current source arrangement to produce multiple reference currents - Google Patents
Current source arrangement to produce multiple reference currents Download PDFInfo
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- EP0623866A2 EP0623866A2 EP94106982A EP94106982A EP0623866A2 EP 0623866 A2 EP0623866 A2 EP 0623866A2 EP 94106982 A EP94106982 A EP 94106982A EP 94106982 A EP94106982 A EP 94106982A EP 0623866 A2 EP0623866 A2 EP 0623866A2
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
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- the invention relates to a current source arrangement for generating multiple reference currents for distributed circuit arrangements with a current source that generates a reference current.
- Reference currents are well known, for example from the book Tietze / Schenk: Semiconductor Circuit Technology, Springer-Verlag, 7th edition, 1985, page 356 ff.
- the precision current sources described in the abovementioned literature contain an operational amplifier which controls a transistor on the output side, one output terminal of which is connected on the one hand to the reference potential via a resistor and on the other hand to the feedback input of the operational amplifier. There is a reference voltage at the positive input of the operational amplifier. A load is switched on at the free output of the transistor. The output voltage of the operational amplifier adjusts itself so that the voltage across the resistor becomes equal to the reference voltage, so that the output current is precisely defined.
- the invention is based on the object of specifying a current source arrangement with which the adaptation properties of distributed circuit arrangements can be improved and mutual coupling of the distributed circuit arrangements can be reduced. Furthermore, a use for such an arrangement is to be specified.
- the invention has the advantage that, by dividing the reference current with the aid of transistors arranged in parallel and spatially arranged, which are also included in a regulation for the sum of the reference currents, the matching properties (matching) by the transistors arranged locally in a limited area be improved. Furthermore, the distributed circuit arrangements are largely decoupled, since interference on one line can practically not couple over to another supply line for another of the distributed circuit arrangements. This results in improved global adaptation properties when the distributed circuit arrangements are largely decoupled. Different technology gradients cannot have a very negative impact.
- Embodiments of the invention are characterized in the subclaims.
- the current source arrangement shown in the figure is e.g. B. powered by a positive voltage, the terminals VCC are at 5 V, while the reference potential GND is at 0 V.
- a reference voltage and a resistor R applied to the VR terminal in a circuit part OA designed as an operational amplifier determine a reference current IB.
- the terminal VR is connected to an input of a transistor N31, which forms a differential amplifier in conjunction with a transistor N32.
- This differential amplifier is supplied by a current source from the transistors P31, P32, N33 and N34.
- the current defined by transistors P31 and P32 is mirrored in the differential amplifier by the current mirror from N33 and N34.
- Transistors P33 and P34 are arranged in the load circuit of differential amplifier transistors N31 and N32, which are also connected as current mirrors.
- the connection point of the output circuits of the transistors N32 and P34 forms the output VO of the operational amplifier OA.
- the output VO controls a plurality of transistors connected in parallel, which are represented in the exemplary embodiment by the transistors N1 to N3.
- a common output terminal of each of the transistors is connected to a terminal of the resistor R, the other terminal of which is at reference potential GND.
- the connection point of the transistors N1 to N3 with the resistor R is connected to the control input of the transistor N32 and forms the feedback input VF of the operational amplifier OA.
- the control loop works so that the potential VF at Control input of transistor N32 corresponds to the potential at terminal VR, ie that the reference voltage is present at resistor R.
- Reference voltage and resistance R precisely determine the reference current IB.
- the reference current IB is divided into three reference currents I1 to I3 using the plurality of transistors lying in parallel, in the exemplary embodiment using the transistors N1 to N3.
- the reference currents I1 to I3 then in turn serve to supply distributed circuit arrangements B1 to B3, of which only the circuit arrangement B1 is shown in detail for reasons of clarity. It goes without saying that the circuit arrangements B1 to B3 further circuit parts, for. B. SZ, VC2 or VC3, which in turn may also be distributed, can be connected downstream. It is therefore also possible to view the respective circuit part B1, B2 or B 3 together with the circuit part SZ, VC2 or VC3 connected downstream as a respective distributed circuit arrangement.
- the three transistors N1 to N3 are arranged spatially close to one another, preferably close together, so that the adaptation properties in a locally narrowly limited area are decisive for the reference currents I1 to I3. Any interferences have the same effect on each of the transistors.
- the well-defined reference currents in this way become the distributed circuit arrangements, e.g. B. three digital-to-analog converters.
- a triple digital-to-analog converter can be generated with the same transistors N1 to N3 from the central reference current IB three well-defined and adapted reference currents I1 to I3, which ensure optimal synchronization of the distributed circuit arrangements.
- such a reference current generation ensures that faults on one line, ie faults with respect to one of the distributed ones Circuitry can practically not couple to the other distributed circuitry.
- a further improvement in the generation of the reference currents I1 to I3 provides that a transistor TC connected as a capacitance is switched to the reference potential from the output VO of the operational amplifier OA, which controls the control connections of the transistors N1 to N3 generating the reference currents.
- TC has a smoothing function.
- Each individual reference current I1 to I3 is supplied locally to a current source arrangement in the distributed circuit arrangement supplied by it, as is illustrated, for example, in block B1, and controls it.
- Blocks B2 and B3 are constructed in the same way as B1.
- the current source implemented locally in the respective distributed circuit arrangement is described in the exemplary embodiment with reference to block B1.
- the current source consists essentially of transistors P11 and P12, which are connected in series with their output circuits and form a cascode stage.
- One terminal of transistor P11 is supplied by terminal VCC.
- the terminal of transistor N1 carrying the potential VB is connected to the control input of transistor P11 and to an output terminal of transistor P12.
- P11 is a p-channel transistor that is designed to be comparatively large.
- the transistor P12 essentially has the task of largely decoupling the connection point of the transistor P11 to the transistor P12 from the control input of the transistor P11 or the associated output terminal of the transistor P12 and to improve the static characteristic of the current source by increasing the differential output resistance.
- a circuit arrangement SZ Downstream of block B1 is a circuit arrangement SZ, which for example forms a current cell for a digital-to-analog converter.
- the current source is advantageously constructed similarly to the circuit B1.
- the transistors P21 to P23 correspond to the transistors P11 to P13.
- the current source IQ supplying the transistor P23 is e.g. B. designed corresponding to the transistors P14, N11 and N12.
- the one output terminal of the transistor P22 is connected to the common connection point of the output circuits of two switch transistors S1 and S2.
- S1 and S2 are controlled by antivalent or complementary signals S and SQ.
- the output terminals O and OQ of the switch transistors S1 and S2 alternately carry the current flowing through P21 and P22.
- transient switching operations of the switch transistors S1 and S2 can at most only affect the control to a small extent of P21 and thus affect the reference current I1.
- the reference current I1 is fed via transistor P12 into transistor P11, which forms a current mirror with P21.
- the structure of block B1 and that shown in FIG. 1 are preferably the same downstream current cell SZ, in particular the control loop executed therein, is achieved that the drain potentials of the transistors P11 and P21 are largely the same. An optimal synchronization of these two circuit parts is thus achieved.
- block B1 can be followed by further current cells in the same way, which are provided, for example, for a digital-to-analog converter. This is shown schematically on the basis of blocks VC2 and VC3, which are connected downstream of blocks B2 and B3 and which accordingly each represent a digital-to-analog converter.
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Abstract
Description
Die Erfindung betrifft eine Stromquellenanordnung zur Erzeugung mehrfacher Referenzströme für verteilte Schaltungsanordnungen mit einer Stromquelle, die einen Bezugsstrom erzeugt.The invention relates to a current source arrangement for generating multiple reference currents for distributed circuit arrangements with a current source that generates a reference current.
Stromquellen zur Erzeugung von Referenz-bzw. Bezugsströmen sind hinlänglich bekannt, beispielsweise aus dem Buch Tietze/Schenk: Halbleiter-Schaltungstechnik, Springer-Verlag, 7. Auflage, 1985, Seite 356 ff. Die in der vorgenannten Literaturstelle beschriebenen Präzisions-Stromquellen enthalten einen Operationsverstärker, der ausgangsseitig einen Transistor steuert, dessen einer Ausgangsanschluß einerseits über einen Widerstand an Bezugspotential und andererseits an den Rückkopplungseingang des Operationsverstärkers gelegt ist. An dem positiven Eingang des Operationsverstärkers liegt eine Referenzspannung. Am freien Ausgang des Transistors wird eine Last angeschaltet. Die Ausgangsspannung des Operationsverstärkers stellt sich dabei so ein, daß die Spannung an dem Widerstand gleich der Referenzspannung wird, so daß der Ausgangsstrom präzise definiert wird.Power sources for generating reference or. Reference currents are well known, for example from the book Tietze / Schenk: Semiconductor Circuit Technology, Springer-Verlag, 7th edition, 1985, page 356 ff. The precision current sources described in the abovementioned literature contain an operational amplifier which controls a transistor on the output side, one output terminal of which is connected on the one hand to the reference potential via a resistor and on the other hand to the feedback input of the operational amplifier. There is a reference voltage at the positive input of the operational amplifier. A load is switched on at the free output of the transistor. The output voltage of the operational amplifier adjusts itself so that the voltage across the resistor becomes equal to the reference voltage, so that the output current is precisely defined.
In Anwendungsschaltungen mit mehrfach gleichen Strukturen, wie z. B. einem Mehrfach-DA-Umsetzer ist eine zuvor beschriebene Präzisionsstromquelle entsprechend mehrfach erforderlich, was sehr aufwendig ist. Üblicherweise erfolgt die Stromversorgung derartiger Mehrfachstrukturen deshalb mit Hilfe einer Stromspiegelschaltung, bei der an zentraler Stelle ein Referenzstrom in einen als Diode geschalteten MOS-Transistor geleitet wird. Der Referenzstrom wird häufig mittels einer externen Quelle oder mit Hilfe eines Widerstandes erzeugt. Weitere zu dem als Diode geschalteten MOS-Transistor gleichartige Transistoren werden dann als Stromquellen in den einzelnen Schaltungsanordnungen der Mehrfachstrukturen an das erhaltene Referenzpotential geschaltet. Durch die Anordnung der Stromquellen mit Hilfe eines Referenztransistors, der als Diode geschaltet ist, und der weiteren, den Mehrfachstrukturen zugeordneten Transistoren ergibt sich ein (räumlich) verteilter Stromspiegel. Die Anpassung (matching) der Mehrfachstrukturen im Hinblick auf gleiche oder vergleichbare Eigenschaften sind aufgrund des verteilten Stromspiegels und der verteilten Schaltungsanordnungen schlecht definiert und können zu Verkopplungen über die gemeinsame Vorspannungsleitung führen.In application circuits with multiple identical structures, such as. B. a multiple DA converter, a previously described precision current source is required several times, which is very expensive. Usually, multiple structures of this type are therefore supplied with the aid of a current mirror circuit in which a reference current is conducted at a central point into a MOS transistor connected as a diode. The reference current is often generated using an external source or a resistor. Further transistors similar to the MOS transistor connected as a diode are then used as current sources in the individual circuit arrangements of the multiple structures connected to the reference potential obtained. The arrangement of the current sources with the aid of a reference transistor, which is connected as a diode, and the further transistors assigned to the multiple structures result in a (spatially) distributed current mirror. The adaptation (matching) of the multiple structures with regard to the same or comparable properties are poorly defined due to the distributed current mirror and the distributed circuit arrangements and can lead to coupling via the common bias line.
Der Erfindung liegt die Aufgabe zugrunde, eine Stromquellenanordnung anzugeben, mit der die Anpassungseigenschaften verteilter Schaltungsanordnungen verbessert und gegenseitige Verkopplungen der verteilten Schaltungsanordnungen verringert werden können. Weiterhin soll eine Verwendung für eine derartige Anordnung angegeben werden.The invention is based on the object of specifying a current source arrangement with which the adaptation properties of distributed circuit arrangements can be improved and mutual coupling of the distributed circuit arrangements can be reduced. Furthermore, a use for such an arrangement is to be specified.
Diese Aufgabe wird durch die Merkmale der Patentansprüche 1 und 8 gelöst.This object is solved by the features of claims 1 and 8.
Die Erfindung hat den Vorteil, daß durch die Aufteilung des Bezugsstroms mit Hilfe parallel liegender, räumlich beieinander angeordneter Transistoren, die zudem in eine Regelung für die Summe der Referenzströme einbezogen sind, die Anpassungseigenschaften (matching) durch die lokal in einem begrenzten Gebiet beieinander angeordneten Transistoren verbessert werden. Weiterhin werden die verteilten Schaltungsanordnungen weitgehend entkoppelt, da Störungen auf einer Leitung praktisch nicht auf eine andere Versorgungsleitung für eine andere der verteilten Schaltungsanordnungen überkoppeln kann. Somit ergeben sich bei weitgehender Entkopplung der verteilten Schaltungsanordnungen verbesserte globale Anpassungseigenschaften. Unterschiedliche Technologiegradienten können sich damit nicht stark negativ auswirken.The invention has the advantage that, by dividing the reference current with the aid of transistors arranged in parallel and spatially arranged, which are also included in a regulation for the sum of the reference currents, the matching properties (matching) by the transistors arranged locally in a limited area be improved. Furthermore, the distributed circuit arrangements are largely decoupled, since interference on one line can practically not couple over to another supply line for another of the distributed circuit arrangements. This results in improved global adaptation properties when the distributed circuit arrangements are largely decoupled. Different technology gradients cannot have a very negative impact.
Ausgestaltungen der Erfindung sind in Unteransprüchen gekennzeichnet.Embodiments of the invention are characterized in the subclaims.
Die Erfindung wird nachfolgend anhand eines Ausführungsbeispiels näher erläutert, das in Figur 1 dargestellt ist.The invention is explained in more detail below using an exemplary embodiment which is shown in FIG. 1.
Die in der Figur gezeigte Stromquellenanordnung wird z. B. von einer positiven Spannung versorgt, wobei die Klemmen VCC auf 5 V liegen, während das Bezugspotential GND auf 0 V liegt.The current source arrangement shown in the figure is e.g. B. powered by a positive voltage, the terminals VCC are at 5 V, while the reference potential GND is at 0 V.
Eine an einem als Operationsverstärker ausgebildeten Schaltungsteil OA an der Klemme VR anliegende Referenzspannung und ein Widerstand R bestimmen einen Bezugsstrom IB. Die Klemme VR ist mit einem Eingang eines Transistors N31 verbunden, der in Verbindung mit einem Transistor N32 einen Differenzverstärker bildet. Dieser Differenzverstärker wird von einer Stromquelle aus den Transistoren P31, P32, N33 und N34 versorgt. Der durch die Transistoren P31 und P32 definierte Strom wird dabei durch den Stromspiegel aus N33 und N34 in den Differenzverstärker gespiegelt. Im Lastkreis der Differenzverstärkertransistoren N31 und N32 sind Transistoren P33 und P34 angeordnet, die ebenfalls als Stromspiegel geschaltet sind. Der Verbindungspunkt der Ausgangskreise der Transistoren N32 und P34 bildet den Ausgang VO des Operationsverstärkers OA.A reference voltage and a resistor R applied to the VR terminal in a circuit part OA designed as an operational amplifier determine a reference current IB. The terminal VR is connected to an input of a transistor N31, which forms a differential amplifier in conjunction with a transistor N32. This differential amplifier is supplied by a current source from the transistors P31, P32, N33 and N34. The current defined by transistors P31 and P32 is mirrored in the differential amplifier by the current mirror from N33 and N34. Transistors P33 and P34 are arranged in the load circuit of differential amplifier transistors N31 and N32, which are also connected as current mirrors. The connection point of the output circuits of the transistors N32 and P34 forms the output VO of the operational amplifier OA.
Der Ausgang VO steuert eine Mehrzahl parallel geschalteter Transistoren, die im Ausführungssbeispiel durch die Transistoren N1 bis N3 dargestellt sind. Ein gemeinsamer Ausgangsanschluß jeder der Transistoren ist mit einem Anschluß des Widersstands R verbunden, dessen anderer Anschluß auf Bezugspotential GND liegt. Der Verbindungspunkt der Transistoren N1 bis N3 mit dem Widerstand R ist andererseits mit dem Steuereingang des Transistors N32 verbunden und bildet den Rückkoppelungseingang VF des Operationsverstärkers OA. In Betrieb arbeitet der Regelkreis so, daß das Potential VF am Steuereingang des Transistors N32 dem Potential an der Klemme VR entspricht, d. h., daß am Widerstand R die Referenzspannung anliegt. Referenzspannung und Widerstand R bestimmen präzise den Bezugsstrom IB.The output VO controls a plurality of transistors connected in parallel, which are represented in the exemplary embodiment by the transistors N1 to N3. A common output terminal of each of the transistors is connected to a terminal of the resistor R, the other terminal of which is at reference potential GND. The connection point of the transistors N1 to N3 with the resistor R, on the other hand, is connected to the control input of the transistor N32 and forms the feedback input VF of the operational amplifier OA. In operation, the control loop works so that the potential VF at Control input of transistor N32 corresponds to the potential at terminal VR, ie that the reference voltage is present at resistor R. Reference voltage and resistance R precisely determine the reference current IB.
Der Bezugsstrom IB wird mit Hilfe der Mehrzahl parallel liegender Transistoren, im Ausführungsbeispiel mit Hilfe der Transistoren N1 bis N3 in drei Referenzströme I1 bis I3 geteilt. Die Referenzströme I1 bis I3 dienen dann ihrerseits zur Versorgung verteilter Schaltungsanordnungen B1 bis B3, von denen aus Gründen der Übersichtigkeit lediglich die Schaltungsanordnung B1 detailliert dargestellt sind. Es ist selbstverständlich, daß den Schaltungsanordnungen B1 bis B3 weitere Schaltungsteile, z. B. SZ, VC2 bzw. VC3, die ihrerseits ebenfalls verteilt sein dürfen, nachgeschaltet sein können. Man kann deshalb auch den jeweiligen Schaltungsteil B1, B2 oder B 3 zusammen mit dem jeweils nachgeschalteten Schaltungsteil SZ, VC2 oder VC3 als jeweilige verteilte Schaltungsanordnung ansehen.The reference current IB is divided into three reference currents I1 to I3 using the plurality of transistors lying in parallel, in the exemplary embodiment using the transistors N1 to N3. The reference currents I1 to I3 then in turn serve to supply distributed circuit arrangements B1 to B3, of which only the circuit arrangement B1 is shown in detail for reasons of clarity. It goes without saying that the circuit arrangements B1 to B3 further circuit parts, for. B. SZ, VC2 or VC3, which in turn may also be distributed, can be connected downstream. It is therefore also possible to view the respective circuit part B1, B2 or B 3 together with the circuit part SZ, VC2 or VC3 connected downstream as a respective distributed circuit arrangement.
Die drei Transistoren N1 bis N3 sind räumlich beieinander, vorzugsweise eng beieinander angeordnet, so daß für die Referenzströme I1 bis I3 die Anpassungseigenschaften in einem lokal eng begrenzten Gebiet ausschlaggebend sind. Eventuelle Störeinflusse wirken sich auf jeden der Transistoren in gleicher Weise aus. Die auf diese Weise gut definierten Referenzströme werden zu den verteilten Schaltungsanordnungen, z. B. drei Digital-Analog-Umsetzern geleitet. Insbesondere bei gleichen Strukturen, z. B. einem Dreifach-Digital-Analog-Umsetzer können mit gleich ausgelegten Transistoren N1 bis N3 aus dem zentralen Bezugsstrom IB drei gut definierte und angepaßte Referenzströme I1 bis I3 erzeugt werden, die einen optimalen Gleichlauf der verteilten Schaltungsanordnungen gewährleisten. Weiterhin wird mit einer derartigen Referenzstromerzeugung sichergestellt, daß Störungen auf einer Leitung, d. h. Störungen bezuglich einer der verteilten Schaltungsanordnungen praktisch nicht auf die anderen verteilten Schaltungsanordnungen überkoppeln können.The three transistors N1 to N3 are arranged spatially close to one another, preferably close together, so that the adaptation properties in a locally narrowly limited area are decisive for the reference currents I1 to I3. Any interferences have the same effect on each of the transistors. The well-defined reference currents in this way become the distributed circuit arrangements, e.g. B. three digital-to-analog converters. Especially with the same structures, e.g. B. a triple digital-to-analog converter can be generated with the same transistors N1 to N3 from the central reference current IB three well-defined and adapted reference currents I1 to I3, which ensure optimal synchronization of the distributed circuit arrangements. Furthermore, such a reference current generation ensures that faults on one line, ie faults with respect to one of the distributed ones Circuitry can practically not couple to the other distributed circuitry.
Eine weitere Verbesserung bei der Erzeugung der Referenzströme I1 bis I3 sieht vor, daß vom Ausgang VO des Operationsverstärkers OA, der die Steueranschlüsse der die Referenzströme erzeugenden Transistoren N1 bis N3 steuert, ein als Kapazität geschalteter Transistor TC nach Bezugspotential geschaltet ist. TC übt eine Glattungsfunktion aus.A further improvement in the generation of the reference currents I1 to I3 provides that a transistor TC connected as a capacitance is switched to the reference potential from the output VO of the operational amplifier OA, which controls the control connections of the transistors N1 to N3 generating the reference currents. TC has a smoothing function.
Jeder einzelne Referenzstrom I1 bis I3 wird in der durch ihn versorgten verteilten Schaltungsanordnung lokal einer Stromquellenanordnung zugeführt, wie sie beispielsweise in dem Block B1 dargestellt ist, und steuert diese. Die Blöcke B2 und B3 sind in gleicher Weise wie B1 aufgebaut.Each individual reference current I1 to I3 is supplied locally to a current source arrangement in the distributed circuit arrangement supplied by it, as is illustrated, for example, in block B1, and controls it. Blocks B2 and B3 are constructed in the same way as B1.
Die lokal in der jeweiligen verteilten Schaltungsanordnung realisierte Stromquelle wird im Ausführungsbeispiel anhand des Blockes B1 beschrieben. Die Stromquelle besteht im wesentlichen aus den Transistoren P11 und P12, die mit ihren Ausgangskreisen in Reihe geschaltet sind und eine Kaskodestufe bilden. Ein Anschluß des Transistors P11 wird von der Klemme VCC versorgt. Der das Potential VB führende Anschluß des Transistors N1 ist mit dem Steuereingang des Transistors P11 und mit einem Ausgangsanschluß des Transistors P12 verbunden. P11 ist ein p-Kanal-Transistor, der vergleichsweise groß ausgelegt ist. Der Transistor P12 hat im wesentlichen die Aufgabe, den Verbindungspunkt des Transistors P11 mit dem Transistor P12 vom Steuereingang des Transistors P11 bzw. dem damit verbundenen Ausgangsanschluß des Transistors P12 weitgehend zu entkoppeln und die statische Kennlinie der Stromquelle durch Vergrößerung des differentiellen Ausgangswiderstands zu verbessern. Damit werden Störeinflüsse auf den Steueranschluß des Transistors P11 und damit auf den Referenzstrom I1 verringert und die Gateanschlüsse der Transistoren P13 und P23 auf jeweils gleiches Potential gelegt. Fur die Entkopplung ist eine Regelschleife vorgesehen, die im wesentlichen aus den Transistoren P12 und P13 besteht. Dazu ist der an VCC angeschlossene Transistor P3 mit seinem Steueranschluß am Verbindungspunkt der Transistoren P11 und P12 angeschlossen, während der Steueranschluß des Transistors P12 am Ausgang des Transistors P13 angeschlossen ist. P13 wird von der aus den Transistoren P14 und N11 sowie N12 gebildeten Stromquelle versorgt. Dazu wird P14 vom Potential VB, d. h. dem Ausgangsanschluß des Transistors N1 gesteuert. Der von VCC durch P14 fließende Strom wird mit Hilfe der Transistoren N12 und N11 in den Kreis von P13 gespiegelt.The current source implemented locally in the respective distributed circuit arrangement is described in the exemplary embodiment with reference to block B1. The current source consists essentially of transistors P11 and P12, which are connected in series with their output circuits and form a cascode stage. One terminal of transistor P11 is supplied by terminal VCC. The terminal of transistor N1 carrying the potential VB is connected to the control input of transistor P11 and to an output terminal of transistor P12. P11 is a p-channel transistor that is designed to be comparatively large. The transistor P12 essentially has the task of largely decoupling the connection point of the transistor P11 to the transistor P12 from the control input of the transistor P11 or the associated output terminal of the transistor P12 and to improve the static characteristic of the current source by increasing the differential output resistance. This reduces interference on the control connection of the transistor P11 and thus on the reference current I1, and the gate connections of the transistors P13 and P23 are set to the same potential. There is a control loop for the decoupling provided, which consists essentially of the transistors P12 and P13. For this purpose, the transistor P3 connected to VCC has its control connection connected to the connection point of transistors P11 and P12, while the control connection of transistor P12 is connected to the output of transistor P13. P13 is supplied by the current source formed from transistors P14 and N11 and N12. For this purpose, P14 is controlled by the potential VB, ie the output terminal of the transistor N1. The current flowing from VCC through P14 is mirrored into the circuit of P13 using transistors N12 and N11.
Dem Block B1 nachgeschaltet ist eine Schaltungsanordnung SZ, die beispielsweise eine Stromzelle für einen Digital-Analog-Umsetzer bildet. Die Stromquelle ist im Ausführungsbeispiel vorteilhaft ähnlich wie der Kreis B1 aufgebaut. Dazu entsprechen die Transistoren P21 bis P23 den Transistoren P11 bis P13. Die den Transistor P23 versorgende Stromquelle IQ ist z. B. entsprechend wie die Transistoren P14, N11 und N12 ausgebildet. Anders als der Transistor P12 ist der eine Ausgangsanschluß des Transistors P22 mit dem gemeinsamen Verbindungspunkt der Ausgangskreise zweier Schaltertransistoren S1 und S2 verbunden. S1 und S2 werden von antivalenten bzw. komplementären Signalen S und SQ gesteuert. Entsprechend führen die Ausgangsanschlüsse O und OQ der Schaltertransistoren S1 und S2 abwechselnd den durch P21 und P22 fließenden Strom. Durch die in gleicher Weise wie beim Block B1 mit Hilfe des Regeltransistors P23 vorgenommene Entkopplung des Verbindungspunktes der Transistoren P21 und P22 vom Verbindungspunkt des Transistors P22 mit den Transistoren S1 und S2 können sich transiente Schaltvorgänge der Schaltertransistoren S1 und S2 höchstens in geringem Maße auf die Ansteuerung von P21 und damit auf den Referenzstrom I1 auswirken.Downstream of block B1 is a circuit arrangement SZ, which for example forms a current cell for a digital-to-analog converter. In the exemplary embodiment, the current source is advantageously constructed similarly to the circuit B1. For this purpose, the transistors P21 to P23 correspond to the transistors P11 to P13. The current source IQ supplying the transistor P23 is e.g. B. designed corresponding to the transistors P14, N11 and N12. Unlike the transistor P12, the one output terminal of the transistor P22 is connected to the common connection point of the output circuits of two switch transistors S1 and S2. S1 and S2 are controlled by antivalent or complementary signals S and SQ. Accordingly, the output terminals O and OQ of the switch transistors S1 and S2 alternately carry the current flowing through P21 and P22. By decoupling the connection point of the transistors P21 and P22 from the connection point of the transistor P22 with the transistors S1 and S2 in the same way as in block B1 using the control transistor P23, transient switching operations of the switch transistors S1 and S2 can at most only affect the control to a small extent of P21 and thus affect the reference current I1.
Funktionell wird also der Referenzstrom I1 über den Transistor P12 in den Transistor P11 eingespeist, der mit P21 einen Stromspiegel bildet.Durch die vorzugsweise gleiche Struktur des Blocks B1 und der in Figur 1 dargestellten nachgeschalteten Stromzelle SZ, insbesondere die darin ausgeführte Regelschleife wird erreicht, daß die Drainpotentiale der Transistoren P11 und P21 weitgehend gleich sind. Somit wird ein optimaler Gleichlauf dieser beiden Schaltungsteile erzielt. Es ist selbstverständlich, daß dem Block B1 weitere Stromzellen in gleicher Weise nachgeschaltet werden können, die beispielsweise für einen Digital-Analog-Umsetzer vorgesehen sind. Dies ist schematisch anhand der den Blöcken B2 und B3 nachgeschalteten Blöcke VC2 und VC3 dargestellt, die dementsprechend dann jeweils einen Digital-Analog-Umsetzer repräsentieren.Functionally, the reference current I1 is fed via transistor P12 into transistor P11, which forms a current mirror with P21. The structure of block B1 and that shown in FIG. 1 are preferably the same downstream current cell SZ, in particular the control loop executed therein, is achieved that the drain potentials of the transistors P11 and P21 are largely the same. An optimal synchronization of these two circuit parts is thus achieved. It goes without saying that block B1 can be followed by further current cells in the same way, which are provided, for example, for a digital-to-analog converter. This is shown schematically on the basis of blocks VC2 and VC3, which are connected downstream of blocks B2 and B3 and which accordingly each represent a digital-to-analog converter.
Claims (8)
dadurch gekennzeichnet,
daß der Bezugsstrom (IB) mit Hilfe einer Mehrzahl parallel liegender Transistoren (N1 bis N3), die räumlich beieinander angeordnet sind, in eine der Mehrzahl entsprechende Zahl Referenzströme (I1 bis I3) aufgeteilt wird.Current source arrangement for generating multiple reference currents for distributed circuit arrangements with a current source that generates a reference current
characterized,
that the reference current (IB) is divided into a number of reference currents (I1 to I3) corresponding to the plurality by means of a plurality of transistors (N1 to N3) arranged in parallel, which are arranged spatially next to one another.
dadurch gekennzeichnet,
daß die Transistoren (N1 bis N3) vom Ausgang (VO) eines Operationsverstärkers (OA) gesteuert werden, dessen einer Eingang an einem Referenzpotential (VR) liegt und dessen zweiter Eingang (VF) an einem gemeinsamen Verbindungspunkt der Transistoren und eines Widerstandselements (R) liegt.Arrangement according to claim 1,
characterized,
that the transistors (N1 to N3) are controlled by the output (VO) of an operational amplifier (OA), one input of which is connected to a reference potential (VR) and the second input (VF) of which is at a common connection point of the transistors and a resistance element (R) lies.
dadurch gekennzeichnet,
daß die Transistoren (N1 bis N3) gleich ausgebildet sind.Arrangement according to claim 1 or 2,
characterized,
that the transistors (N1 to N3) are identical.
dadurch gekennzeichnet,
daß parallel zu den Transistoren (N1 bis N3) eine Kapazität (TC) geschaltet ist.Arrangement according to one of the preceding claims,
characterized,
that a capacitor (TC) is connected in parallel with the transistors (N1 to N3).
dadurch gekennzeichnet,
daß jeder der Transistoren (N1 bis N3) ausgangsseitig mit einer der verteilten Schaltungsanordnungen verbunden ist, welche jeweils eine von dem zugeordneten Transistor gesteuerte Stromquellenanordnung (P11, P12; P21, P22) aufweist.Arrangement according to one of the preceding claims,
characterized,
that each of the transistors (N1 to N3) is connected on the output side to one of the distributed circuit arrangements, each of which has a current source arrangement (P11, P12; P21, P22) controlled by the associated transistor.
dadurch gekennzeichnet,
daß die Stromquellen als Kaskodestufen ausgebildet sind und daß der Ausgang jedes der Transistoren (N1 bis N3) einen ersten Transistor (P11) der Kaskodestufe steuert und mit einem Ausgangsanschluß des zweiten Transistors (P12) verbunden ist, der mit einem Regeltransistor (P13) zur Regelung des Potentials an dem Verbindungspunkt des ersten und des zweiten Transistors (P11, P12) verbunden ist.Arrangement according to claim 5,
characterized,
that the current sources are designed as cascode stages and that the output of each of the transistors (N1 to N3) controls a first transistor (P11) of the cascode stage and is connected to an output terminal of the second transistor (P12) which is connected to a control transistor (P13) for regulation of the potential at the connection point of the first and the second transistor (P11, P12).
dadurch gekennzeichnet,
daß jeder der Referenzströme (I1 bis I3) in die jeweils zugeordnete verteilte Schaltungsanordnung (B1, SZ; B2, VC2; B3, VC3) gespiegelt wird.Arrangement according to one of the preceding claims,
characterized,
that each of the reference currents (I1 to I3) is mirrored in the respectively assigned distributed circuit arrangement (B1, SZ; B2, VC2; B3, VC3).
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE4315296 | 1993-05-07 | ||
| DE4315296A DE4315296C2 (en) | 1993-05-07 | 1993-05-07 | Current source arrangement for generating multiple reference currents |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| EP0623866A2 true EP0623866A2 (en) | 1994-11-09 |
| EP0623866A3 EP0623866A3 (en) | 1995-01-11 |
| EP0623866B1 EP0623866B1 (en) | 2000-03-01 |
Family
ID=6487526
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP94106982A Expired - Lifetime EP0623866B1 (en) | 1993-05-07 | 1994-05-04 | Current source arrangement to produce multiple reference currents |
Country Status (2)
| Country | Link |
|---|---|
| EP (1) | EP0623866B1 (en) |
| DE (2) | DE4315296C2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19746950C2 (en) * | 1997-01-31 | 2003-11-06 | Lg Semicon Co Ltd | Digital-to-analog converter |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4587477A (en) * | 1984-05-18 | 1986-05-06 | Hewlett-Packard Company | Binary scaled current array source for digital to analog converters |
| US4596948A (en) * | 1984-10-17 | 1986-06-24 | Irvine Sensors Corporation | Constant current source for integrated circuits |
| EP0231872A2 (en) * | 1986-02-03 | 1987-08-12 | Siemens Aktiengesellschaft | Switching current source |
| EP0424742A2 (en) * | 1989-10-27 | 1991-05-02 | Motorola, Inc. | Floating output digital to analog converter |
| US5063343A (en) * | 1990-04-05 | 1991-11-05 | Gazelle Microcircuits, Inc. | Current pump structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0169388B1 (en) * | 1984-07-16 | 1988-09-28 | Siemens Aktiengesellschaft | Integrated constant-current source |
-
1993
- 1993-05-07 DE DE4315296A patent/DE4315296C2/en not_active Expired - Fee Related
-
1994
- 1994-05-04 DE DE59409161T patent/DE59409161D1/en not_active Expired - Lifetime
- 1994-05-04 EP EP94106982A patent/EP0623866B1/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4587477A (en) * | 1984-05-18 | 1986-05-06 | Hewlett-Packard Company | Binary scaled current array source for digital to analog converters |
| US4596948A (en) * | 1984-10-17 | 1986-06-24 | Irvine Sensors Corporation | Constant current source for integrated circuits |
| EP0231872A2 (en) * | 1986-02-03 | 1987-08-12 | Siemens Aktiengesellschaft | Switching current source |
| EP0424742A2 (en) * | 1989-10-27 | 1991-05-02 | Motorola, Inc. | Floating output digital to analog converter |
| US5063343A (en) * | 1990-04-05 | 1991-11-05 | Gazelle Microcircuits, Inc. | Current pump structure |
Non-Patent Citations (1)
| Title |
|---|
| IEEE JOURNAL OF SOLID-STATE CIRCUITS, Bd.22, Nr.6, Dezember 1987, NEW YORK US Seiten 971 - 981 LARSON ET AL. 'GaAs Switched Capacitor Circuits for High-Speed Signal Processing' * |
Also Published As
| Publication number | Publication date |
|---|---|
| DE4315296C2 (en) | 2000-03-02 |
| EP0623866B1 (en) | 2000-03-01 |
| DE4315296A1 (en) | 1994-11-10 |
| EP0623866A3 (en) | 1995-01-11 |
| DE59409161D1 (en) | 2000-04-06 |
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