EP0619051A1 - Circuit for generating variable-frequency pulses from periodic pulses - Google Patents
Circuit for generating variable-frequency pulses from periodic pulsesInfo
- Publication number
- EP0619051A1 EP0619051A1 EP93902357A EP93902357A EP0619051A1 EP 0619051 A1 EP0619051 A1 EP 0619051A1 EP 93902357 A EP93902357 A EP 93902357A EP 93902357 A EP93902357 A EP 93902357A EP 0619051 A1 EP0619051 A1 EP 0619051A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- pulses
- output
- input
- content
- down counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 230000000737 periodic effect Effects 0.000 title claims abstract description 11
- 230000001133 acceleration Effects 0.000 claims abstract description 10
- 239000013256 coordination polymer Substances 0.000 claims description 35
- 230000003247 decreasing effect Effects 0.000 claims description 10
- 230000000295 complement effect Effects 0.000 claims description 8
- 239000010453 quartz Substances 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 101100493897 Arabidopsis thaliana BGLU30 gene Proteins 0.000 claims 1
- 101100171060 Caenorhabditis elegans div-1 gene Proteins 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 239000008186 active pharmaceutical agent Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000002123 temporal effect Effects 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/68—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using pulse rate multipliers or dividers pulse rate multipliers or dividers per se
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
Definitions
- the present invention relates to a variable frequency pulse generation circuit from periodic pulses.
- This circuit can be used in particular to start, turn and then brake a stepper motor with very high precision and stability.
- This motor can be rotating or linear.
- the engine can be used in mechanical image still image analyzers, for example.
- a read head scans an image.
- the movement of the head should be as uniform as possible. This movement generally includes, from a standstill, an acceleration phase, a constant speed phase and a braking phase.
- Known devices for controlling a stepping motor generally use circuits with a voltage-controlled oscillator (VCO in Anglo-Saxon literature). These circuits are mixed digital and analog. Such a flow is shown in FIG. 1. It uses an up-down counter CDE which receives on a counting input EP periodic input pulses. The pulses can be supplied by any suitable generator. This CDE up-down counter has Q content which is sent to a digital-to-analog DAC converter. The digital-analog converter DAC supplies an input of a voltage-controlled VCO oscillator. The VCO oscillator has an S output which provides output pulses, part of these pulses is variable frequency. A feedback loop is provided between the output S of the VCO oscillator and an input EM of the CDE up-down counter.
- VCO voltage-controlled oscillator
- the frequency of the VCO oscillator varies when you start sending pulses to the CDE up-down counter.
- the frequency of the output pulses increases until the digital-analog converter DAC saturates.
- the deceleration phase begins when the content Q of the up-down counter CDE decreases and the digital-analog converter DAC no longer saturates.
- the pulses supplied at the output are increasingly spaced. The temporal stability and precision of the frequency of the output pulses is not guaranteed.
- the instability is due to the VCO oscillator itself which cannot have sufficient stability and to the analog components (generally resistors, capacitors) used in the circuit.
- this circuit uses a feedback loop which has its own Instability.
- This circuit is suitable for controlling the movement of an object from one point to another but is incapable of ensuring this movement with good linearity and good temporal precision.
- the present invention aims to remedy these drawbacks. It proposes a circuit for generating output pulses, at least a part of which at variable frequency, from periodic input pulses.
- This circuit without feedback loop makes it possible to control a stepping motor extremely precisely.
- This circuit works with digital circuits.
- This circuit includes: a frequency divider having a content, receiving on an input the input pulses which increment its content, and supplying on an output an output pulse as soon as its content reaches a maximum content, the said divider having a division ratio corresponding to the number of input pulses received between two output pulses,
- Means for modifying the division ratio of the divider so that output pulses are generated at variable frequency Preferably, a quartz device is used to generate the input pulses in order to obtain the desired stability.
- the means for modifying the division ratio may include a first up-down counter having a content modified by the output pulses, the content of the divider taking the value of the content of the first up-down counter as soon as said divider receives an input pulse , after generating an output pulse.
- the circuit may include means for incrementing by one the content of the first up-down counter from first auxiliary pulses as a function of the output pulses, so that output pulses are generated at increasing frequency and means for decrementing by one the content of the first up-down counter from second auxiliary pulses as a function of the output pulses, so that output pulses are generated at decreasing frequencies.
- the circuit according to the invention will advantageously generate as many output pulses at increasing frequency as at decreasing frequency.
- the circuit according to the invention can generate output pulses at constant frequency, this frequency being able to be glued from input pulses.
- the circuit according to the invention can be used to control a stepping motor.
- the invention will be better understood from the following description given with reference to the appended figures which represent: FIG. 1, already described, a circuit for generating pulses according to the prior art;
- Figure 3 a diagram as a function of time of the states of certain elements of the circuit of Figure 2;
- This circuit receives on an input terminal E periodic pulses of frequency FI. It generates pulses on an output terminal S, at least part of which is of variable frequency.
- circuit represented in FIG. 2 begins by generating pulses with increasing frequency then generates pulses with constant frequency, then pulses with decreasing frequency.
- the engine which will be controlled will be in acceleration mode, then in nominal mode, then in braking mode. This is just a non-limiting example.
- the input pulses preferably come from a QA quartz device in order to benefit from the highest possible accuracy and stability. We assume that we are working in positive logic, that is to say that the outputs of the circuits used are at the high level when they are active.
- a start order in the form of an Impulse, is sent from a terminal G to an input SI of a flip-flop Bl of type R, S.
- the flip-flop B also has an RI input.
- the flip-flops of type R, S have two inputs, one R and the other S and two outputs Q and Q * (Q represents the logical complement of Q).
- Input S aims to activate output Q and input R aims to deactivate output Q.
- the output Q goes to the high level.
- I when the input R receives a signal at the high level, the input S being at the low level, the output Q goes to the low level.
- the output Q1 of the flip-flop B1 is active as soon as the start order has been sent.
- a pulse counter C1 receives on a clock input H, the periodic input pulses as soon as the output Q1 is active.
- a gate PI preferably of the AND type receives as input, on the one hand the input pulses and on the other hand the output Q1 of the flip-flop Bl.
- the gate PI is open and supplies the input pulses as output as the output Q1 of the flip-flop B1 is active.
- the output of the gate PI is sent to the clock input H of the counter Cl.
- the counter C1 is intended to count N input pulses, the number N being the number of output pulses that the circuit according to the invention will generate. N is an integer greater than one.
- This number is representative of the amplitude of the movement that one wants to make. In the example described, it is assumed that 11 pulses at the circuit output are desired.
- the counter Cl is loaded by a loading input C1P at a value - N so that the counter Cl generates on a RC output a pulse as soon as N pulses have been received by the input H.
- the RC output of the counter Cl is connected to the input RI of the flip-flop Bl.
- a frequency divider CP receives the input pulses on an HP input as soon as the start order has been given.
- the CP divider is a programmable divider.
- the starting order also arrives at an input S2 of a flip-flop B2 of type D.
- Flip-flop B2 has an output Q2 and another input D2 connected in permanence at low level.
- the B2 flip-flop is a synchronous flip-flop, it also has a clock input H2. After the start command, the Q2 output is active until the H2 input goes high.
- the output Q2 is connected to an input of a gate P7 preferably of type ET. Gate P7 receives the periodic input pulses on another input.
- door P7 is open and supplies the input pulses to the input HP of the divider CP.
- the divider CP has a content J and a division report. Before the starting order, the content J is indifferent.
- the divider CP counts the input pulses until its content J is equal to a maximum content Jmax.
- the divider CP then generates an output pulse on an output RP.
- the output RP is also the output S of the circuit according to the invention.
- the division ratio is equal to the number of input pulses received between two output pulses. This division ratio is variable so that output pulses can be generated at variable frequency. Before the starting order, the division ratio is arbitrary.
- the divider has a loading input LP connected to the output RP and a data input DP. As soon as an output pulse has been generated on the RP output, and it has been followed by an input pulse on the HP input, a loading order is sent by the LP input and the content J of the CP divider takes a value present on the DP input.
- the DP input is connected to the QD output of a CUD up-down counter.
- the CUD up-down counter has K content at all times.
- the QD output permanently delivers the content K of the CUD up-down counter to the DP input.
- the QD output can include several output bits if the up-down counter is designed to count large numbers.
- the content J of the divider CP is incremented with the input pulses until the said content J is equal to the maximum content Jmax.
- An output pulse is generated on the RP output as soon as the HP input has received a new input pulse.
- the pulses generated by the output RP will be used to modify the content K of the up-down counter CUD.
- the division ratio of the divider CP is variable since K will be modified.
- the CUD up-down counter includes a CI counting input and a CM counting down input. It has a loading input L to give it initial content before the start order.
- the content K of the CUD up-down counter will be incremented by one at each output pulse as long as the content of the CUD up-down counter has not reached a maximum value Kmax for this up-down counter.
- the division ratio of the CP divider will decrease and the output pulses will be closer and closer. The frequency of the output pulses increases more and more.
- a decoding circuit P6 receives the content K of the up-down counter as an input.
- This circuit P6 can be an AND type gate. It has an output which feeds an input R3 of a rocker B3 of type RS.
- the input R3 aims to deactivate an output Q3 of the flip-flop B3 when the content K of the up-down counter CUD is equal to the maximum content Kmax.
- the B3 flip-flop has an S3 input aimed at activating the output
- a gate P4 preferably of the AND type, combines as input the output Q3 of the flip-flop B3 and pulses which are a function of the output pulses.
- I ⁇ door P4 is open as long as the output Q3 is active.
- the output pulses arrive at a counting input CI of the up-down counter CUD and increment its content K.
- the output Q3 of the flip-flop B3 is inactive, that is to say when the content K of the CUD up-down counter is maximum and equal to Kmax, door P4 closes and the CUD up-down counter stops being incremented. Its content K remains constant.
- the divider CP then has a division ratio which remains constant.
- the frequency of the pulses generated at output S is constant, it is the end of the acceleration. The engine reaches its rated speed after accelerating.
- the division ratio of the divider CP is equal to one when it is constant.
- the maximum content Jmax of the divider CP is then equal to the maximum content Kmax of the up-down counter CUD.
- An output pulse will be generated on the output RP as soon as an input pulse will appear on the input HP of the divider CP.
- the output pulses will be periodic and have the frequency IF of the input pulses.
- the up-down counter If one wishes to generate M pulses with increasing frequency (M is an integer greater than one), it suffices to load the up-down counter with the complement of M with respect to the maximum content Kmax increased by one.
- the loading command arriving on a loading input L of the up-down counter CUD is used.
- the CUD up-down counter counts in hexadecimal. Its maximum content is F. If 4 increasing frequency output pulses are desired, the CUD up-down counter is loaded at the hexadecimal value C.
- each output pulse was used to increment the content of the CUD up-down counter by one.
- the output RP of the divider CP is directly connected to the input of door P4. It can be envisaged that several output pulses are necessary to increment the content of the CUD up-down counter by one in order to reduce the frequency of the output pulses. It is possible to insert an auxiliary divider DIV1 having a division ratio x (x integer greater than zero) between the output RP and the input of the gate P4. Gate P4 receives first auxiliary pulses which are a function of the output pulses. Figure 4 shows this variant.
- the output RP is connected to an input HV1 of the divider DIV1
- the input of the gate P4 is connected to an output RV1 of the divider DIV1.
- the engine may have to be decelerated.
- the circuit according to the invention will then generate M 'decreasing variable frequency output pulses.
- M ' is an integer greater than one.
- the means for decrementing the content K of the down-counter CUD will be described. They include a B4 type RS flip-flop receiving on an S4 input, aiming to activate an output Q4 of the B4 flip-flop, the order of start of the decrementation.
- the flip-flop B4 has an input R4, aimed at making the output Q4 inactive.
- the input R4 receives an order indicating that the N output pulses have been generated. It's the end of deceleration.
- a P5 door preferably of ET type combines as input the output Q4 of the flip-flop B4 and pulses as a function of the output pulses.
- a second auxiliary divider DIV2 can be inserted between the output RP and the input of the door P5.
- the output RP is connected to an input HV2 of the divider DIV2 and the input of the gate P5 is connected to an output RV2 of the divider DIV2.
- the input of gate P5 receives second auxiliary pulses which are a function of the output pulses.
- the auxiliary divider DIV2 has a division ratio of x '(x' integer greater than zero).
- the two auxiliary divisors DIV1 and DIV2 are merged and that x is equal to x '. It is also conceivable that the division ratios are equal to one and the auxiliary dividers can be removed.
- another ACC up-down counter receives on an AP counting input the N input pulses.
- This AP input is connected to the output of the PI gate.
- This up-down counter ⁇ CC has a content A equal to zero before the start order content A is present on a QC output.
- the up-down counter ACC includes a loading input LA connected to the reset reset command. It receives on an AM down count input the output pulses coming from the output RP of the divider CP.
- the ACC-down counter increments by one in each receiving N input pulses and simultaneously decremented by a receiving an output pulse, the time not that the N input pulses have been received, the content A of the up-down counter ACC is only decremented.
- the content A then represents the number of output pulses that remain to be generated. As long as the counting input AP is incremented, the content A does not represent the number of output pulses to be generated.
- a decoding circuit P2 preferably a NAND type gate, is provided for decoding the moment when the N output pulses have been generated. It combines as input, on the one hand the content A of the up-down counter ACC and on the other hand the logical complement of the output Q3 of the flip-flop B3.
- An inverter I can be inserted between the output Q3 and the circuit P2 or else one can use the output Q3 * which is the logical complement of the output Q3. This is the first variant which is shown in FIG. 2.
- the circuit P2 is connected to the input R4 of the flip-flop B4. When the circuit P2 opens, this indicates that the content A of the up-down counter ACC is zero and that the up-down counter CUD is no longer incremented.
- the output Q4 of the flip-flop B4 is inactive, the door P5 is closed and the up-down counter CUD is no longer decremented. It's the end of deceleration.
- the circuit P2 is also connected to the clock input H2 of the flip-flop B2. When the circuit P2 opens, the output Q2 of the flip-flop B2 becomes inactive, the door P7 closes and the input HP of the divider CP no longer receives input pulses.
- the second up-down counter ACC can also contribute to triggering the order of start of the decrementation in association with a decoding circuit P3, preferably an AND type gate.
- the circuit P3 combines as input, on the one hand the content A of the up-down counter ACC, and on the other hand the logical complement of the output Q3 of the flip-flop B3.
- the input S4 of the flip-flop B4 is connected to the output of the circuit P3. I -when the P3 circuit is open, it provides an order to start decrementing. This order occurs when the content A is equal to the number M 'of output pulses to be generated at decreasing frequency and when the first up-down counter CUD is no longer incremented.
- the output Q4 of the flip-flop B4 becomes active, the gate P5 opens and the output pulses decrement the content K of the up-down counter CUD.
- FIG. 3 represents a diagram over time of the states of the elements of the circuit according to the invention.
- the first line represents the constant frequency input pulses FI.
- the starting order is represented with the reference G.
- N 11 output pulses will be generated and the counter Cl will count 11 input pulses.
- the output Q1 of the flip-flop B1 is inactive until the start order has not been given. It becomes active with the start order and remains so until the counter C1 has finished counting the 11 input pulses, then becomes Inactive again.
- the output Q2 of the flip-flop B2 is inactive before the starting order G, it becomes active after the starting order G, the rest until. the content of the ACC up-down counter reaches zero so the 11 output pulses have been generated, then becomes inactive again.
- the output Q3 of flip-flop B3 is active until the content of the up-down counter CUD has reached its maximum value Kmax. F-'lle then becomes inactive. It's the end of the acceleration.
- the output Q4 of flip-flop B4 is inactive until the start of deceleration has taken place. It becomes active until the content A of the ACC up-down counter is empty.
- the content A of the ACC up-down counter, present on the QC output, is incremented from zero by the 11 pulses input and simultaneously decremented by each output pulse.
- the content K of the up-down counter CUD is incremented from the value C to the value F in acceleration mode, remains constant at the value F in nominal mode, then is decremented from the value E to the value A in deceleration mode.
- J max takes the value F.
- the content K of the up-down counter CUD then becomes the content J of the divider CP.
- an output pulse is generated as soon as the content J of the divider CP is maximum and as soon as a new input pulse arrives at the input HP.
- the RP output does indeed generate 11 output pulses including 4 at increasing frequency, 3 at constant frequency and
- the means for triggering the start of the decrementation and the order indicating that the N pulses have been generated include a decounter DEC and a shift register RS with y bits (y is an integer greater than one). It is a register with serial input and parallel outputs.
- the shift register RS has a clock input HS and a data input DS. On the DS input, it receives the number N of output pulses in the form of successive y bits.
- the RS shift register has y outputs RS (1) to RS (y). These y outputs feed y inputs AD (1) to AD (y) of the DEC down-counter.
- the decounter DEC has a reset input LD and another downcount input DM connected to the output RP of the divider CP.
- the DEC decounter has a content P equal to N just after the reset and this content is present on an output QE. There is transfer from the shift register RS to the decounter DEC. The content P of the decounter DEC is decremented by the output pulses and this content P represents at each instant the number of output pulses to be generated.
- the output QE of the decounter DEC is connected to the input of decoding circuits P2 'and P3' supplying respectively the input R4 and the input S4 of the flip-flop B4.
- the output of circuit P2 1 also supplies the clock input H2 of the flip-flop B2.
- the circuit P2 ' provides the order indicating that the N output pulses have been generated when the content P of the decounter DEC is zero.
- the circuit P3 ′ provides the order for the start of the decrementation when the content P of the decounter DEC takes a value equal to M ′.
- FIG. 5 also shows a single auxiliary divider DIV, having a division ratio of x. It receives on an HV input the output pulses. It provides a pulse on an RV output every x Output pulses at the input of gate P4 and gate P5.
- the frequency of the output pulses can be obtained with the desired precision from a QA quartz generating the input pulses.
- the frequency of quartz can be divided. Any suitable quartz synthesis device can be used.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Optimization (AREA)
- Mathematical Analysis (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Nonlinear Science (AREA)
- Control Of Stepping Motors (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
La présente invention concerne un circuit de génération d'impulsions de sortie dont au moins une partie à fréquence variable à partir d'impulsions d'entrée périodiques. Il comporte un diviseur de fréquence (CP) ayant un contenu (J) et recevant sur une entrée (HP) les impulsions d'entrée qui incrémentent son contenu. Le diviseur fournit une impulsion de sortie dès que son contenu a atteint un contenu maximum (Jmax) et a un rapport de division égal au nombre d'impulsions d'entrée reçues entre deux impulsions de sortie. Des moyens (CUD) sont prévus pour modifier le rapport de division de manière à ce que des impulsions de sortie puissent être générées à fréquence variable. Application: commande de l'accélération et de la décélération de moteurs pas à pas.The present invention relates to a circuit for generating output pulses, at least part of which has a variable frequency from periodic input pulses. It comprises a frequency divider (CP) having a content (J) and receiving on an input (HP) the input pulses which increment its content. The divider provides an output pulse as soon as its content has reached a maximum content (Jmax) and has a division ratio equal to the number of input pulses received between two output pulses. Means (CUD) are provided for modifying the division ratio so that output pulses can be generated at variable frequency. Application: Acceleration and deceleration control of stepper motors.
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9116043 | 1991-12-23 | ||
FR9116043A FR2685581A1 (en) | 1991-12-23 | 1991-12-23 | CICRUIT FOR GENERATING VARIABLE FREQUENCY PULSES FROM PERIODIC PULSES. |
PCT/FR1992/001215 WO1993013596A1 (en) | 1991-12-23 | 1992-12-21 | Circuit for generating variable-frequency pulses from periodic pulses |
Publications (1)
Publication Number | Publication Date |
---|---|
EP0619051A1 true EP0619051A1 (en) | 1994-10-12 |
Family
ID=9420414
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP93902357A Withdrawn EP0619051A1 (en) | 1991-12-23 | 1992-12-21 | Circuit for generating variable-frequency pulses from periodic pulses |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0619051A1 (en) |
CA (1) | CA2124119A1 (en) |
FR (1) | FR2685581A1 (en) |
WO (1) | WO1993013596A1 (en) |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2755535C3 (en) * | 1977-12-13 | 1981-06-11 | Siemens AG, 1000 Berlin und 8000 München | Circuit arrangement for controlling a stepping motor and method for operating the circuit arrangement |
US4231104A (en) * | 1978-04-26 | 1980-10-28 | Teradyne, Inc. | Generating timing signals |
FR2512604A1 (en) * | 1981-09-08 | 1983-03-11 | Shinshu Seiki Kk | SPEED CONTROL DEVICE FOR STEP-BY-STEP MOTORS |
NL8104590A (en) * | 1981-10-08 | 1983-05-02 | Oce Nederland Bv | METHOD AND APPARATUS FOR CONTROLLING A STEPPER MOTOR |
JPS60241797A (en) * | 1984-05-14 | 1985-11-30 | Hitachi Ltd | Control circuit of stepping motor |
-
1991
- 1991-12-23 FR FR9116043A patent/FR2685581A1/en active Pending
-
1992
- 1992-12-21 WO PCT/FR1992/001215 patent/WO1993013596A1/en not_active Application Discontinuation
- 1992-12-21 EP EP93902357A patent/EP0619051A1/en not_active Withdrawn
- 1992-12-21 CA CA 2124119 patent/CA2124119A1/en not_active Abandoned
Non-Patent Citations (1)
Title |
---|
See references of WO9313596A1 * |
Also Published As
Publication number | Publication date |
---|---|
CA2124119A1 (en) | 1993-07-08 |
FR2685581A1 (en) | 1993-06-25 |
WO1993013596A1 (en) | 1993-07-08 |
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