Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/50—Control of the SSIS exposure
  • H04N25/53—Control of the integration time
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/70—SSIS architectures; Circuits associated therewith
  • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
  • H04N25/74—Circuitry for scanning or addressing the pixel array

Definitions

• the present invention relates to solid state imaging or image pick-up devices and in particular to such devices provided with electronic exposure control means.
• the present invention provides a solid state image pick-up device comprising a two-dimensional array of sensing cells, each sensing cell having a photodiode and a transistor for reading from and writing to the photodiode, horizontal and vertical scanning means coupled to each cell of the array, wherein said vertical scanning means comprises a plurality of vertical scanning lines, each commonly connected to sensing cells arranged in a horizontal direction, and vertical shift register means having outputs connected to the vertical scanning lines for driving the vertical scanning lines with control pulses so as to cause each line to be successively reset and then sampled after a variable period defining an integration time, characterised in that the vertical shift register means comprises a single vertical shift_ register formed and arranged to be driven with an input so as to drive a group of successive vertical scanning lines during each line period, and there are provided global reset and sample signal driven means connected to each of said lines via a decode cell, each said decode cell being connected to the decode cells of preceding and succeeding lines, said decode cells being formed and arranged so that the leading line of the group
• Fig. 1 is a general schematic plan view of a solid state image pick-up device of the type disclosed in our earlier International Patent Publication No. WO 91/04633
• Fig. 2 is a detail view showing part of the vertical shift register of the device of Fig. 1 with associated decode cells and connections thereto
• Fig. 3 is a schematic representation of the status of the various lines in the device of Figs. 1 and 2 at any given time;
• Fig. 4 is a detail view showing the internal architecture of an individual decode cell; Figs. 5 to 7 showing waveforms for the vertical shift register input, the reset signal, and a comparison of the waveforms for different lines at any given time; and Fig. 8 illustrates a suitable control algorithm for exposure control.
• Fig. 1 shows a solid state image pick-up device 1 comprising a two-dimensional array 2 of sensing cells 3 coupled to horizontal and vertical scanning means 4 and 5, respectively.
• the vertical scanning means comprises a vertical shift register 6 containing a plurality of vertical shift register cells 7 having a common input line ⁇ for receiving input signals f_ and each connected 9 via a respective decode cell 10 to a vertical scanning line 11 connected in turn to a horizontal row 12 of sensing cells 3 (see Fig. 1) .
• Each of the decode cells 10 is also commonly connected 13 to global reset and sampling lines 14 and 15, respectively.
• the vertical shift register input signal f is made up of a block of reset control pulses for enabling resetting of a number of the vertical scanning lines 11 - lines i+n+1 to N and 1 to i leaving lines i+1 to i+n "integrating" i.e. "recording" the light falling on them until they are sampled - see Fig. 3.
• the number of pulses in the block may be varied so that at any given moment any number from just one to all of the lines are reset - corresponding to maximum number of lines "integrating" and hence maximum integration period resulting in maximum exposure and vice versa respectively.
• all the lines 11 receive a reset signal via the global reset line 14. Only those lines 11 receiving control reset signals via the respective vertical shift register cells 7 are however actually reset.
• the sample signal received via the global sampling line 15 is timed ahead of the reset signal received via the global reset line 14 so that the sampled line i is sampled prior to being reset.
• the decode cell 10 is formed and arranged so that whilst all the lines 11 receive a sample signal via the global sampling line 15, only line i, the first line in the block of lines being reset is actually sampled.
• the decode cell comprises a NOR gate 16 and three NAND gates 17, 18, 19.
• the NOR gate 16 monitors the presence of a reset control signal from the respective vertical shift register cell 7 and provides an output X, to the first NAND gate 17 of the decode cell 10 of the next vertical scanning line i+1 and to a second NAND gate of the decode cell of line i.
• the first NAND gate 17 of each decode cell 10 compares the "reset" status of the present line i and the previous line i-1, the leading edge of the block of "reset” lines corresponding to the absence of "reset” status on the present line (at the time of sampling - see below) and presence of "reset” status on the previous line.
• the third NAND gate 19 then uses the output of the second NAND gate 18 to enable sampling only at that line i at the leading edge of the block of "reset” lines. In this way sampling and then resetting of a variable number of lines (corresponding to variable exposure times) can be controlled simply by means of providing blocks of reset control pulses of variable size through the vertical shift register.
• Fig. 4 represents only one way of achieving the desired control of sampling using global sampling and reset inputs and control pulse inputs via the (single) vertical shift register and that various other forms of decode cell may also be used.
• the actual values which should be used to set the exposure times may be readily determined by any suitable means including for example measurement of grey level histograms of previous images and/or measuring the percentages of pixels with values above or below two or more grey scale thresholds, and then comparing these against predetermined criteria.
• Fig. 8 is an automatic exposure control decision diagram.
• the video stream is internally histogrammed by pixel brightness into three bins: very white, average, and very black. Where the image is found to be nearly all black it is judged to be too dark and the exposure increased. Conversely when the image is found to be nearly all white it is judged to be too bright and the exposure reduced.
• the present invention provides a method of automatically electronically controlling exposure in a solid state image pick-up device comprising a two-dimensional array of sensing cells, each sensing cell having a photodiode and a transistor for reading from and writing to the photodiode, horizontal and vertical scanning means coupled to each cell of the array, wherein said vertical scanning means comprises a plurality of vertical scanning lines, each commonly connected to sensing cells arranged in a horizontal direction, and vertical shift register means having outputs connected to the vertical scanning lines for driving the vertical scanning lines with control pulses so as to cause each line to be successively reset and then sampled after a variable period defining an integration time, which method comprises the steps of providing an input to the vertical shift register so as to drive a group of successive vertical scanning lines with control signals for enabling resetting thereof during each line period, providing global sampling and reset signals to all the vertical scanning lines, and processing the signals received at each line so as to enable sampling of a vertical scanning line at the leading edge of said group of successive vertical scanning lines, monitoring the image obtained with said

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• 1991
  • 1991-08-19 GB GB919117837A patent/GB9117837D0/en active Pending
• 1992
  • 1992-08-18 JP JP5504193A patent/JPH06509920A/ja active Pending
  • 1992-08-18 EP EP92917955A patent/EP0599949B1/de not_active Expired - Lifetime
  • 1992-08-18 DE DE69216838T patent/DE69216838T2/de not_active Expired - Fee Related
  • 1992-08-18 WO PCT/GB1992/001522 patent/WO1993004556A1/en active IP Right Grant

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