Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N7/00—Television systems
  • H04N7/08—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division
  • H04N7/087—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division with signal insertion during the vertical blanking interval only
  • H04N7/088—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division with signal insertion during the vertical blanking interval only the inserted signal being digital
  • H04N7/0881—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division with signal insertion during the vertical blanking interval only the inserted signal being digital the signal being time-compressed before its insertion and subsequently decompressed at reception

Definitions

• the invention relates to a video system for the insertion of at least one signal representing information (said associated information signal) into a video signal representative of a moving image in order to obtain a video signal, said signal. enriched video, and / or to provide reverse processing of the enriched video signal obtained in order to extract the video signal and at least one directly exploitable associated information signal.
• the invention applies in particular to insert at least one audio signal (associated information signal) in order to obtain an enriched video signal (designated in this case video signal o / audi o), representative of a moving image in which the sound is synchronized with the image.
• the audio channel (s) are recorded on the video tapes by means of special heads, which requires specific equipment and limits the number of possible audio channels (generally to three).
• the audio channels require specific subcarriers with the appropriate processing, which results in congestion of television frequencies.
• this technique which has the advantage of being able to be implemented in the absence of special audio heads or subcarriers specific audio in case of transmission, is limited to the production of video images which are fixed for a certain duration; moreover, it only allows one audio channel to be inserted into the video signal.
• the present invention proposes to improve existing systems; it relates in particular to a device for inserting into a video signal at least one signal of associated information, which makes it possible to obtain an enriched video signal (for example representative of a moving sound image) without having to modify the materials existing (television, video recorder, camcorder).
• a device for inserting into a video signal at least one signal of associated information, which makes it possible to obtain an enriched video signal (for example representative of a moving sound image) without having to modify the materials existing (television, video recorder, camcorder).
• the insertion device targeted by the invention comprises, in combination, a video input EV, at least one associated information input EA, a separator SEP of synchronization signals s y , s-- connected to the video input, an analog / digital converter CAN receiving the associated information signal, an MDA memory connected to the analog / digital converter CAN, a digital / analog converter DAC connected to the output of said memory MDA, a MIX mixer connected to the EV video input and to the digital / analog converter DAC and adapted to deliver the enriched video signal to an SVA output, a PLL phase-locked loop connected to the SEP splitter to receive the synchronization signals s y , s n and adapted to deliver, on the one hand, ra read addresses to the memory MDA, on the other hand, a control signal s 2 at the read frequency F 2 to the digital / analog converter DAC, a PLC MP connected to the SEP separator to receive the synchronization signals s y , s ⁇ and
• the method of the invention leads to an enriched video signal which has very exactly the same nature as an ordinary video signal and which, therefore, can be processed in the same way as a video signal with the same equipment (recording , transmission, reception). It is possible to insert into the video signal several associated information signals (for example several audio signals representative of different sounds) by assigning in each frame of the video signal a different selected line to each associated information signal.
• several associated information signals for example several audio signals representative of different sounds
• the enriched video signal thus synthesized can be processed to extract the associated information signal (s) and make them directly usable, without modification of existing equipment, with the simple addition of a processing device comprising in combination an EVA enriched video input. , a SEP separator of synchronization signals s y , s h connected to the enriched video input EVA, an analog / digital converter CAN connected to the enriched video input EVA, an MDA memory connected to the analog / digital converter ADC, a digital / analog converter DAC connected to the output of said memory MDA, an associated information output SAE connected to the digital / analog converter DAC, a phase locked loop PLL connected to the separator SEP to receive the synchronization signals s v , s- ⁇ and adapted to deliver, on the one hand, write addresses a 'to the memory MDA, on the other hand, a control signal s' 2 at the write frequency F ' 2 to the digital / analog converter DAC, a PLC MP connected to the SEP separat
• each frame is meant both the insertion in all the frames of the video signal (without exception) and the regular insertion in certain frames only (for example one frame on two, or three).
• the invention extends to a mixed device capable of carrying out either the insertion or the treatment mentioned above according to the operating mode chosen by a function selection.
• This device comprises, in combination, video input means EV, EVA capable of receiving a video signal or an enriched video signal, at least one associated information input EA capable of receiving an associated information signal, a SEP separator synchronization signals s y , s h connected to the video input means EV, EVA, a SELFONC function selector adapted to deliver a signal i / e representative of the insertion / extraction operating mode, an analog / digital ADC converter, a MUX1 multiplexer connected, on the one hand, to the video input means EV, EVA and to the associated information input EA for receive the signals present at these inputs, on the other hand, to the analog / digital converter CAN to deliver towards this one of these signals according to a command signal of cdm mode, an MDA memory connected to the analog / digital converter ADC, a digital /
• FIG. 1 is a block diagram of an insertion device for obtaining a video / audio signal
• FIGS. 2a to 21 are timing diagrams illustrating the insertion process implemented in said device
• FIG. 3 is a block diagram of the microprocessor-based controller used
• FIG. 4 is a block diagram of a device for processing a video / audio signal to deliver usable video signals and audio signals
• FIGS. 5a and 5b are timing diagrams illustrating the operation of the processing device of Figure 4
• FIG. 6 is a block diagram of a device according to the invention, capable of performing the above insertion or processing - evoked according to the chosen mode.
• the device shown by way of example in FIG. 1 is intended to insert audio signals (in the example two in number, but this number is not limited) in a video signal in order to obtain a video signal / audio representative of a moving sound image.
• the video signal a frame of which is illustrated in FIG. 2a and a line in FIG. 2b, is a standard video signal for example with 625 interlaced lines.
• This signal comprises a line synchronization signal s ⁇ composed of tops between each line and a frame synchronization signal s v composed of tops between each frame.
• This video signal is introduced into the device on an EV video input.
• the audio signals are introduced into the device on audio inputs EA (in the example two in number: EA--, EA 2 ).
• EA in the example two in number: EA--, EA 2 .
• An example of an audio signal is shown in Figure 2c.
• the video signal is delivered, on the one hand, to an amplifier of the conventional AMPLIV type in order to calibrate it, on the other hand, to a SEP splitter adapted to extract the line synchronization signals s ⁇ and frame s y therefrom.
• the audio signals are delivered to amplifiers such as AMPLIS provided on each audio channel in order to calibrate them, then to a COM switch which makes it possible, at all times, to select the audio signal to be inserted on command of an MP microprocessor controller described further.
• the selected audio signal is delivered to an analog / digital ADC converter.
• This converter performs a sampling of the audio signal on command of a control signal s ⁇ supplied by the MP automaton.
• This control signal of frequency equal to or multiple of the line synchronization frequency of the video signal, conditions the sampling frequency F -, which is therefore equal to or multiple of said line synchronization frequency.
• the signal s-- has a frequency equal to the line synchronization frequency and the sampling is carried out at this frequency.
• Each sample is digitized in binary by the CAN converter which delivers a binary signal digitized at the frequency F--.
• Figures 2c to 2f illustrate the operation of the converter ( Figure 2d; control signal s.-; Figure 2e: sampling; Figure 2f: binarization).
• the binary signal from the ADC converter is delivered to a dual access memory MDA and is loaded into this memory at a write frequency equal to the frequency F.-.
• the write addresses wa are supplied by the MP controller.
• a digital / analog converter DAC is connected to the output of the MDA memory in order to receive the binary signals read from said MDA memory and convert them into analog signals.
• This reading from the digital memory MDA and the analog conversion which follows are carried out at a reading frequency F at least equal to NF-, where N is the number of lines contained in a frame of the video signal.
• the automaton MP which receives the synchronization signals s and S j - from the separator SEP performs a counting of the tops of the line synchronization signal with resetting to zero at each top of the frame synchronization signal.
• this PLC MP receives from a selector of lines SELIG a signal for selection l s of the line (or fraction of line) in which the insertion is to be carried out.
• the PLC MP compares the line count signal and the selection signal 1_, with a view to delivering an insertion validation signal valmel to the digital memory MDA. This signal triggers the reading of said memory and the conversion of the read values which are delivered in analog form to an input of a MIX mixer.
• the reading frequency F 2 is supplied to the DAC converter by a control signal S generated by a phase locked loop PLL.
• This frequency Fr ⁇ being greater than F •• (at least equal to NF--), a temporal compression of the audio signal is thus carried out and the ligson signal coming from the DAC converter is a compressed audio signal.
• the read addresses ra are supplied to the memory MDA by the phase-locked loop PLL.
• This PLL loop conventionally comprises a voltage controlled oscillator VCO, which delivers the control signal s (frequency F), a divider counter (COMPT) which delivers the read addresses ra and a phase comparator CPH, these means being connected as shown in Figure 1.
• VCO voltage controlled oscillator
• COMPT divider counter
• FIGS. 2g, 2h and 2j respectively illustrate the signal s 2 for read control at the frequency F 2 , the digital / analog conversion carried out at this frequency by the DAC converter, and the ligson compressed audio signal obtained.
• the MIX mixer receives on its other input the calibrated video signal from the AM ' PLIV amplifier; it is controlled by the validation validation signal valmel to be switched at each frame at the instants corresponding to the start and end of the selected line in order to insert into said line the compressed audio signal ligson.
• the video / audio signal from the MIX mixer is available on an SVA output for recording or transmission.
• Figures 2k and 21 illustrate on the same scale (duration of about two frames), on the one hand, the audio signal, on the other hand, the video / audio signal delivered on the SVA output of the device.
• the memory MDA is a dual-access memory, the write and read access of which are connected, on the one hand, to the PLC MP, on the other hand, to the phase locked loop PLL .
• the MP automaton is preferably a microprocessor automaton with a PROM read only memory, a random access memory RAM, a BVF buffer, an adaptation circuit for PIA peripherals and a unit.
• PAL programmed logic as shown in Figure 3. This controller could optionally be a wired controller.
• the device shown by way of example in FIG. 4 is intended to process the video / audio signal obtained in the device in FIG. 1, to deliver a video signal and an audio signal which can be used by conventional equipment in order to generate a moving image and the corresponding sound in synchronism with said image.
• the same references have been used as those of FIG. 1 for the units having the same structures and the same functions.
• the video / audio signal is fed into the processing device through an EVA video / audio input.
• This signal is delivered, on the one hand, to an SVE video output, on the other hand, to a SEP separator of the signals of synchronization s y , s h , finally to an analog / digital ADC converter.
• SVE video output on the other hand, to a SEP separator of the signals of synchronization s y , s h , finally to an analog / digital ADC converter.
• the ADC converter samples and converts the video / audio signal to digital at a frequency F ' 2 supplied by a control signal s' 2 .
• the digital signal from the ADC converter is stored in real time in a digital memory MDA at the times provided by an extraction validation signal valext which is delivered by a PLC MP. This signal valext is generated by the automaton so as to validate the memorization of the line or lines containing the compressed audio signal.
• the PLC MP receives a line selection signal l s from a line selector SELIG and the synchronization signals s y , s h ; it counts the tops of the line synchronization signal with resetting to zero at each top of the frame synchronization signal.
• the automaton compares the line counting signal thus generated and the selection signal to deliver the valext signal.
• the frequency of conversion and of loading into the digital memory MDA (writing frequency F * 2 ) is provided by the control signal s' 2 which is generated by a phase locked loop PLL.
• the PLL loop includes a voltage controlled oscillator VCO, a counter-divider C0MPT and a phase comparator CPH.
• the control signal s' 2 carrying the frequency F ' 2 is delivered to the CAN converter by the oscillator VCO, while the write addresses wa' are supplied to the memory MDA by the counter-divider COMPT.
• a digital-to-analog DAC converter is connected to the digital memory MDA in order to receive the binary signals read from said memory and to convert them into analog logical signals.
• C ettelec tu reetlac onv ersion analog which follows, are e fected at a frequency of
• This signal s' .- is generated by the PLC from the line synchronization signal s h .
• the read addresses ra ′ are supplied to the memory MDA by the PLC MP.
• the signal from the DAC converter is thus a decompressed audio signal whose time scale is equal to that of the initial audio signal. It is sent to an SAE audio output for processing.
• the insertion device and the processing device described above with reference to FIGS. 1 and 4 can be combined in a single device making it possible to carry out, according to the chosen mode, namely insertion to deliver a video / audio signal to starting from a video signal and one or more audio signals, ie the processing of a video / audio signal to restore a video signal and one or more usable audio signals.
• Such a mixed device includes the means already described for the two aforementioned devices arranged in a similar manner, namely (the previous references have been used): video input means EV, EVA capable of receiving a video signal or a video / audio signal, at least one audio input EA capable of receiving an audio signal, a SEP separator of synchronization signals s y , s ⁇ connected to the video input means EV, EVA, an analog converter / digital ADC, an MDA memory connected to the analog / digital ADC converter, a digital / analog converter DAC connected to the output of said MDA memory, a MIX mixer connected to the video input means EV, EVA, MUXO, a locking loop of PLL phase connected to the SEP separator and adapted to deliver reading addresses ra, writing addresses wa ', a control signal s at the reading frequency F and a control signal from s ' 2 to the writing frequency F' 2 , a PLC with microprocessor MP programmed to generate
• This device is also provided with additional means which allow a selection of the chosen mode.
• These means comprise first of all a SELFONC function selector adapted to deliver to the PLC MP an i / e signal representative of the chosen operating mode, this signal being processed by the PLC to develop the CDM mode control signals which are delivered to various multiplexers or demultiplexers described below in order to establish through them the desired connection insertion / extraction.
• a MUXO multiplexer completes the video input means EV, EVA in order to connect the amplifier AMPLIV with the input of the video signal EV in insertion mode or with the input of the video / audio signal EVA in extraction mode.
• a multiplexer MUX1 is connected, on the one hand, to the aforementioned input means EV, EVA (at the output of the multiplexer MUXO), on the other hand, to the audio input EA (at the output of the amplifier AMPLIS) in order to receive the signals present at these inputs and to deliver one of these signals to the analog / digital converter CAN according to the mode control signal cdm.
• a MUX2 demultiplexer is connected, on the one hand, to the digital / analog converter DAC to receive the signal from it, on the other hand, to the MIX mixer and to an SAE audio output to deliver this signal to one of them depending on the cdm mode control signal.
• a MUX3 multiplexer is connected, on the one hand, to the PLL loop to receive the signals and addresses originating therefrom, on the other hand, to the analog / digital converter CAN, to the digital / analog converter DAC and to the memory MDA to deliver them as a function of the mode control signal cdm, respectively the control signal s'2 > the control signal s 2> and the addresses for reading or write ra, wa '.
• a multiplexer MUX ' 4 is connected, on the one hand, to the automaton to receive the signals coming from the latter, on the other hand, to the analog / digital converter CAN, to the digital / analog converter DAC and to the MDA memory to deliver to them as a function of the mode control signal cdm respectively the control signal s--, the control signal s * -
• the device operates like the device represented in FIG. 1 or like the device represented in FIG. 4.

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• Engineering & Computer Science (AREA)
• Multimedia (AREA)
• Signal Processing (AREA)
• Television Signal Processing For Recording (AREA)

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• 1991
  • 1991-07-12 FR FR9108932A patent/FR2679091B1/fr not_active Expired - Fee Related
• 1992
  • 1992-07-10 EP EP92916225A patent/EP0594774A1/de not_active Withdrawn
  • 1992-07-10 WO PCT/FR1992/000676 patent/WO1993001684A1/fr not_active Application Discontinuation

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