Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
  • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
  • H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
  • H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
  • H04L9/0662—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
  • H04L2209/12—Details relating to cryptographic hardware or logic circuitry

Definitions

• the invention relates to a ciphering device according to the preamble of claim 1.
• a ciphering device For the transferring of information it has been known for a long time in different applications to use different methods of ciphering the information before the trans ⁇ ferring thereof.
• the first reason for ciphering is that the information should not be possible to read for anybody who accesses the information in an improper way during the transfer.
• the problems of improper access to the information have increased rather than decreased.
• One previously known method is based on so called block ciphering according to which a data format with fixed block lengths is used.
• incoming data must be expanded to the block size used, adding redundant data to the information to be transferred.
• block ciphering should be used in a total ciphering of a connection, i.e. for both data and a transfer protocol, block synchronization must be implemented so as to identify the start and the end of transferred blocks, further increasing the amount of redundant data that has to be transferred.
• the ciphering process is identical each time it is used two identical messages in plain text will always result in two identical cryptograms.
• the complete deciphering key must be involved in the process which in practice delimits the size of the key, requiring in turn frequent changes of the key.
• Bit sequence cihpering includes implementation of internal registers, which are modified and will effect the ciphering process. As a result two identical messages will be ciphered differently from time to time. Accordingly, th most appropriate block size, i.e. 1, can be used in the ciphering process.
• the bit sequence generated does not hav to be synchronized with respect to the start and the end of the block, and all types of block sizes of the plain text can be ciphered without any data expansion.
• the internal registers have to be synchronized between a transmitter and a receiver so as to balance the ciphering and the dechipering process. The synchronization is accomplished by transmitting separately an initial value to said receiver.
• the ciphering device is provided with a sequence of bits to be ciphered and comprises a data input for said sequence, a data output for a ciphered bit sequence and a mixing unit, a first input thereof being connected to said data input, an output thereof being connected to said data output, and a second input thereof being connected to a code unit for generating code bits, said code unit comprising at least one shift register, the input thereof being connected to said data output, and at least one memory storing code bits, said memory being addressed from said shift register for outputing code bits into said mixing unit.
• a very large key is required in form of a large amount of code bits. As the key has to be large practical problems will arise in handling said key, and therefore the practical use of said method has been delimited.
• An object of the present invention is to overcome the problems and drawbacks mentioned above and to accomplish a ciphering device that is independent from blocks and that decreases dramatically the size of the key which has to be distributed to said transmitters and said receivers.
• FIG. 1 is a block diagram showing a basic circuit for a so called cipher feed back crypto according to prior art technique
• FIG. 2 is a block diagram showing the basics of the ciphering device according to the invention.
• FIG. 3 is a block diagram showing the basics of a deciphering device according to the invention.
• FIG. 4 is a block diagram showing a further development of the device according to the invention.
• FIG. 1 In the block diagram of FIG. 1 there is shown a ciphering device according to a prior art technique called "cipher feed back crypto".
• the device comprises a data input into which a sequence of bits to be ciphered is fed, and a data output 11, from which a ciphered bit sequence is taken.
• Said data input 10 is connected to a first input of a mixing unit 13, and said data output 11 is connected to an output of said mixing unit 13.
• Said data output 11 is connected also to an input of a shift register 15 forming part of a code unit 14.
• Said code unit 14 comprises also a memory 16, which is addressed by outputs of said shift register 15 and which stores code bits for the ciphering process. An output of said memory 16 is connected to a second input of said mixing unit 13.
• Said mixing unit 13 comprises preferably an EXOR gate.
• the deciphering accor ⁇ ding to the described method is a completely reversed process compared to the ciphering process, and therefore a deciphering device comprises corresponding units, that is data input 110, a data output 111, a mixing unit 113, a shift register 115, into which incoming ciphered data bits are fed, and a memory 116.
• the deciphered sequence of data bits is available on the output of said mixing unit 113.
• the device according to the invention shown in FIG. 2 comprises, in addition to the means included in the device shown in FIG.
• an address selecting means 12 which is provided with a first set of inputs 20, which are connected to outputs of said shift register 15, and a second set of inputs 21, which are connected to outputs of an address generating means 17.
• Said address selecting means 12 is also provided with a set of outputs 22 which are operatively connected to said memory 16 for addressing said memory.
• Said address generating means 17 is arranged to address all addresses in said memory 16 that are used for code bits. By said address selecting means 12 addresses to said memory are selected either from said shift register 15 or said address generating means 17. During a ciphering process said memory 16 is addressed by said shift register 15, and in a initiating process the addressing is made by said address generating means 17.
• the code bits that are stored in said memory 16 in the addresses selected by said address generating means 17 are provided by a pseudo-random generator 17, which preferably comprises a feedback shift register 19.
• a pseudo-random generator 18 In said pseudo-random generator 18 there is stored a start value which constitutes the key in this device. Means that are not shown are provided for inputting said key into said pseudo-random generator 18 at appro ⁇ priate points of time.
• said pseudo-random generator 18 comprises a shift register 19 a feed back polynomial calculates in a conventional manner a feedback value that is entered into the first position of said shift register 19.
• control unit 23 is arranged for the control of said address generating means and said memory 16, said control unit ensuring that an appropriate selec ⁇ tion and number of generated code bits is stored in all positions utilized in said memory 16.
• control unit ensuring that an appropriate selec ⁇ tion and number of generated code bits is stored in all positions utilized in said memory 16.
• some part or parts of the generated code bits sequence are omitted to render the search of said start value more difficult.
• a deciphering device functions in a way completely corresponding to the ciphering device of FIG. 2, one difference being that said shift register 115 is connected directly to said data input 110.
• Corresponding means and elements of said deciphering device has been given corresponding reference numerals with an addition of 100.
• FIG. 4 shows a further development of the device according to the invention, further comprising two sets of shift registers 15,15', address generating means 17,17' and memory units 16,16', all in series. In the embodiment shown only one pseudo-random generator is used, but also two can be utilized.

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• Engineering & Computer Science (AREA)
• Computer Security & Cryptography (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Storage Device Security (AREA)

Applications Claiming Priority (3)

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• 1991
  • 1991-07-01 SE SE9102040A patent/SE468730B/sv not_active IP Right Cessation
• 1992
  • 1992-07-01 WO PCT/SE1992/000490 patent/WO1993001578A1/en not_active Application Discontinuation
  • 1992-07-01 AU AU22916/92A patent/AU2291692A/en not_active Abandoned
  • 1992-07-01 EP EP92915602A patent/EP0592595A1/de not_active Withdrawn

Non-Patent Citations (1)

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