EP0561135A2 - Method of driving bistable displays, in particular ferroelectric liquid crystal displays - Google Patents

Abstract

With the same available maximum voltage of the line drivers and the same liquid crystal material as in the case of conventional FLC displays, information-carrying column pulses of shorter duration than for line pulses to build up write pulses have the effect of improving a number of display characteristics, for example the contrast or image refresh rate. The image refresh rate is further improved by overlapping line pulses of lines addressed one after the other. <IMAGE>

Description

The present invention relates to a liquid crystal switching and display device (display) with a special electrical control scheme, which leads to a high contrast and in particular to short switching times.

Switching and display devices which contain ferroelectric liquid crystal mixtures (“FLC light valves”) are known, for example, from EP-B 0 032 362 (= US Pat. No. 4,367,924). Liquid crystal light valves are devices that, for. B. due to electrical wiring change their optical transmission properties such that light falling through (and possibly reflected again) is intensity modulated. Examples are the well-known clock and calculator displays or liquid crystal displays in the OA (office automation) or TV (television) area. However, this also includes optical closures, so-called "light shutters", as used for. B. in copiers, printers, etc. are used. So-called "spatial light modulators" also belong to the field of application of liquid crystal light valves (see Liquid Crystal Device Handbook, Nikkan Kogyo Shimbun, Tokyo, 1989; ISBN 4-526-02590-9C 3054 and the works cited therein).

The electro-optical switching and display devices are constructed in such a way that the FLC layer is enclosed on both sides by layers which usually, in this order starting from the FLC layer, have at least one orientation layer, electrodes and a boundary plate (e.g. made of glass). are. They also contain a polarizer if they are operated in "guest-host" or reflective mode, or two polarizers if transmissive birefringence ("birefringence mode") is used as the mode. The switching and display elements can optionally further auxiliary layers, such as. B. Diffusion barrier or insulation layers included.

Such orientation layers, together with a sufficiently small spacing of the boundary disks, bring the FLC molecules of the FLC mixture into a configuration in which the molecules lie with their longitudinal axes parallel to one another and the smectic planes are arranged perpendicular or obliquely to the orientation layer. In this arrangement, the molecules are known to have two equivalent orientations, between which they can be switched by the pulsed application of an electric field, i. H. FLC displays can be switched bistably. The switching times are inversely proportional to the spontaneous polarization of the FLC mixture and are in the range of µs.

The main advantage of the FLC displays compared to the LC displays that have so far been found in industrial practice is the multiplex ratio that can be achieved. H. the maximum number of lines that can be controlled in the time-sequential method (“multiplex method”), which is practically unlimited in FLC displays in contrast to conventional LC displays.

A simple matrix arrangement of electrodes (rows 1 to n and columns 1 to m) is shown in Fig. 1. The electrodes are usually located on the inside of the carrier plates of the display with the rows on one and the columns on the other carrier plate. In the crossover areas, the pixels B, the liquid crystal located between rows and columns is switched. As usual, the electrodes are referred to as columns, to which the information-carrying pulses (also called column or data pulses) are applied. The lines are then activated in a stroboscopic manner sequentially by electrical pulses (activation pulses), which is the prerequisite for information transmission to the pixels of the lines.

A basic description of multiplex addressing for FLC displays has been made e.g. B. in Proc. SID 28/2, 211 (1987) and in Ferroelectrics 94.3 (1989). In EP-A 0 167 398 an addressing scheme is presented, in which the inscription of light and dark points takes place separately in two successive images. A disadvantage of the technology described here is that it leads to a 4-slot system when addressing is required to be free of DC voltage on average ("slot" is the usual term for this cycle time τ in this technology). The number of slots indicates how many clock cycles are required to write to a display line. For a given switching speed of the liquid-crystalline material and a given number of screen lines, this number is therefore proportional to the duration of an image construction and should therefore be kept as small as possible. A further disadvantage of the electrical control described in EP-A 0 167 398 is the harmful influence of the data pulses which occur in the so-called "worst case" (most unfavorable data pulse constellation when addressing determined by the image information) and therefore at half the frequency measured at the row addressing lead to a strong disturbance in the transmission of unaddressed pixels (switching elements) and thus ultimately to a deterioration in the contrast.

The number of slots can be increased by introducing so-called blanking pulses or (also called reset pulses), as in the literature (e.g. in Proc. SID 28/2, 211 (1987); Japan-Display 18, (1989); Liquid Crystals and Uses, vol. 1, p. 305 ff, World Scientific Publishing Co., 1990; Jap. J. Appl. Physics 28, L483 (1989) and in DE 4017893Al). These blanking pulses form part of the line addressing and have the purpose of switching one or more lines of the display into a certain state without the influence of any information transfer to other display lines. According to the in the Proc. SID described method this happens simultaneously for several lines in a special time interval in which no information is written into the display. This method has the disadvantage that these special time intervals lead to a lowering of the frame rate. In the other references mentioned above, the more common method is described, which consists in that Row pulses are applied which, due to their shape - ie their amplitude or time duration - switch one or more rows into a certain state independently of the simultaneous application of information-modulated column pulses. The second part of the row addressing is formed by the activation pulses, which follow the blanking pulses either immediately or with a certain time interval. In superposition with the column (data) pulses assigned to these activation pulses, such an activation pulse is now perceived by the assigned pixel as a switching pulse (selection) or as a non-switching pulse (half-selection). Regardless of the case, this overlay is referred to below as a write pulse. Blanking pulses of any line may overlap with blanking pulses and activation pulses of other lines.

All references cited have in common that the write pulses are constructed from addressing pulses of the same length on the row and column side. Activation and data pulses therefore have the same duration. This also applies to the switching (last) part of the addressing scheme, which is presented in Japan Display 18, (1989) and which follow each other directly in the blanking and writing pulse. The use of the methods described there to shorten the line addressing time also requires a correspondingly steeper electro-optical characteristic. This duration of column and activation pulses then represents the length of the smallest clock cycle τ (of the slot already explained above) (Fig. 2). If you want to avoid applying DC voltage to the display, you have to use bipolar pulses, at least for the column pulses leads to line addressing times of at least 2 * τ, since only a single line can receive its pixel information in this time interval. For this reason, a line addressing time of at least two slots is used in all references cited above.

As described above, the image change time of a display is the product of the line addressing time and the number of lines - for a given number of lines (due to standards or requirements for resolution) and a given number of slots proportional to the cycle time τ. The cycle time τ, in turn, is now capped for at least two reasons: 1. With no τ, the available electrical maximum voltage (limited by semiconductor components or costs) is not sufficient to switch the liquid crystal; 2. If the τ is too small, the voltage required for switching leads to electrical breakdown in the addressed pixel. The restriction mentioned under 1. relates primarily to the row drivers and not so much to the column drivers, since in the addressing methods described above the row drivers have to deliver at least twice the voltage as the column drivers.

It has now surprisingly been found that with the same maximum voltage available for the line driver modules and the same liquid crystal material, a number of display properties, e.g. B. the contrast or the frame rate, can be improved by choosing a shorter period of time for the information-carrying column pulses than for the line pulses, specifically also for the generation of the write pulse.

The invention thus relates to a method for multiplex addressing an FLC switching device, in which an electrical pulse sequence is applied to the row and column electrodes in such a way that the information is transmitted for a pixel in the form of a write pulse, which is built up from the superposition of activating row pulses and Information-carrying column pulses, characterized in that the individual column pulses building up the write pulse are shorter in time than the activating row pulses assigned in time. The invention relates to the structure of the write pulse and it is immaterial how the addressing scheme is otherwise carried out. In order to achieve a short image repetition time, it may be advantageous to work with blanking pulses. Lines addressed one after the other do not necessarily have to be lines that are spatially adjacent.

The method for multiplex addressing can also be carried out in that the longest column pulse building the write pulse is shorter than the shortest line pulse building up this write pulse.

It is advantageous if, during the action of a column pulse which carries the information for a display line, no further display line is provided with voltage on the line side. However, this does not apply to information-independent deletion.

The column pulses are applied in such time intervals that an overlapping row addressing with the row voltages building up the write pulse is possible (= sometimes simultaneous write pulse addressing of more than one row). In contrast, the column pulses must not overlap.

If the column pulses have a DC voltage component (off-set), there is a risk of unintentional switching of the system, which of course should be avoided in practice. DC-free addressing is therefore preferred. This also applies to the line pulses, averaged over several image change times.

A DC voltage component is avoided in particular if the write pulses are constructed antisymmetrically, i. H. in the case of time mirroring, represent similar pulses with inverter polarity.

In particular, the control according to the invention can be used advantageously if the ferroelectric liquid crystal in an SSFLC cell is previously brought into a so-called bookshelf geometry by electrical field treatment (SID 91 Digest pp. 396, 1991).

When using the known method of dividing the screen with double-sided column contacting, the method according to the invention can be carried out in each of the two partial images.

The invention can be used both for the black and white addressing of FLC displays with fixed values of the column pulse amplitudes (modulo sign) as also for addressing to generate analog grayscale with variable values of the column pulse amplitudes or lengths.

The invention is not limited to FLC displays, but can also be used for other switching elements which, due to their symmetry, can be switched by means of pulse addressing, such as e.g. B. Arrangements with nematic liquid crystals as described in WO 91/11747.

In use, the invention is not limited to optical displays, but can also be used for spatial light modulators (SLM) and the like. Ä. are used.

The construction of an electronic implementation of the controls according to the invention takes place in a basic analogy to the implementation as z. B. is described in DE 4 017 893.

In addition to the method described, the invention relates to an FLC switching device which contains the multiplex addressing system to which the method according to the invention can be applied.

• 1. Die Kontrastverringerung aufgrund des im passiven Multiplexverfahren unvermeidlichen Datenpulseinflußes auf nicht aktivierte Zeilen ist geringer, da in den erfindungsgemäßen Adressierschemata typischerweise automatisch Pausen zwischen den Datenpulsen für hintereinander adressierte Zeilen erscheinen, was zu geringerem Flicker führt.
• 2. Durch eine überlappende Zeilenadressierung wird die effektive Zeilenadressierzeit und damit die Bildwechsel- (oder -aufbau-)zeit kleiner, ohne daß dabei die Zeilenspannung verändert wird; lediglich die ohnehin niedrigen Spaltenspannungen werden erhöht.
• 3. Bei entsprechender Wahl des erfindungsgemäßen Verfahrens ist die maximal am Bildpunkt anliegende Spannung geringer als bei herkömmlichen Adressierungsschemata mit der gleichen Zeilenadressierzeit und deshalb geeignet, elektrische Durchbrüche zu verhindern.
• 4. Es ist nicht prinzipiell notwendig, daß die so erwirkte Verkürzung der Zeilenadressierzeit einer steileren elektroopischen Kennlinie bedarf.

The method according to the invention has the following advantages, among others:

• 1. The reduction in contrast due to the inevitable data pulse influence on non-activated lines in the passive multiplexing process is less, since in the addressing schemes according to the invention pauses typically appear automatically between the data pulses for successively addressed lines, which leads to less flicker.
• 2. By overlapping line addressing, the effective line addressing time and thus the picture change (or build-up) time is reduced without changing the line voltage; only the already low column tensions are increased.
• 3. With a corresponding choice of the method according to the invention, the maximum voltage present at the pixel is lower than in conventional addressing schemes with the same row addressing time and is therefore suitable for preventing electrical breakdowns.
• 4. In principle, it is not necessary that the shortening of the line addressing time obtained in this way require a steeper electro-optical characteristic curve.

The following examples are intended to illustrate the invention without restricting it.

example 1

Overlapping bipolar pulses of height V _{r are} applied to the lines. For this purpose, bipolar but shorter data pulses of the amplitude V _d are added in the pixels, the inversion point of which lies at the same time as the assigned bipolar line pulses (FIG. 3). The overlap time of the bipolar line pulses of successively addressed lines is (2b) τ where τ is the width of the (half) bipolar line pulses and aτ is the width of the (half) bipolar data pulses and the following applies that 0 <a <1, 0 <2b <1- a.

Depending on the polarity of the data pulses, the switching pulse switches (select pulse, supercritical) or does not switch (half-select, subcritical).

F1 besitzt die Phasenfolge X-2 S_c* 63 S_A 75 N* 851 und hat bei 25°C eine spontane Polarisation von 45 nC/cm².The effect of this addressing scheme was tested using the ferroelectric liquid crystal mixture F1. F1 has the following composition:

F1 has the phase sequence X-2 S _c * 63 S _A 75 N * 851 and has a spontaneous polarization of 45 nC / cm² at 25 ° C.

It was filled into a typical test cell with rubbed polyvinyl alcohol (PVA) as an orientation layer and a layer thickness of 1.5 µm, subjected to an electrical field treatment to achieve a quasi-bookshelf configuration (SID 91 Digest pp. 396, 1991) and with the addressing scheme described above wired (Fig. 4). The following were selected: τ = 32 µs, a = 0.5, 2b = 0.5, which results in an effective row addressing time of 48 µs. 4 (a) and (c) show an information-independent switching reset pulse and the switching (supercritical) write pulse, while FIGS. 4 (b) and (d) show the effect of the subcritical write pulse.

The pulse area that is primarily relevant for switching is shown hatched for the pixels in FIG. 3. In the subcritical case it is (V _r -aV _d ) τ and in the supercritical case (V _r + aV _d ) _τ . The line addressing time is 2 (1-b) τ, which is shorter than the time 2τ that applies to conventional addressing schemes. There are voltage-free intervals of length 2 (1-ab) τ between the column-side data pulses, which has an advantageous effect on the crosstalk behavior (DE 40 17 893 A1).

Example 2

The embodiment according to Example 1 can also be modified in such a way that the polarity of the bipolar line pulses of lines addressed one after the other is inverted. The information coding for the column pulses is inverted accordingly. This addressing has the advantage that the line drivers do not have to deliver more than two voltage levels (0 and V _r , or 0 and -V _r ) at a given time.

Example 3

The embodiment according to Example 1 can also be changed so that the first part of the bipolar row addressing pulse is omitted or - for the purpose of DC field compensation - elsewhere in the addressing scheme - e.g. B. in connection with a blanking pulse - is executed.

Example 4

As in Example 1, the lines are exposed to bipolar pulses, but without temporal overlap.

Conventional bipolar pulses of the same duration as the duration of the line pulses are applied to the columns. This serves as a reference to the embodiment according to the invention, in which, as in Example 1, column pulses of half the line pulse duration are used.

An FLC mixture with a spontaneous polarization of 35 nC / cm² and a phase sequence X-3 SmC * 56 SmA 79 N * 84 I is now in a typical test cell with a thickness of 1.9 µm, provided with a rubbed organic orientation layer on both sides of the FLC Layer connected with the two addressing schemes described. 5a, b and 6a, b show the interference of the optical transmission by the data pulses in comparison Reference and in the case according to the invention. The lower disturbance in the case according to the invention is clearly evident.

6a to 6c show the optical response after filtering through a low-pass filter, which clearly shows that the contrast in the case according to the invention is approximately twice as large as in the conventional comparison case.

Description of the figures Fig. 1

The pixels (indicated by way of example: B) of a liquid crystal switching element are the overlap regions of the electrode strips which are applied to the two inner sides of the substrates in such a way that they form horizontal strips (rows) on one substrate and vertical strips (columns) on the other substrate . In electrical addressing in the multiplex method, the information-carrying data pulses V _di (i = 1 to m) are by definition placed on the columns, while the lines are subjected to stroboscopic and sequential activation pulses V _rj (j = 1 to n). The known technique of a split screen can also be used, in which the columns z. B. are interrupted in the middle and two fields are written simultaneously by using both ends of the column for data input.

Fig. 2

Row pulse (1) and column pulse (2) subtract to the pixel signal (3). So far, controls with the same pulse duration for row and column pulses have been used to build up the write pulse.

Fig. 3

Overlapping line activation pulses (top line) allow a shorter line addressing time with correspondingly short pulses for data transmission (second and third lines from above). Exemplary pulse sequences for two information cycles are shown from the electrical addressing sequence for two rows (k and k + 1) (Fig. 3a) and two columns (i and i + 1) (Fig. 3b and c). These lead to the voltage curves shown in the lower part of the figure at the four overlapping pixels of the above. Rows and columns, (Fig. 3d and e).

Fig. 4

In the upper part of the diagrams, the sequence of pulses is shown as it acts on a picture element or on the test cell filled with the ferroelectric liquid crystal F1 according to Example 1. In the lower part the associated optical transmission curve of the liquid crystal cell is recorded in intensity units as measured with a photodiode.

The electrical pulse sequence contains a reset or blanking pulse R, which switches the liquid crystal independently of the action of data pulses, as well as a supercritical write pulse S (a) and c)) and a subcritical write pulse HS (b) and d)). The row pulses have a duration of τ = 32 µs and the column pulses have a duration of aτ = 16 µs. The simulated overlap time 2b of the line pulses is 16µs.

In a) and b) the row voltage V _r = 14.4 volts and the column voltage V _d = 7.2 volts while for c) and d) V _r = 14.4 volts, V _d = 9.6 volts.

Fig. 5

In the upper part of the diagrams, the sequence of pulses is shown as it is a picture element of an FLC display under conventional control experiences. The associated optical transmission curve is shown in the lower part of the picture. Below, the complete dark state is shown as a reference line. 5a and b clearly show the interference from the column pulses. A contrast (ratio of light to dark transmission) of just under 10: 1 can be seen from FIG. 5c.

6a and b

5 only when using the method according to the invention with half the column pulse width. A contrast of approximately 20: 1 can be seen from FIG. 6c.

Claims (10)

Method for multiplex addressing of an FLC switching device, in which an electrical pulse sequence is applied to the row and column electrodes in such a way that the information transmission for a pixel takes place in the form of a write pulse, which is built up from the superposition of activating row pulses and information-bearing column pulses, characterized in that that the individual column pulses building up the write pulse are shorter in time than the activating row pulses assigned in time. Method according to Claim 1, characterized in that the longest column pulse building up the write pulse is shorter than the shortest line pulse building up this write pulse. Method according to Claim 1 or 2, characterized in that during the action of a column pulse carrying the information for a display line, no further display line is provided with voltage on the line side, except for the purpose of deleting information independently. Method according to Claims 1 to 3, characterized in that the line pulses of the lines addressed one behind the other, which build up the write pulse, overlap in time. Method according to Claims 1 to 4, characterized in that the column pulses building up the write pulse do not have a DC voltage part overall on average. Method according to Claims 1 to 4, characterized in that the line pulses have no DC voltage part over the time average over one or more picture change times. A method according to claim 1, characterized in that it is used for multiplex addressing of bistable or multistable liquid crystal displays which can be switched by means of pulse addressing due to their polar symmetry properties. Method according to Claims 1 to 7, characterized in that the write pulses are constructed antisymmetrically. Method according to Claims 1 to 8, characterized in that the ferroelectric liquid crystal is in a bookshelf or quasi-bookshelf geometry. FLC switching device containing a multiplex addressing system, in which the information is transmitted for a pixel in the form of a write pulse, characterized in that the individual column pulses building up the write pulse are shorter in time than the activating row pulses assigned in time.

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