EP0539488A1

EP0539488A1 - Method and apparatus for bandwidth limited binary signals.

Info

Publication number: EP0539488A1
Application number: EP91913635A
Authority: EP
Inventors: Ab Unitex
Original assignee: Unitex AB
Current assignee: NOMET MANAGEMENT SERVICES BV
Priority date: 1990-07-18
Filing date: 1991-07-18
Publication date: 1993-05-05
Anticipated expiration: 2011-07-18
Also published as: JPH05509448A; AU650895B2; DE69124242D1; SE9002460D0; AU8234291A; SE9002460L; DE69124242T2; ATE147907T1; SE466725B; EP0539488B1; US5454006A; JP3043067B2; WO1992002081A1

Abstract

Dans une méthode permettant de limiter la bande passante d'un signal binaire sélectionné (B), on obtient un signal numérique modulé (D) présentant une série continue de modifications du niveau. Les deux états logiques occurents (1, 0) sont chacun représentés par un train d'impulsions symétriques correspondant, dont les fréquences (f1, f2) sont réciproquement différentes. La fréquence la plus élevée (f2) est égale au nombre de bits transmis chaque seconde divisé par deux hertz. La transition entre les deux trains d'impulsion s'effectue de telle sorte que l'intégrale du signal résultant soit nulle sur une durée de trois ou quatre bits d'information. Selon une forme de réalisation préférée d'un codeur et décodeur, chacun comprend un compteur de mot de code qui, combiné à un circuit logique de combinaison (tableau de mot de code) déclenche ou est déclenché par un registre à décalage permettant de transmettre ou de recevoir respectivement le signal numérique modulé.A method of limiting the bandwidth of a selected binary signal (B) results in a modulated digital signal (D) having a continuous series of level changes. The two logic states occurring (1, 0) are each represented by a train of corresponding symmetrical pulses, the frequencies of which (f1, f2) are mutually different. The higher frequency (f2) is equal to the number of bits transmitted each second divided by two hertz. The transition between the two pulse trains takes place in such a way that the integral of the resulting signal is zero over a period of three or four information bits. According to a preferred embodiment of an encoder and decoder, each comprises a code word counter which, combined with a combination logic circuit (code word table) triggers or is triggered by a shift register making it possible to transmit or to respectively receive the modulated digital signal.

Description

METHOD AND APPARATUS FOR BANDWIDTH LIMITED BINARY SIGNALS,

Technical Field

The present invention relates to a method of limiting the bandwidth of a selected binary signal, by generat¬ ing a digital signal which exhibits a continuous series of changes in signal level. The two logic states are each represented by a respective pulse train, which have the respective frequencies fl and f2.

Background Art

Several different digital signal transmission methods are described in the literature. For example, various textbooks describe methods which are generally known under the designations NRZ-coding, Bifas-coding and DM- coding. See, for instance, the product catalogue "Z16C30 CMOS USC Universal Serial Controller", May 1989, ZiLOG Inc., Campbell, California 95008-6609, U.S.A. , page 8.

The most simplest and the most common method is the NRZ method (Non Return to Zero) , which implies that a logic one is corresponded by a high signal and a logic zero is corresponded by a low signal (or vice versa). NRZ- signalling requires a transmission channel that has a bandwidth of from 0 to 1/TB Hz, where TB is the dura¬ tion of a data bit in seconds. The NRZ-code has a large direct voltage component, which renders it un¬ suitable when the lower band limit differs from 0. Neither does NRZ guarantee a smallest time lapse be- tween two mutually sequential changes in signal level. which means that the clock signal cannot be obtained from the data signal, but must be transmitted on a separate channel.

Another method is the Bi-phase code method. In the Bi¬ phase code, at least one and at most two changes in signal level always occur with each bit interval. Although this enables the clock signal to be obtained from the coded signal, the bandwidth of the transmis- sion channel is increased to 0-2/TB. The most serious drawback with the Bi-phase codes is that the upper band limit is twice the upper band limit with NRZ signal¬ ling.

The Manchester code is a variant of Bi-phase modula¬ tion, also known as Biphase-level, where a logic one is coded as 1/2TB high signal level followed by 1/2TB low signal level and a logic zero is coded as 1/2TB low signal level followed by 1/2TB high signal level. The Manchester code is therefore dependent on polarity.

The DM-code (Delay Modulation) or the Miller code is another method which, similar to the Bi-phase code, enables the clock signal to be regenerated from the modulated data signal, but lacks the drawback of the Bi-phase code with respect to the high upper band limit. The DM-code modulated data signal, however, is completely void of direct voltage components. In DM, a logic one is coded as a change in signal level in the middle of the bit interval and a logic zero is coded as a change in signal level at the end of the bit inter¬ val, only if it is followed by a further zero.

Both the Manchester codes and the DM codes also have the drawback that in the case of an infinite stream of ones or zeroes, the modulated data signal is identical to the phase shift of solely 1/2 data bit. This re¬ sults in a synchronization problem, since it is neces¬ sary for the receiver (the decoder) to be aware of the phase position in order to be able to decode the modu¬ lated signal correctly.

Disclosure of the Invention

The object of the present invention is to provide a method which will avoid the drawbacks associated with the known methods and to modulate a digital signal so that the resultant signal will be more suited for transmission over bandwidth limited media, for example a cable.

This is achieved in accordance with the invention in that the frequencies fl, f2 of the pulse train of the modulated digital signal are mutually different, and in that the higher frequency, f2, is equal to the number of data bits per second divided by two (1/2TB). The transition between the two pulse positions is arranged so that the integral (RDS) of the resultant signal will be equal to zero within the duration of four trans- itted data bits (4TB).

The modulated signal is coded differentially, so that it is the transitions or junctions from one signal level to the other that are information carrying (and not the actual levels themselves). This implies a polarity dependency.

In a particularly preferred embodiment of the inventive method, in which the selected binary input signal is an NRZ-signal, the following coding table is used for translating the selected NRZ-signal:

+ = one or more zeroes: The first 3 zeroes are coded in accordance with the code word, whereafter there remains at least one further zero.

The code word is twice the length of the coded binary bit pattern, such that 2 bits for each NRZ-bit are used for modulating the upptecknignsmediumet. The code word modulates the recording means so that a logic one (1) will result in a change in signal level after the bit interval, and so that a logic zero (0) will result in no change in signal level.

The code word can also be expressed as a trinary? (with the base 3) . When the code word is expressed with the base 3, corresponding reasoning is then: The code word modulates the r ecording means such that a one (1) results in a change in signal level in the middle of the bit interval, a two (2) will result in a change in signal level after the bit interval, and a zero (0) will result in no change in signal level. This is a definition of the code word. It can also said be that a one (1) results in a change in signal level at the BEGINNING of the bit interval and a two (2) in the MIDDLE of the bit interval. Similar to the place change of the numerals 1 and 0 of the NRZ-data.

It will be seen from the coding table that the modu¬ lated signal contains signal transitions or junctions with time intervals in steps of TB/2, although never less than 1TB and never more than 4TB.

The code word is transmitted differentially, such that the NRZ-signal in the second row of the code table (01) is modulated to 0011 when the preceding bit is o, or to 1100 when the preceding bit is 1.

Synchronization is achieved because, in the resultant bit stream, which is composed of the code words, the sequence 10101 (binary) is unique for three consecutive ones (111) in the original NRZ-signal. This fact is utilized by the receiver (the decoder) for determining the phase position of the incoming bit stream.

Description of Preferred Bmbofliments

The method according to the present invention will now be described in more detail with reference to the accompanying drawings, in which

Figures 1-3 illustrate the modulation of signal level at different conceivable sequences of logic ones and zeroes in the digital input signal;

Figure 4 illustrates an exemplifying coder arrangement by means of which the coding method can be carried out and which lies within the scope of the invention; and Figure 5 illustrates an exemplifying decoder arrange¬ ment by means of which the decoding method can be carried out and which lies within the scope of the invention.

The binary input signal B is illustrated in the Figures by different sequencies of logic ones, 1, and zeroes, 0, that can occur. The code word sequence C (expressed with the base 3) is given during each such binary signal, this sequence being used in the inventive method. Shown beneath these sequencies is the resul¬ tant digital signal D, which in the illustrated and described preferred embodiment of the invention has been modulated in accordance with the inventive method in a manner such that the highest and the lowest fre¬ quency will be 2/TB and 1/8TB respectively. The refer¬ ence sign and magnitude TB signifies respectively a bit interval and the duration in seconds respectively of a data bit. Shown on the bottom line in each of Figures 1-3 are the values of the integral RDS (Run Length

Digital Sum), which according to the method shall be equal to zero within a period of 4TB.

Figure 1 shows a selected binary signal B which con- tains a sequence of logic ones, 1, i.e. each bit inter¬ val TB consists of a logic one. According to the invention, such a sequence of logic ones is modulated with code word C, which in Figure 1, and also in the Figures following Figure 1, is expressed as a trinary, and results in the digital signal D. Thus, a logic one is coded as a change in the middle of each bit interval TB when this logic one is preceded by another logic one. This is presented as case I in the Coding Table presented above. Figure 2a illustrates case II according to the Coding Table, in which a zero is followed by a one. Thus, the digital signal D is modulated by a change in signal level after the bit interval TB in which the logic zero occurs. If the selected binary signal B contains a sequence of two logic zeroes followed by a logic one, as illustrated in Figure 2b and presented as case III in the Coding Table, the digital signal D is modulated by a change in signal level in the middle of the bit interval TB that includes the second logic zero.

Figure 2c illustrates a conceivable coding possibility when the selected binary signal B includes a sequence of three logic zeroes which are followed by a logic one. In this case, the coding is obtained by modu¬ lating the digital signal D such as to present a change of its signal level after each bit interval TB that includes a logic zero. However, it has been found more advantageous to modulate the digital signal D such as to present a change in signal level after the second bit interval TB that includes a zero, as will be seen from Figure 2d and illustrated with case IV in the Coding Table presented above.

In those instances when the selected binary signal B includes a sequence of more than three zeroes prior to a subsequent one, case V in the Coding Table presented above, the digital signal D is modulated in accordance with the present invention such as to present a change in its signal level at both the middle of the second bit interv 1 TB and at the end of the third bit inter¬ val TB. This is shown in Figure 3.

In order to illustrate how the inventive method can be realized, a coding arrangement and a decoding arrange- ment will now be described with reference to Figures 4 and 5. It will be understood, however, that these two arrangements are merely given by way of example only and that the method can be practiced equally as well with other arrangements or with a modified arrangement.

CODER

A coding arrangement by means of which the inventive method can be carried out includes a code word counter 1, a shift register 2, a feedback-connected flip-flop 3 and a combinatory logic 4 which forms a code word table. The code word counter 1 is constructed to count-up one step for each pulse and if the counter counts-up from 3, it will become 1. It can only be zero when set to zero. (Zero setting 0-1-2-3-1-2-3-1- 2-3-1). Incoming bit streams are detected at a rate of l/TB. The shift register 2 and the feedback-connected flip-flop 3 are clock controlled at 2/TB. The code word counter 1 is clock controlled at a rate of l/TB.

At the beginning of a coding process, the shift regis¬ ter 2 is set to 10101010, which is the state to which it would be set after four NRZ-αnes (1111), in order to enable the receiver (the decoder in Figure 5) to be able to find the correct phase position in the modu¬ lated signal D. When an incoming data bit is a logic one (l), the code word is read in that row to which the code word counter 1 points and this code word is in- serted in the shift register 2, whereafter the code word counter 1 is set to zero. When the incoming data bit is zero (0) and the code word counter 1 is numeral 3, the code word is read in line 3+ and this code word is introduced into the shift register 2 with a dis- placement or shift of two steps. When the incoming data word is zero (0), the code word counter 1 σounts- up one step. Only the logic ones of the code word C (Figures 1-3) need be written into the shift register 2, since a logic zero is clocked into the least sig- nificant bit in each clock cycle.

The feedback-connected flip-flop 3 is advantageously coupled back via an XOR-gate 6.

DECODER

An arrangement for regenerating a selected binary signal B from a modulated signal D includes a code word counter 11, a shift register 12, two flip-flops 17, 18, a phase-locked loop (DPLL) 16 and combinatory logic which forms code word table 14, a comparator 13 and a synchronizing detector 15. The construction of the code word counter 11 coincides with the construction of the code word counter 1 in the coder arrangement. One of the aforesaid flip-flops is a RXC flip-flop 17 which, in response to a signal from the synchronizing detector 15, is intended to activate an output flip- flop 18 from which the regenerated selected binary signal B can be obtained. The shift register 12 and the RXC flip-flop 17 are clock controlled at a rate of 2/TB. The code word counter 11 and the output flip- flop 18 are clock controlled at a rate of l/TB.

The incoming signal D, which consists of a signal modulated in accordance with the method (ADPC High

Density Pulse Code) is delivered to the digital phase- locked loop (DPPL) 16 which is operated at a frequency which is several times higher than the frequency of the incoming signal D (e.g. 16/TB) . When the signal is detected, there is produced on the output of the DPLL- loop 16 a clock signal (2/TB) which is in phase with the incoming signal D. The clock signal 2/TB is used to clock the coded signal D into the shift register 12. When the last five bits in the shift register 12 are 10101, the flip-flop of the synchronizing detector 15 flips, wherein the RXC flip-flop 17 is activated and produces a clock signal having the frequency l/TB, which is in phase with the regenerated binary signal B. The code word indicated by the code word counter 11 is compared with the content of the shift register 12 in each RXC cycle. If the code word coincides with the content of the shift register, a logic one (1) is clocked into the output flip-flip 18 and the code word counter 11 is set to zero. If there is no such coin- cidence, a logic zero (0) is clocked into the output flip-flip 18 and the setting of the shift register 12 is controlled so as to coincide with the beginning of a longer code word or, when the code word counter 11 is 3, so that the shift register 12 contains the code word in the line (3+) according to the above described

Coding Table. If an error is detected, the synchro¬ nizing flip-flop 15 is reset and the decoder again searches for the synchronizing pattern.

The described exemplifying coder/decoder embodiment is only suited for an NRZ-code which, in turn, is coded according to some supervisory protocol, for example with start and stop bits which are able to distinguish the original signal from the decoded signal when the decoded signal is introduced by a number of logic ones (those that were used for synchronization) and is terminated with logic zeroes. The terminating zeroes can be avoided by delaying the NRZ-signal through a plurality of series-connected flip-flops (not shown). The method can be extended with special code words which can be used for more advanced synchronization and control of a communication channel.

A full implementation for transferring blocks of binary data of selected content and length in the form of a data package can be constructed in accordance with the following, in which the code words are expressed in base 3:

preamble beginning of frame type 1 beginning of frame type 2 beginning of frame type 3 beginning of frame type 4

0 - co number of data bits end of frame mark . postamble

Thus, a selected binary signal B can be transmitted with pronounced bandwith limitation with the aid of the inventive method. The thus modulated digital signal D is truly binary, having solely two levels. When prac¬ ticing the present invention, there is obtained a bit- coded signal of high information density, high power spectrum and narrow bandwidth, which we have according¬ ly designated HDPC, High Density Pulse Code. The bit- code modulated signal contains no direct voltage com¬ ponent and is, in itself, clock controlled. In the case of data communication, there is obtained with this bit-code modulated signal automatic (re-) synchroniza¬ tion and phase error detection. The inventive method .3 well-suited for use within both data communcation and for storing digital information. In the case of data communication, the method can be used with both point-to-point and with bus (multidrop) connections and data can be transmitted continuously or in block form (data package).

It will be understood that the illustrated circuit construction described with reference to Figures 4 and 5 merely represents an example of how the inventive method can be realized. Both of the aforediscussed functions coding and decoding can be integrated in a single logic circuit. It will also be obvious to one of normal skill in this art that the method can be applied with other techniques which include sequential logic, with or without the aid of a read memory for translating bit patterns, or as a state machine.

Claims

1. A method for limiting the bandwidth of a selected binary signal (B) , by generating a modulated digital signal (D) which presents a continuous series of signal level changes when the two logic states (1, 0) are each represented by a respective symmetric pulse train having the frequencies fl and f2, c h a r a c ¬ t e r i z e d in that the frequencies fl, f2 are mutually different, wherein the higher frequency f2 is equal to the number of data bits transmitted each second divided by two herz (1/2TB) , and in that the transition between the two pulse trains is arranged so that the integral of the resultant signal will be zero within the duration of three or four data bits.

2. A method according to Claim 1, c h a r a c ¬ t e r i z e d in that the modulated signal (D) is truly binary having solely two levels.

3. A method according to Claim 1, c h a r a c ¬ t e r i z e d in that the ratio between the longest and the shortest time lapse between two mutually se¬ quential changes in signal level is at most 4:1.

4. A method according to Claim 1, c h a r a c ¬ t e r i z e d in that the time lapse between two mutually sequential changes in signal level is form 1 to 4 times duration of a data bit (TB) in steps of 1/2 times the duration of a data bit.

5. A method according to any one of the preceding Claims, c h a r a c t e r i z e d in that a sequence of logic ones (1) of the selected binary signal (B) modulates the digital signal (D) such as to present a change in signal level in the middle of each bit inter¬ val (TB) , and in that when a logic one is preceded by a logic zero, there is no change in the signal level during the bit interval (TB) (Figures 1 and 2 respec- tively) .

6. A method according to any one of Claims 1-4, c h a r a c t e r i z e d in that the occurrence of a single logic zero (0) followed by a one (l) in the selected binary signal (B) results in modulation of the digital signal (D) such as to present a change in signal level after that bit interval (TB) in which the logic zero is included, whereas the occurrence of two logic zeroes (0) in a sequence which is followed by a one (1) in the selected binary signal (B) results in modulation of the digital signal (D) such as to present a change in signal level in the middle of the bit interval (TB) that includes the second logic zero (Figures 2a and 2b respectively).

7. A method according to any one of Claims 1-4, c h a r a c t e r i z e d in that a sequence of three logic zeroes (0) followed by a one (1) in the selected binary signal (B) results in modulation of the digital signal (D) such as to present a change in the signal level after each bit interval (TB) that includes logic zero (Figure 2c) .

8. A method according to any one of Claims 1-4, c h a r a c t e r i z e d in that a sequence of three logic zeroes (0) followed by a one (1) in the selected binary signal (B) results in modulation of the digital signal (D) such as to present a change in the signal level after the second bit interval (TB) (Figure 2d) .

9. A method according to any one of Claims 1-4, c h a r a c t e r i z e d in that in that a sequence of three logic zeroes (0) followed by at least a further zero (0) in the selected binary signal (B) results in modulation of the digital signal (D) such as to present a change in the signal level in the middle of that bit interval (TB) which includes the second zero (0) and a further change in the signal level at the end of that bit interval (TB) which includes the third zero (0), wherein this sequence is repeated until fewer than four zeroes remain in the limited binary signal (B) (Figure 3).

10. A coder for limiting the bandwidth of a selected binary signal (B) by producing a modulated digital signal (D) which presents a continuous series of changes in signal level when the two logic states (1, 0) are each represented by a respective symmetrical pulse train having the frequencies fl and f2, c h a r a c t e r i z e d by a code counter (1) which is controlled by the selected binary signal (B) such as to modify, together with the input signal, the content of a shift register (2) whose output is connected to a feedback-connected flip-flop (3) from whose output the digital signal (D) can be obtained.

11. A coder according to Claim 10, c h a r a c ¬ t e r i z e d in that the code word counter (1) is connected to an input of an OR-gate (5), whose other input is supplied with the selected binary signal (B) and the output of which is connected to the charging input (SET) of the shift register (2).

12. A decoder which functions to recreate a selected binary signal (B) from a modulated digital signal (D) which presents a continuous series of signal level changes where the two logic states (1, 0) are each represented by a respective symmetrical pulse train having the frequencies fl and f2, c h a r a c - t e r i z e d by a shift register (12) and a clock- controlled phase locked loop (16) whose inputs are supplied with the modulated digital signal (D) and whose outputs are connected to the data inputs and clock inputs respectively of an output flip-flop (18) , wherein the register includes in its line to the output flip-flip, from whose output the selected binary signal (B) can be obtained, a comparator (13) whose output is coupled back to its other input, in addition to the output flip-flop, via a code word counter (11) and a combinatory logic (4).

13. A decoder according to Claim 12, c h a r a c ¬ t e r i z e d by a synchronizing detector (15) which is connected to the shift register (12) and which is intended to be activated when the modulated digital signal (D) contains a predetermined synchronizing pattern (e.g. 10101 binary) and is intended to be reset upon detection of an unpermitted signal.