EP0512263B1 - Circuit for generating very weak currents - Google Patents

Description

The invention relates to a circuit for generating very small currents.

State of the art

DE-A-3124289 describes a circuit which contains a current mirror. EP-A-0366253 describes a circuit with a noise-insensitive current mirror for generating a mirrored output current. DE-A-3139166 describes a current source which can be controlled by means of a current mirror and has limiter properties. US-4,673,867 describes a current mirror circuit whose output current has a temperature-independent relationship to a reference current. None of these documents contain a stepped current mirror for generating very small currents.

invention

The invention has for its object to provide a circuit with which very small currents can be generated. This object is achieved by the circuit according to the invention specified in claim 1.

To generate very small currents, eg in the nA range, multiple current mirroring with the help of multiple emitters can be used, but the currents generated with this depend on parameter tolerances and temperatures. In addition, such circuits require a relatively large chip area when implemented in an integrated circuit.
In principle, the solution according to the invention is that means for current mirroring (13, 23, 33) are connected to means for changing the amount (14, 24, 34) of the mirrored current, the ratio of a reference current fed into the means for current mirroring (I _ref ) can be set to a current provided by the means for changing the amount (I _out / I _out ') with one or more components (R, R') contained in the means for changing the amount, the means for current mirroring one or more transistors (13, 23, 28, 33, 38) and the means for changing the amount can contain one or more transistors (14, 24, 27, 34, 37) and the component contained in the means for changing the amount for adjusting from a resistor (R) or consist of several resistors (R, R ').

Advantageous developments of the circuit according to the invention result from subclaims 2 to 9.

The ratio of the reference current of the current mirror circuit to the first output current at the collector of the output transistor can be set by dimensioning a first resistor R in the emitter of the output transistor of a current mirror circuit. By adding a second current mirror stage with a second resistor R 'contained therein and with a second output current, the ratio of the reference current to the first output current, which corresponds to the ratio of the reference current to the first output current, results for R = R', when using an integrated circuit only a relatively small chip area is required.
This reduction in the currents can advantageously be increased further by designing a transistor in the second current mirror stage as a multiple transistor.

drawings

Fig. 1

eine Stromspiegelstufe;

Fig. 2

eine mit einer zweiten Stromspiegelstufe erweiterte Stromspiegel-Schaltung;

Fig. 3

eine mit einer zweiten Stromspiegelstufe erweiterte Stromspiegel-Schaltung mit Ausgangsstrom-Abschaltmöglichkeit.

Exemplary embodiments of the invention are described with the aid of the drawings. The drawings show in:

Fig. 1

a current mirror stage;

Fig. 2

a current mirror circuit expanded with a second current mirror stage;

Fig. 3

a current mirror circuit expanded with a second current mirror stage with output current switch-off possibility.

Embodiments

wobei U_T die Temperaturspannung ist.1 shows a current mirror circuit with a first current mirror transistor 13 and a first transistor 14. From an operating voltage 10, the collector of the first current mirror transistor is fed with a reference current I _ref via a current source 11. The base and the collector of the first current mirror transistor are connected to the base of the first transistor. The emitter of the first current mirror transistor is located directly and the emitter of the first transistor is connected to ground via a first resistor R. The open collector of the first transistor supplies the output current I _out . The ratio of I _ref to I _{out can be} set by dimensioning the first resistor R: $${\text{I.}}_{\text{out}}{\text{* R = U}}_{\text{T}}{\text{* ln (I}}_{\text{ref}}{\text{/ I}}_{\text{out}}\text{),}$$

where U _{T is} the temperature voltage.

wobei k die Anzahl der parallelgeschalteten Transistoren an Stelle des ersten Transistors ist.I _out can advantageously also be reduced by designing the first transistor 14 as a multiple transistor. Then: $${\text{I.}}_{\text{out}}{\text{* R = U}}_{\text{T}}{\text{* ln (I}}_{\text{ref}}{\text{* k / I}}_{\text{out}}\text{),}$$

where k is the number of transistors connected in parallel instead of the first transistor.

FIG. 2 shows a stepped current mirror circuit with a first current mirror transistor 23 and a first transistor 24. From an operating voltage 20, the collector of the first current mirror transistor is fed with a reference current I _ref via a current source 21. The The base and the collector of the first current mirror transistor are connected to the base of the first transistor and to a second resistor R '. The emitter of the first current mirror transistor is located directly and the emitter of the first transistor is connected to ground via a first resistor R. The open collector of the first transistor supplies the output current I _out .
The other side of the second resistor R 'is connected to the base of a second transistor 27 and to the collector and base of a second current mirror transistor 28. The emitter of the second current mirror transistor is grounded and the emitter of the second transistor is connected to the emitter of the first transistor. The open collector of the second transistor delivers the reduced output current I _out '.
Then (for R = R ′): $${\text{I.}}_{\text{out}}{\text{* R = U}}_{\text{T}}{\text{* ln (I}}_{\text{out}}{\text{/ I}}_{\text{out}}\text{′).}$$

wobei n die Anzahl der parallelgeschalteten Transistoren an Stelle des zweiten Stromspiegel-Transistors ist.Advantageously, I _out 'can still be reduced by designing the second current mirror transistor 28 as a multiple transistor.
Then (for R = R ′): $${\text{I.}}_{\text{out}}{\text{* R = U}}_{\text{T}}{\text{* ln (I}}_{\text{out}}{\text{/ (I}}_{\text{out}}\text{′ * N)),}$$

where n is the number of transistors connected in parallel instead of the second current mirror transistor.

$${\text{I}}_{\text{out}}{\text{*R = U}}_{\text{T}}{\text{*ln(I}}_{\text{out}}{\text{/(I}}_{\text{out}}\text{′*n)).}$$

If both the first transistor 24 and the second current mirror transistor 28 are replaced by k or n multiple transistors, the following applies (for R = R ′): $${\text{I.}}_{\text{out}}{\text{* R = U}}_{\text{T}}{\text{* ln (I}}_{\text{ref}}{\text{* k / I}}_{\text{out}}\text{),}$$

$${\text{I.}}_{\text{out}}{\text{* R = U}}_{\text{T}}{\text{* ln (I}}_{\text{out}}{\text{/ (I}}_{\text{out}}\text{′ * N)).}$$

With R = R 'and k = n = 1, the same current ratio as for I _ref / I _out advantageously results for I _out / I _out '.

In this way, current sources e.g. for the range from 1 ... 500nA. Such current sources can be used, for example, to implement fully integrated integrator circuits with long integration times, e.g. in the range, 0.015 ... 0.06s, and very small integration capacities, e.g. in the range 5 ... 20pF.

FIG. 3 shows a stepped current mirror circuit with a first current mirror transistor 33 and a first transistor 34. From an operating voltage 30, the collector of the first current mirror transistor is fed with a reference current I _ref via a current source 31. The base and the collector of the first current mirror transistor are connected to the base of the first transistor and to a second resistor R '. The emitter of the first current mirror transistor is located directly and the emitter of the first transistor is connected to ground via a first resistor R. The open collector of the first transistor supplies the output current I _out .
The other side of the second resistor R 'is connected to the base of a second transistor 37 and to the collector and base of a second current mirror transistor 38. The emitter of the second current mirror transistor is grounded and the emitter of the second transistor is connected to the emitter of the first transistor. The open collector of the second transistor delivers the reduced output current I _out '.
The same relations as for FIG apply. 2, but the currents can I _out and _out I 'by the additional switching current I _off switch off. The following applies:
I _off * R approximately ≧ 0.5 V.

Claims (7)

1. Circuit for generating a reduced current (I_out) with means for current reflection (13, 23, 33) and means for modifying the size (14, 24, 34) of the reflected current connected thereto, whereby the ratio of a reference current (I_ref) fed into the current reflection means to the reduced current (I_out) and can be adjusted using a component (R) contained within the size modification means, characterised in that second current mirror means (28, 38) is connected via a second component (R′) to the current reflection means (23, 33) which second means controls second size modification means (27, 37) - in particular a transistor - which is connected to the component (R) in the size modification means and which makes available a current (I_out′) further reduced compared with the reduced current (I_out) and dependent on the reference current (I_ref), the further reduced current being variable dependent upon the size of the component (R) and/or the second component (R′) in the size modification means, such that in the case of equality of these components the ratio of the reference current (I_ref) to the reduced current (I_out) is equal to the ratio of the reduced current (I_out) to the further reduced current (I_out′).
2. A circuit according to claim 1, characterised in that the size modifications means contains a transistor or a multiple transistor (24, 34).
3. A circuit according to claim 1 or 2, characterised in that the second current reflection means contains a multiple transistor (28, 38) or a corresponding number of current mirrors connected in parallel.
4. A circuit according to one or more of claims 1 to 3, characterised in that the component and/or the second component is a resistor.
5. A circuit according to one or more of claims 2 to 4, characterised in that the transistor or the multiple transistor in the size modification means (14, 24, 34) is connected to earth via a resistor (R).
6. A circuit according to one or more of claims 1 to 5, characterised in that the reduced (I_out) or the further reduced (I_out′) current can be switched off by means of a switching current (I_off) fed into the size modification means (14, 24, 34) or into the second size modification means (27, 37).
7. A circuit according to one or more of claims 1 to 6, characterised in that the further reduced current (I_out′) lies in the range 1 nA to 500 nA.

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