EP0491389B1 - Semiconductor power component - Google Patents

Semiconductor power component Download PDF

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Publication number
EP0491389B1
EP0491389B1 EP19910121732 EP91121732A EP0491389B1 EP 0491389 B1 EP0491389 B1 EP 0491389B1 EP 19910121732 EP19910121732 EP 19910121732 EP 91121732 A EP91121732 A EP 91121732A EP 0491389 B1 EP0491389 B1 EP 0491389B1
Authority
EP
European Patent Office
Prior art keywords
semiconductor body
semiconductor
substrate
wafer
substrate wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP19910121732
Other languages
German (de)
French (fr)
Other versions
EP0491389A1 (en
Inventor
Reinhold Dr. Kuhnert
Roland Dr. Sittig
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
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Siemens AG
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Publication of EP0491389A1 publication Critical patent/EP0491389A1/en
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Publication of EP0491389B1 publication Critical patent/EP0491389B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/427—Cooling by change of state, e.g. use of heat pipes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/8382—Diffusion bonding
    • H01L2224/8383—Solid-solid interdiffusion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor

Definitions

  • the invention relates to a power semiconductor component.
  • a component of this type is known from FR-A-2 090 206, the component having a semiconductor body which is connected on both main surfaces by soft soldering to an upper and a lower substrate wafer and which has a plastic ring which the substrate wafers and the Surrounds semiconductor body on the vand side.
  • a component of this type is known from EP-A-0 242 626.
  • Such components are usually installed in a gas-tight housing in order to protect them from mechanical damage and harmful environmental influences.
  • Both the electrical resistance of the resulting arrangement and its thermal resistance must be kept as low as possible in order to ensure low-loss operation and effective cooling of the component.
  • the invention has for its object to provide a power semiconductor device of the type mentioned, the electrical and thermal properties are improved compared to the conventional components of this type. This is achieved according to the invention by training according to claims 1 or 2.
  • the advantage that can be achieved with the invention is, in particular, that the individual parts of the component are joined together in a material-locking manner by pressure sintering or diffusion welding on their surfaces through which the load current flows. If one compares the encapsulated embodiments of the power semiconductor component according to the invention with the b-known power semiconductor components in an encapsulated construction, there is also the advantage of a strong reduction in capsule volume and capsule weight.
  • Claims 3 and 4 are directed to advantageous refinements and developments of the invention.
  • the semiconductor body 1 shows a large-area semiconductor diode with a disk-shaped semiconductor body 1 made of doped semiconductor material, e.g. Silicon, shown, which contains a planar pn junction 2.
  • the semiconductor region lying below the pn junction 2 is n-conducting, while the semiconductor region is p-conducting above 2.
  • the semiconductor body 1 is connected on its cathode-side main surface 3 to a substrate wafer 4, which consists for example of molybdenum.
  • a substrate disk 5, preferably also made of molybdenum, is attached to its anode-side main surface 6.
  • parts 1, 4 and 5 are connected by the known methods of low-temperature connection technology, known as pressure sintering or diffusion welding. Pressure sintering is explained in more detail with reference to FIG. 2.
  • the substrate wafers 4 and 5 are either galvanized on their surfaces to be connected to the semiconductor body 1 or on all sides provided applied contact layers 7 and 8, which are about 2 to 3 microns thick and consist of silver, for example.
  • the upper side and the lower side of the semiconductor body 1 are each coated with a layer sequence consisting, for example, of an approximately 1 ⁇ m thick Al layer, an approximately 100 nm thick titanium layer applied thereon, and an approximately 500 nm thick middle layer Nickel or platinum, and finally there is a covering, about 200 nm thick silver layer.
  • a layer sequence consisting, for example, of an approximately 1 ⁇ m thick Al layer, an approximately 100 nm thick titanium layer applied thereon, and an approximately 500 nm thick middle layer Nickel or platinum, and finally there is a covering, about 200 nm thick silver layer.
  • a paste 11 and 12 is applied in layers on the contacting layers 7 and 8, with a layer thickness of approximately 10 to 100 ⁇ m, preferably approximately 20 ⁇ m.
  • Silver powder with platelet-shaped powder particles, which is suspended in cyclohexanol as a solvent, is used as the starting material for the production of paste 11, 12.
  • the paste thus produced is then degassed in vacuo in order to avoid the formation of voids during drying.
  • the semiconductor body 1 with its contacting layer 9 is placed on the upper side of the substrate wafer 4 covered by the paste 11 and the substrate wafer 5 with its underside covered by the paste 12 is placed on the contacting layer 10 of the semiconductor body 1 and the whole made of parts 1, 4 and 5 brought to a sintering temperature of 230 ° C, for example.
  • a pressure of at least 900 N / cm is exerted on the arrangement 1, 4, 5 during a sintering time of approximately one minute.
  • an adequate connection of the parts mentioned is achieved even with sintering times of a few seconds and that the pressure can also be increased to 1 to 2 t / cm.
  • the sintering temperature can be in a range which has a lower limit value of approximately 150 ° C. and an upper limit value of approximately 250 ° C. It should also be emphasized that pressure sintering is carried out in a normal atmosphere, ie it is not necessary to use protective gas.
  • the substrate wafers 4 and 5 according to FIG. 2 are provided with contact layers 7 and 8, while noble metal contacting layers 9 and 10, which preferably consist of gold or silver, are applied to the underside and the top of the semiconductor body 1.
  • noble metal contacting layers 9 and 10 which preferably consist of gold or silver
  • metallic intermediate layers for. B. from Al, Ag, Cu or Au, with a layer thickness of about 10 to 20 microns. These intermediate layers are plastically deformable in order to compensate for the roughness depths of the surfaces to be joined together. If the intermediate layers consist of noble metal, the contacting layers 9 and 10 can also be omitted, since in this case they are replaced by the intermediate layers.
  • the parts 1, 4 and 5 coated in this way are now placed on top of one another in such a way that the underside of the semiconductor body 1 touches the contacting layer 7 of the substrate wafer 4 and the top of 1 of the contacting layer 8 of the substrate wafer 5 rests.
  • Parts 1, 4 and 5 are then brought to a temperature which is approximately in the range from 150 to 250 ° C., that is to say in a moderate temperature range which is comparable to the operating temperature of a power semiconductor.
  • These parts are pressed together with a contact pressure of about 500 to 2500 kp / cm or more during a diffusion time of a few minutes. Sufficient results are achieved even with diffusion times of just a few seconds. On the other hand, the pressure can be increased to over 2.5 t / cm.
  • Diffusion welding is also expediently carried out in a normal atmosphere without the use of a protective gas.
  • connection methods described above can be used to first connect parts 1 and 4, and then another Process follows in order to connect the resulting arrangement 1, 4 to the substrate wafer 5.
  • the interconnected parts 1, 4 and 5 are then connected with e.g. made of curable plastic provided plastic jacket 13 ( Figure 1), which connects the edges of the substrate disks 4 and 5 with each other and 14 and 15 encloses them slightly laterally.
  • the substrate disks 4 and 5 form the conductive outer walls of a housing surrounding the semiconductor component, which is supplemented by the plastic jacket 13 to such an extent that it is completely sealed off from the outside.
  • the electrical and thermal properties of the component are considerably improved compared to conventional components of a comparable type, the volume and weight of the housing or the capsule being considerably reduced.
  • the thermal expansion coefficient of the substrate wafers 4 and 5 and the connection temperature in such a way that mechanical stresses which destroy the component cannot occur between the lowest operating temperature and the connection temperature.
  • the exemplary embodiment according to FIG. 3 is not part of the claimed invention and shows a pot-shaped housing for a power semiconductor component 1, which, as already described, is connected to two substrate wafers 4 and 5.
  • 16 designates a metallic housing base which has a bulging edge 16a and is connected to the underside of the substrate wafer 4.
  • a metallic housing cover 17, which is also a bulging edge 17a is connected to the substrate wafer 5, wherein a low-temperature connection method can also be used for this.
  • all connections between parts 1, 4, 5, 16 and 17 are made in one and the same operation.
  • the height of the housing shell is dimensioned so large that the required security against overvoltages on the anode-cathode path of the component is guaranteed.
  • Figure 4 shows an embodiment of the invention, which is used in a boiling-cooled system.
  • This essentially consists of a closed container 19 which is partially filled with a liquid, electrically insulating medium 20.
  • Freon for example, is suitable for this.
  • the disk-shaped semiconductor body 1 forms a structural unit with the substrate wafers 4 and 5, which are materially connected to it in the manner described, which is arranged in the container 19 such that it is surrounded by the medium 20.
  • the insulating medium 20 thus takes over the function of the plastic jacket 13 present in FIG. 1 and supplements the parts 1, 4 and 5 to form a system which is closed to the outside and is protected against harmful environmental influences.
  • the electrical wiring of the power semiconductor component 1, 4, 5 takes place via two pressure contact pieces 21 and 22, which are each in contact with the substrate disks 4 and 5 and are pressed against one another with a sufficient contact pressure, which is indicated in FIG. 4 by a compression spring 23.
  • An electrically insulating disc 24 prevents the generally metallic container 19 from short-circuiting the pressure contact pieces 21 and 22.
  • the pressure contact pieces 21 and 22 are each connected to electrical feed lines 25 and 26, which are guided to the outside in an isolated manner by the wall of the container 19.
  • FIG. 4 a plurality of structural units, each consisting of parts 1, 4, 5, can also be stacked and arranged between the contact pieces 21 and 22.
  • FIG. 5 shows an embodiment of the exemplary embodiment according to FIG. 1, in which a cooling element 29 is materially connected to the substrate wafer 4 by pressure sintering or diffusion welding, this connection preferably being made simultaneously with the other connections.
  • the cooling element 29 is provided with bores 30 which run approximately parallel to the semiconductor wafer 1 and through which a coolant flows in a manner known per se for better heat dissipation.
  • a further embodiment of the exemplary embodiment according to FIG. 1 shown in FIG. 6 consists in that the substrate wafer 4 ′ connected to the underside of the semiconductor body 1 itself is designed as a cooling element. In this case, it is expediently provided with bores 31 through which a coolant is pumped.
  • 1 represents the semiconductor body of a controllable power semiconductor component, for example a thyristor, which has a control electrode 32.
  • a control line 33 the connection of which is designated 34.
  • the parts 32 and 33 are arranged in a recess 35 in the substrate wafer 5, an extension 13a of the plastic jacket 13 expediently filling the recess 35 such that it controls the control line 33 with respect to the substrate wafer 5 and with respect to the main surface 6 of the semiconductor body 1 electrically isolated outside the control electrode 32.
  • a light guide can also be provided in a light-ignitable thyristor, which runs to a light-sensitive region of the semiconductor body 1 provided instead of the control electrode 32.
  • FIG. 8 shows part of a thyristor designed according to the invention, the semiconductor body 1 of which contains an n-emitter 36, a p-base 37 and an n-base 38.
  • the lower part of FIG. 1, which contains the p-emitter, has been omitted for the sake of clarity.
  • a fingered control electrode 39 is provided here, which contacts the p base 37 and is connected to a contact 41 on the edge, separated from the semiconductor body 1 by an electrically insulating layer 40. This in turn is connected to a control line 42, which is guided through the plastic jacket 13 to the outside.
  • the first metallization, e.g. made of aluminum, belonging parts 39 and 41 are covered by an insulating intermediate layer 43.
  • a second metallization 44 e.g. made of aluminum, which contacts the n-emitter 36 in contact holes 45 of the intermediate layer 43 and is connected to the substrate wafer 5.
  • the connection is also made using a low temperature connection method as described above.
  • Such a two-layer metallization 39 and 44 in conjunction with an edge-side contact 41 enables electrical control of certain semiconductor regions in the main surface 6 of the semiconductor body 1 even without the recess 35 of the substrate wafer 5 indicated in FIG. 7.
  • disk-shaped semiconductor components such as transistors or four-layer diodes
  • substrate disks can be materially connected to substrate disks and then surrounded with a plastic or ceramic jacket or arranged in a boiling-cooled system.
  • the material connection of the surfaces of the individual component parts through which the load current flows leads to a significant improvement in the thermal and electrical properties of the components.

Description

Die Erfindung bezieht sich auf ein Leistungshalbleiterbauelement. Ein Bauelement dieser Art ist aus der FR-A-2 090 206 bekannt, wobei das Bauelement einen Halbleiterkörper aufweist, der an beiden Hauptflächen jeweils durch Weichlöten mit einer oberen und einer unteren Substratscheibe verbunden ist und das einen Kunststoffring aufweist, der die Substratscheiben und den Halbleiterkörper vandseitig umschießt.The invention relates to a power semiconductor component. A component of this type is known from FR-A-2 090 206, the component having a semiconductor body which is connected on both main surfaces by soft soldering to an upper and a lower substrate wafer and which has a plastic ring which the substrate wafers and the Surrounds semiconductor body on the vand side.

Ein Bauelement dieser Art ist aus der EP-A-0 242 626 bekannt. Üblicherweise werden solche Bauelemente in ein gasdichtes Gehäuse eingebaut, um sie vor mechanischen Beschädigungen und schädlichen Umwelteinflüssen zu schützen. Dabei müssen sowohl der elektrische Widerstand der entstehenden Anordnung als auch deren thermischer Widerstand möglichst klein gehalten werden, um einen verlustarmen Betrieb und eine effektive Kühlung des Bauelements zu gewährleisten. Der Erfindung liegt die Aufgabe zugrunde, ein Leistungshalbleiterbauelement der eingangs genannten Art anzugeben, dessen elektrische und thermische Eigenschaften gegenüber den herkömmlichen Bauelementen dieser Art verbessert sind. Das wird erfindungsgemäß durch eine Ausbildung nach den Patentansprüchen 1 oder 2 erreicht.A component of this type is known from EP-A-0 242 626. Such components are usually installed in a gas-tight housing in order to protect them from mechanical damage and harmful environmental influences. Both the electrical resistance of the resulting arrangement and its thermal resistance must be kept as low as possible in order to ensure low-loss operation and effective cooling of the component. The invention has for its object to provide a power semiconductor device of the type mentioned, the electrical and thermal properties are improved compared to the conventional components of this type. This is achieved according to the invention by training according to claims 1 or 2.

Der mit der Erfindung erzielbare Vorteil liegt insbesondere darin, daß die einzelnen Teile des Bauelements an ihren vom Laststrom durchflossenen miteinander zu verbindenden Flächen durch Drucksintern oder Diffusionsschweißen materialschlüssig zusammengefügt sind. Vergleicht man die gekapselten Ausführungsformen des Leistungshalbleiterbauelements nach der Erfindung mit den b-ekannten Leistungshalbleiterbauelementen in gekapselter Bauweise, so ergibt sich weiterhin der Vorteil einer starken Reduzierung von Kapsel-volumen und Kapselgewicht.The advantage that can be achieved with the invention is, in particular, that the individual parts of the component are joined together in a material-locking manner by pressure sintering or diffusion welding on their surfaces through which the load current flows. If one compares the encapsulated embodiments of the power semiconductor component according to the invention with the b-known power semiconductor components in an encapsulated construction, there is also the advantage of a strong reduction in capsule volume and capsule weight.

Die Ansprüche 3 und 4 sind auf vorteilhafte Ausgestaltungen und Weiterbildungen der Erfindung gerichtet.Claims 3 and 4 are directed to advantageous refinements and developments of the invention.

Die Erfindung wird nachfolgend anhand einiger, in der Zeichnung dargestellter Ausführungsbeispiele näher erläutert. Dabei zeigen:

Figur 1
ein erstes Ausführungsbeispiel mit einer flachen Gehäuseform,
Figur 2
eine Darstellung zur Erläuterung von Niedertemperaturverbindungsverfahren,
Figur 3
ein zweites Ausführungsbeispiel mit einer topfartigen Gehäuseform,
Figur 4
ein drittes Ausführungsbeispiel für eine siedegekühlte Anlage, die
Figuren 5 und 6
vorteilhafte Ausgestaltungen des ersten Ausführungsbeispiels und die
Figuren 7 und 8
zwei weitere Ausführungsbeispiele, bei denen das Leistungshalbleiterbauelement steuerbar ausgebildet ist.
The invention is explained in more detail below with the aid of some exemplary embodiments shown in the drawing. Show:
Figure 1
a first embodiment with a flat housing shape,
Figure 2
a diagram for explaining low-temperature connection methods,
Figure 3
a second embodiment with a pot-like housing shape,
Figure 4
a third embodiment of a boiling-cooled system, the
Figures 5 and 6
advantageous embodiments of the first embodiment and the
Figures 7 and 8
two further exemplary embodiments in which the power semiconductor component is designed to be controllable.

In Figur 1 ist eine großflächige Halbleiterdiode mit einem scheibenförmigen Halbleiterkörper 1 aus dotiertem Halbleitermaterial, z.B. Silizium, dargestellt, der einen planaren pn-Übergang 2 enthält. Das unterhalb des pn-Übergangs 2 liegende Halbleitergebiet ist dabei n-leitend, während das Halbleitergebiet oberhalb von 2 p-leitend ist. Der Halbleiterkörper 1 ist an seiner kathodenseitigen Hauptfläche 3 mit einer Substratscheibe 4 verbunden, die beispielsweise aus Molybdän besteht. Weiterhin ist eine vorzugsweise ebenfalls aus Molybdän bestehende Substratscheibe 5 an seiner anodenseitigen Hauptfläche 6 angefügt.1 shows a large-area semiconductor diode with a disk-shaped semiconductor body 1 made of doped semiconductor material, e.g. Silicon, shown, which contains a planar pn junction 2. The semiconductor region lying below the pn junction 2 is n-conducting, while the semiconductor region is p-conducting above 2. The semiconductor body 1 is connected on its cathode-side main surface 3 to a substrate wafer 4, which consists for example of molybdenum. Furthermore, a substrate disk 5, preferably also made of molybdenum, is attached to its anode-side main surface 6.

Die Verbindung der Teile 1, 4 und 5 erfolgt wie bereits erwähnt nach denen an sich bekannten, als Drucksintern bzw. Diffusionsschweißen bezeichneten Verfahren der Niedertemperaturverbindungstechnik. Das Drucksintern wird anhand von Figur 2 näher erläutert. Dabei werden die Substratscheiben 4 und 5 entweder an ihren mit dem Halbleiterkörper 1 zu verbindenden Oberflächen oder auch allseitig mit galvanisch aufgetragenen Kontaktschichten 7 bzw. 8 versehen, die etwa 2 bis 3 µm dick sind und z.B. aus Silber bestehen. Die Oberseite und die Unterseite des Halbleiterkörpers 1 werden jeweils mit einer Schichtfolge überzogen, die aus einer etwa 1 µm starken Al-Schicht, einer auf dieser aufgetragenen, etwa 100 nm dicken Titanschicht, einer über dieser liegenden, etwa 500 nm dicken Mittelschicht, z.B. aus Nickel oder Platin, und schließlich einer diese abdeckenden, etwa 200 nm starken Silberschicht besteht. In Figur 2 sind lediglich die als Kontaktierungsschichten dienenden Silberschichten dargestellt und mit 9 und 10 bezeichnet. Anschließend wird auf den Kontaktierungsschichten 7 und 8 jeweils eine Paste 11 und 12 schichtförmig, und zwar mit einer Schichtdicke von etwa 10 bis 100 µm, vorzugsweise etwa 20 µm, aufgetragen. Als Ausgangsstoff für die Herstellung der Paste 11, 12 wird Silberpulver mit plättchenförmigen Pulverpartikeln verwendet, das in Cyclohexanol als Lösungsmittel suspendiert wird. Anschließend wird die so hergestellte Paste im Vakuum entgast, um beim Trocknen eine Lunkerbildung zu vermeiden.As already mentioned, parts 1, 4 and 5 are connected by the known methods of low-temperature connection technology, known as pressure sintering or diffusion welding. Pressure sintering is explained in more detail with reference to FIG. 2. The substrate wafers 4 and 5 are either galvanized on their surfaces to be connected to the semiconductor body 1 or on all sides provided applied contact layers 7 and 8, which are about 2 to 3 microns thick and consist of silver, for example. The upper side and the lower side of the semiconductor body 1 are each coated with a layer sequence consisting, for example, of an approximately 1 μm thick Al layer, an approximately 100 nm thick titanium layer applied thereon, and an approximately 500 nm thick middle layer Nickel or platinum, and finally there is a covering, about 200 nm thick silver layer. In FIG. 2 only the silver layers serving as contacting layers are shown and designated 9 and 10. Then a paste 11 and 12 is applied in layers on the contacting layers 7 and 8, with a layer thickness of approximately 10 to 100 μm, preferably approximately 20 μm. Silver powder with platelet-shaped powder particles, which is suspended in cyclohexanol as a solvent, is used as the starting material for the production of paste 11, 12. The paste thus produced is then degassed in vacuo in order to avoid the formation of voids during drying.

Nach dem Trocknen der Pasten 11 und 12 werden der Halbleiterkörper 1 mit seiner Kontaktierungsschicht 9 auf die von der Paste 11 bedeckte Oberseite der Substratscheibe 4 und die Substratscheibe 5 mit ihrer von der Paste 12 bedeckten Unterseite auf die Kontaktierungsschicht 10 des Halbleiterkörpers 1 aufgesetzt und die gesamte aus den Teilen 1, 4 und 5 bestehende Anordnung auf eine Sintertemperatur von z.B. 230°C gebracht. Bei dieser Temperatur wird auf die Anordnung 1, 4, 5 während einer Sinterzeit von etwa einer Minute ein Druck von mindestens von 900 N/cm ausgeübt. Es ist jedoch darauf hinzuweisen, daß bereits bei Sinterzeiten von einigen Sekunden eine ausreichende Verbindung der genannten Teile erreicht wird und daß der Druck auch auf 1 bis 2 t/cm gesteigert werden kann. Die Sintertemperatur kann in einem Bereich liegen, der einen unteren Grenzwert von etwa 150°C und einen oberen Grenzwert von etwa 250°C aufweist. Weiterhin ist hervorzuheben, daß das Drucksintern in normaler Atmosphäre vorgenommen wird, d.h. eine Anwendung von Schutzgas nicht erforderlich ist.After the pastes 11 and 12 have dried, the semiconductor body 1 with its contacting layer 9 is placed on the upper side of the substrate wafer 4 covered by the paste 11 and the substrate wafer 5 with its underside covered by the paste 12 is placed on the contacting layer 10 of the semiconductor body 1 and the whole made of parts 1, 4 and 5 brought to a sintering temperature of 230 ° C, for example. At this temperature, a pressure of at least 900 N / cm is exerted on the arrangement 1, 4, 5 during a sintering time of approximately one minute. However, it should be pointed out that an adequate connection of the parts mentioned is achieved even with sintering times of a few seconds and that the pressure can also be increased to 1 to 2 t / cm. The sintering temperature can be in a range which has a lower limit value of approximately 150 ° C. and an upper limit value of approximately 250 ° C. It should also be emphasized that pressure sintering is carried out in a normal atmosphere, ie it is not necessary to use protective gas.

Ein weiteres, für die Verbindung der Teile 1, 4 und 5 geeignetes Verfahren der Niedertemperaturverbindungstechnik ist das Diffusionsschweißen. Dabei werden die Substratscheiben 4 und 5 gemäß Figur 2 mit Kontaktschichten 7 und 8 versehen, während auf die Unterseite und die Oberseite des Halbleiterkörpers 1 Edelmetall-Kontaktierungsschichten 9 und 10 aufgebracht werden, die vorzugsweise aus Gold oder Silber bestehen. Es ist vorteilhaft, unter den Kontaktierungsschichten 9 und 10 noch metallische Zwischenschichten, z. B. aus Al, Ag, Cu oder Au, mit einer Schichtdicke von etwa 10 bis 20 µm vorzusehen. Diese Zwischenschichten sind plastisch verformbar, um die Rauhtiefen der miteinander zu verbindenden Flächen auszugleichen. Falls die Zwischenschichten aus Edelmetall bestehen, können die Kontaktierungsschichten 9 und 10 auch entfallen, da sie in diesem Fall durch die Zwischenschichten ersetzt werden. Die in dieser Weise beschichteten Teile 1, 4 und 5 werden nun so aufeinander gesetzt, daß die Unterseite des Halbleiterköpers 1 die Kontaktierungsschicht 7 der Substratscheibe 4 berührt und die Oberseite von 1 der Kontaktierungsschicht 8 der Substratscheibe 5 anliegt. Anschließend werden die Teile 1, 4 und 5 auf eine Temperatur gebracht, die etwa im Bereich von 150 bis 250°C liegt, also in einem gemäßigten Temperaturbereich, der mit der Betriebstemperatur eines Leistungshalbleiters vergleichbar ist. Dabei werden diese Teile mit einem Anpreßdruck von etwa 500 bis 2500 kp/cm oder darüber während einer Diffusionszeit von einigen Minuten zusammengepreßt. Aber auch bei Diffusionszeiten von nur wenigen Sekunden werden schon ausreichende Ergebnisse erzielt. Andererseits kann der Druck auf über 2,5 t/cm gesteigert werden. Auch das Diffusionsschweißen erfolgt zweckmäßigerweise in einer normalen Atmosphäre ohne die Anwendung eines Schutzgases.Another method of connecting the parts 1, 4 and 5 that is suitable for low-temperature connection technology is diffusion welding. The substrate wafers 4 and 5 according to FIG. 2 are provided with contact layers 7 and 8, while noble metal contacting layers 9 and 10, which preferably consist of gold or silver, are applied to the underside and the top of the semiconductor body 1. It is advantageous, under the contacting layers 9 and 10, metallic intermediate layers, for. B. from Al, Ag, Cu or Au, with a layer thickness of about 10 to 20 microns. These intermediate layers are plastically deformable in order to compensate for the roughness depths of the surfaces to be joined together. If the intermediate layers consist of noble metal, the contacting layers 9 and 10 can also be omitted, since in this case they are replaced by the intermediate layers. The parts 1, 4 and 5 coated in this way are now placed on top of one another in such a way that the underside of the semiconductor body 1 touches the contacting layer 7 of the substrate wafer 4 and the top of 1 of the contacting layer 8 of the substrate wafer 5 rests. Parts 1, 4 and 5 are then brought to a temperature which is approximately in the range from 150 to 250 ° C., that is to say in a moderate temperature range which is comparable to the operating temperature of a power semiconductor. These parts are pressed together with a contact pressure of about 500 to 2500 kp / cm or more during a diffusion time of a few minutes. Sufficient results are achieved even with diffusion times of just a few seconds. On the other hand, the pressure can be increased to over 2.5 t / cm. Diffusion welding is also expediently carried out in a normal atmosphere without the use of a protective gas.

Jedes der vorstehend beschriebenen Verbindungsverfahren kann dazu benutzt werden, um zunächst eine Verbindung der Teile 1 und 4 herzustellen, wobei sich dann ein weiteres solches Verfahren anschließt, um die entstandene Anordnung 1, 4 mit der Substratscheibe 5 zu verbinden.Each of the connection methods described above can be used to first connect parts 1 and 4, and then another Process follows in order to connect the resulting arrangement 1, 4 to the substrate wafer 5.

Die miteinander verbundenen Teile 1, 4 und 5 werden anschliessend mit einem z.B. aus aushärtbarem Kunststoff bestehenden Kunststoffmantel 13 (Figur 1) versehen, der die Ränder der Substratscheiben 4 und 5 miteinander verbindet und sie bei 14 und 15 geringfügig seitlich umschließt. Die Substratscheiben 4 und 5 bilden die leitenden Außenwände eines das Halbleiterbauelement umgebenden Gehäuses, das durch den Kunststoffmantel 13 so weit ergänzt wird, daß es nach außen vollständig abgeschlossen ist. Die elektrischen und thermischen Eigenschaften des Bauelements werden gegenüber den herkömmlichen Bauelementen vergleichbarer Art erheblich verbessert, wobei Volumen und Gewicht des Gehäuses bzw. der Kapsel erheblich reduziert werden.The interconnected parts 1, 4 and 5 are then connected with e.g. made of curable plastic provided plastic jacket 13 (Figure 1), which connects the edges of the substrate disks 4 and 5 with each other and 14 and 15 encloses them slightly laterally. The substrate disks 4 and 5 form the conductive outer walls of a housing surrounding the semiconductor component, which is supplemented by the plastic jacket 13 to such an extent that it is completely sealed off from the outside. The electrical and thermal properties of the component are considerably improved compared to conventional components of a comparable type, the volume and weight of the housing or the capsule being considerably reduced.

Für ein nach der Erfindung ausgebildetes Leistungshalbleiterbauelement ist es vorteilhaft, den thermischen Ausdehnungskoeffizienten der Substratscheiben 4 und 5 sowie die Verbindungstemperatur so einzustellen, daß zwischen der niedrigsten Betriebstemperatur und der Verbindungstemperatur keine das Bauelement zerstörenden mechanischen Spannungen auftreten können. Durch die Anwendung der erwähnten Verfahren der Niedertemperaturverbindungstechnik und durch eine geeignete Wahl des Substratmaterials, das z.B. aus Mo, W oder einem Cu/Mo-Sinter-werkstoff bestehen kann, wird dies erreicht.For a power semiconductor component designed according to the invention, it is advantageous to set the thermal expansion coefficient of the substrate wafers 4 and 5 and the connection temperature in such a way that mechanical stresses which destroy the component cannot occur between the lowest operating temperature and the connection temperature. By using the mentioned methods of low temperature connection technology and by a suitable choice of the substrate material, e.g. can be made of Mo, W or a Cu / Mo sintered material, this is achieved.

Das Ausführungsbeispiel nach Figur 3 ist nicht Bestandteil der beanspruchten Erfindung und zeigt ein topfartig geformtes Gehäuse für ein Leistungshalbleiterbauelement 1, das, wie bereits beschrieben, mit zwei Substratscheiben 4 und 5 verbunden ist. Mit 16 ist ein metallischer Gehäuseboden bezeichnet, der einen vorgewölbten Rand 16a aufweist und mit der Unterseite der Substratscheibe 4 verbunden ist. Zur Herstellung dieser Verbindung kann zweckmäßigerweise eines der erwähnten Niedertemperaturverbindungsverfahren herangezogen werden. Ein metallischer Gehäusedeckel 17, der ebenfalls einen vorgewölbten Rand 17a hat, ist mit der Substratscheibe 5 verbunden, wobei auch hierzu ein Niedertemperaturverbindungsverfahren verwendet werden kann. Mit besonderem Vorteil werden alle Verbindungen zwischen den Teilen 1, 4, 5, 16 und 17 in ein und demselben Arbeitsgang hergestellt. Zwischen den einander gegenüberstehenden Rändern 16a und 17a ist ein elektrisch isolierender, hohlzylinderförmiger Gehäusemantel 18, z.B. aus Keramik, angeordnet. Die Höhe des Gehäusemantels wird so groß bemessen, daß die erforderliche Sicherheit gegen Überspannungen an der Anoden-Kathoden-Strecke des Bauelements gewährleistet ist.The exemplary embodiment according to FIG. 3 is not part of the claimed invention and shows a pot-shaped housing for a power semiconductor component 1, which, as already described, is connected to two substrate wafers 4 and 5. 16 designates a metallic housing base which has a bulging edge 16a and is connected to the underside of the substrate wafer 4. One of the mentioned low-temperature connection methods can expediently be used to produce this connection. A metallic housing cover 17, which is also a bulging edge 17a is connected to the substrate wafer 5, wherein a low-temperature connection method can also be used for this. With particular advantage, all connections between parts 1, 4, 5, 16 and 17 are made in one and the same operation. An electrically insulating, hollow cylindrical housing jacket 18, for example made of ceramic, is arranged between the opposing edges 16a and 17a. The height of the housing shell is dimensioned so large that the required security against overvoltages on the anode-cathode path of the component is guaranteed.

Figur 4 zeigt ein Ausführungsbeispiel der Erfindung, das in einer siedegekühlten Anlage eingesetzt ist. Diese besteht im wesentlichen aus einem geschlossenen Behälter 19, der teilweise mit einem flüssigen, elektrischen isolierenden Medium 20 gefüllt ist. Hierfür eignet sich beispielsweise Freon. Der scheibenförmige Halbleiterkörper 1 bildet mit den Substratscheiben 4 und 5, die mit ihm in der beschriebenen Weise materialschlüssig verbunden sind, eine bauliche Einheit, die im Behälter 19 derart angeordnet ist, daß sie vom Medium 20 umgeben ist. Damit übernimmtdas isolierende Medium 20 die Funktion des in Figur 1 vorhandenen, Kunststoffmantels 13 und ergänzt die Teile 1, 4 und 5 zu einem nach außen abgeschlossenen, gegen schädliche Umwelteinflüsse geschützten System. Die elektrische Beschaltung des Leistungshalbleiterbauelements 1, 4, 5 erfolgt über zwei Druckkontaktstücke 21 und 22, die jeweils mit den Substratscheiben 4 und 5 in Kontakt stehen und mit einem hinreichenden Kontaktdruck gegeneinandergepreßt werden, was in Figur 4 durch eine Druckfeder 23 angedeutet wird. Eine elektrisch isolierende Scheibe 24 verhindert, daß der im allgemeinen metallische Behälter 19 die Druckkontaktstücke 21 und 22 kurzschließt. Die Druckkontaktstücke 21 und 22 sind jeweils mit elektrischen Zuleitungen 25 und 26 verbunden, die durch die Wandung des Behälters 19 isoliert nach außen geführt sind. Stellen die Teile 1, 4 und 5 wie beschrieben eine Diode dar, so bilden die Anschlüsse 27 und 28 der Zuleitungen 25 und 26 jeweils den kathodenseitigen und anodenseitigen Diodenanschluß. Das in Figur 4 angewandte Kühlungs-prinzip sieht vor, daß die von dem Halbleiterkörper 1 im Betrieb desselben an das Medium 20 abgegebene Wärme dazu führt, daß das letztere teilweise verdampft, wobei die im oberen Teil des Behälters 19 vorhandenen gasförmigen Teile des Mediums 20 an der von außen gekühlten Wandung des Behälters 19 kondensieren und wieder zum unteren Teil von 19 zurückfließen.Figure 4 shows an embodiment of the invention, which is used in a boiling-cooled system. This essentially consists of a closed container 19 which is partially filled with a liquid, electrically insulating medium 20. Freon, for example, is suitable for this. The disk-shaped semiconductor body 1 forms a structural unit with the substrate wafers 4 and 5, which are materially connected to it in the manner described, which is arranged in the container 19 such that it is surrounded by the medium 20. The insulating medium 20 thus takes over the function of the plastic jacket 13 present in FIG. 1 and supplements the parts 1, 4 and 5 to form a system which is closed to the outside and is protected against harmful environmental influences. The electrical wiring of the power semiconductor component 1, 4, 5 takes place via two pressure contact pieces 21 and 22, which are each in contact with the substrate disks 4 and 5 and are pressed against one another with a sufficient contact pressure, which is indicated in FIG. 4 by a compression spring 23. An electrically insulating disc 24 prevents the generally metallic container 19 from short-circuiting the pressure contact pieces 21 and 22. The pressure contact pieces 21 and 22 are each connected to electrical feed lines 25 and 26, which are guided to the outside in an isolated manner by the wall of the container 19. Represent parts 1, 4 and 5 as described as a diode, so form the connections 27 and 28 of the leads 25 and 26 each the cathode-side and anode-side diode connection. The cooling principle used in FIG. 4 provides that the heat given off by the semiconductor body 1 to the medium 20 during operation of the latter leads to the latter partially evaporating, the gaseous parts of the medium 20 present in the upper part of the container 19 the externally cooled wall of the container 19 condense and flow back to the lower part of 19.

In Figur 4 können auch mehrere, jeweils aus den Teilen 1, 4, 5 bestehende, bauliche Einheiten gestapelt und zwischen den Kontaktstücken 21 und 22 angeordnet werden.In FIG. 4, a plurality of structural units, each consisting of parts 1, 4, 5, can also be stacked and arranged between the contact pieces 21 and 22.

In Figur 5 ist eine Ausgestaltung des Ausführungsbeispiels nach Figur 1 dargestellt, bei der ein Kühlelement 29 durch Drucksintern oder Diffusionsschweißen materialschlüssig mit der Substratscheibe 4 verbunden ist, wobei diese Verbindung vorzugsweise gleichzeitig mit den übrigen Verbindungen hergestellt wird. Das Kühlelement 29 ist mit etwa parallel zur Halbleiterscheibe 1 verlaufenden Bohrungen 30 versehen, die zur besseren Wärmeableitung in an sich bekannter Weise von einem Kühlmittel durchströmt werden. Eine weitere in Figur 6 gezeigte Ausgestaltung des Ausführungsbeispiels nach Figur 1 besteht darin, daß die mit der Unterseite des Halbleiterkörpers 1 verbundene Substratscheibe 4' selbst als Kühlelement ausgebildet ist. In diesem Fall ist sie zweckmäßig mit Bohrungen 31 versehen, durch die ein Kühlmittel gepumpt wird.FIG. 5 shows an embodiment of the exemplary embodiment according to FIG. 1, in which a cooling element 29 is materially connected to the substrate wafer 4 by pressure sintering or diffusion welding, this connection preferably being made simultaneously with the other connections. The cooling element 29 is provided with bores 30 which run approximately parallel to the semiconductor wafer 1 and through which a coolant flows in a manner known per se for better heat dissipation. A further embodiment of the exemplary embodiment according to FIG. 1 shown in FIG. 6 consists in that the substrate wafer 4 ′ connected to the underside of the semiconductor body 1 itself is designed as a cooling element. In this case, it is expediently provided with bores 31 through which a coolant is pumped.

In Figur 7 stellt 1 den Halbleiterkörper eines steuerbaren Leistungshalbleiterbauelements, z.B. eines Thyristors, dar, der eine Steuerelektrode 32 aufweist. Diese ist mit einer Steuerleitung 33 verbunden, deren Anschluß mit 34 bezeichnet ist. Die Teile 32 und 33 sind in einer Ausnehmung 35 der Substratscheibe 5 angeordnet, wobei ein Ansatz 13a des Kunststoffmantels 13 zweckmäßigerweise die Ausnehmung 35 so ausfüllt, daß er die Steuerleitung 33 gegenüber der Substratscheibe 5 und gegenüber der Hauptfläche 6 des Halbleiterkörpers 1 außerhalb der Steuerelektrode 32 elektrisch isoliert. Anstelle der elektrischen Steuerleitung 33 kann bei einem lichtzündbaren Thyristor auch ein Lichtleiter vorgesehen sein, der zu einem anstelle der Steuerelektrode 32 vorgesehenen, lichtempfindlichen Bereich des Halbleiterkörpers 1 hin verläuft.In FIG. 7, 1 represents the semiconductor body of a controllable power semiconductor component, for example a thyristor, which has a control electrode 32. This is connected to a control line 33, the connection of which is designated 34. The parts 32 and 33 are arranged in a recess 35 in the substrate wafer 5, an extension 13a of the plastic jacket 13 expediently filling the recess 35 such that it controls the control line 33 with respect to the substrate wafer 5 and with respect to the main surface 6 of the semiconductor body 1 electrically isolated outside the control electrode 32. Instead of the electrical control line 33, a light guide can also be provided in a light-ignitable thyristor, which runs to a light-sensitive region of the semiconductor body 1 provided instead of the control electrode 32.

Figur 8 zeigt einen Teil eines nach der Erfindung ausgebildeten Thyristors, dessen Halbleiterkörper 1 einen n-Emitter 36 , eine p-Basis 37 und eine n-Basis 38 enthält. Der untere Teil von 1, der den p-Emitter enthält, wurde aus Gründen einer übersichtlichen Darstellung weggelassen. Hier ist eine verfingerte Steuerelektrode 39 vorgesehen, die die p-Basis 37 kontaktiert und mit einem randseitigen, durch eine elektrisch isolierende Schicht 40 vom Halbleiterkörper 1 getrennten Kontakt 41 verbunden ist. Dieser ist seinerseits mit einer Steuerleitung 42 verbunden, die durch den Kunststoffmantel 13 nach außen geführt ist. Die zu einer ersten Metallisierung, z.B. aus Aluminium, gehörenden Teile 39 und 41 werden von einer isolierenden Zwischenschicht 43 abgedeckt. Auf der Zwischenschicht 43 ist eine zweite Metallisierung 44, z.B. aus Aluminium, angeordnet, die den n-Emitter 36 jeweils in Kontaktlöchern 45 der Zwischenschicht 43 kontaktiert und mit der Substratscheibe 5 verbunden ist. Auch die Verbindung erfolgt durch Anwendung eines Niedertemperaturverbindungsverfahrens, wie es weiter oben beschrieben wurde. Durch eine solche Zweilagenmetallisierung 39 und 44 in Verbindung mit einem randseitigen Kontakt 41 kann eine elektrische Ansteuerung bestimmter Halbleiterbereiche in der Hauptfläche 6 des Halbleiterkörpers 1 auch ohne die in Figur 7 angedeutete Ausnehmung 35 der Substratscheibe 5 erfolgen.FIG. 8 shows part of a thyristor designed according to the invention, the semiconductor body 1 of which contains an n-emitter 36, a p-base 37 and an n-base 38. The lower part of FIG. 1, which contains the p-emitter, has been omitted for the sake of clarity. A fingered control electrode 39 is provided here, which contacts the p base 37 and is connected to a contact 41 on the edge, separated from the semiconductor body 1 by an electrically insulating layer 40. This in turn is connected to a control line 42, which is guided through the plastic jacket 13 to the outside. The first metallization, e.g. made of aluminum, belonging parts 39 and 41 are covered by an insulating intermediate layer 43. On the intermediate layer 43 there is a second metallization 44, e.g. made of aluminum, which contacts the n-emitter 36 in contact holes 45 of the intermediate layer 43 and is connected to the substrate wafer 5. The connection is also made using a low temperature connection method as described above. Such a two-layer metallization 39 and 44 in conjunction with an edge-side contact 41 enables electrical control of certain semiconductor regions in the main surface 6 of the semiconductor body 1 even without the recess 35 of the substrate wafer 5 indicated in FIG. 7.

Außer den dargestellten können auch andere scheibenförmige Halbleiterbauelemente, wie z.B. Transistoren oder Vierschicht-dioden, mit Substratscheiben materialschlüssig verbunden und sodann mit einem Kunststoff- oder Keramikmantel umgeben oder in einer siedegekühlten Anlage angeordnet werden. In allen diesen Fällen führt die materialschlüssige Verbindung der vom Laststrom durchflossenen Flächen der einzelnen Bauelementeteile zu einer wesentlichen Verbesserung der thermischen und elektrischen Eigenschaften der Bauelemente.In addition to the ones shown, other disk-shaped semiconductor components, such as transistors or four-layer diodes, can be materially connected to substrate disks and then surrounded with a plastic or ceramic jacket or arranged in a boiling-cooled system. In all In these cases, the material connection of the surfaces of the individual component parts through which the load current flows leads to a significant improvement in the thermal and electrical properties of the components.

Claims (4)

  1. Power semiconductor component having a semiconductor body (1) which is in the form of a wafer, is made of doped semiconductor material and is connected, at its first main area (3), to a first substrate wafer (4) by means of pressure sintering or diffusion welding, in which the semiconductor body (1) is connected, at its second main area (3), to a second substrate wafer (5) by means of pressure sintering or diffusion welding, in which the unit (1, 4, 5) comprising the semiconductor body (1) and the substrate wafers is arranged in a closed container (19) of an evaporatively cooled installation, which container is partially filled with a liquid, electrically insulating medium (20), in such a way that the said unit is surrounded by the said medium (20), and in which the unit surrounded by the liquid, electrically insulating medium (20) contains a plurality of semiconductor bodies (1) which are stacked one on the other and are each connected on both sides to substrate wafers (4, 5).
  2. Power semiconductor component having a semiconductor body (1) which is in the form of a wafer, is made of doped semiconductor material and is connected, at its first main area (3), to a first substrate wafer (4') by means of pressure sintering or diffusion welding, in which the semiconductor body (1) is connected, at its second main area (6), to a second substrate wafer (5) by means of pressure sintering or diffusion welding, in which there is provided a plastic sheath (13) which connects the edges of the two substrate wafers (4', 5) to one another and, together with the two substrate wafers (4', 5), forms a housing which completely seals the semiconductor body (1) from the outside, and in which the first substrate wafer (4') itself is designed as a cooling element and is provided with bores (31) which run approximately parallel to the semiconductor wafer and through which coolant flows.
  3. Power semiconductor component according to Claim 1 or 2, characterized in that the semiconductor body (1) has a controllable semiconductor component, the control electrode (2) or light-sensitive region of which is arranged in a recess (35) in the second substrate wafer (5) and is provided with a control line (33) which is arranged in a manner insulated from the semiconductor body (1) and the second substrate wafer (5).
  4. Power semiconductor component according to Claim 1 or 2, characterized in that the semiconductor body (1) has a controllable semiconductor component, the control electrode (39) of which is connected via a first metallization layer to a contact (41) which is arranged on the edge of the semiconductor body (1) and is wired up to a control line (42), and in that a second metallization layer is provided, which makes contact with individual regions (36) of the semiconductor body (1) and is connected to the second substrate wafer (5) by means of pressure sintering or diffusion welding.
EP19910121732 1990-12-19 1991-12-18 Semiconductor power component Expired - Lifetime EP0491389B1 (en)

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DE59107763D1 (en) 1996-06-05
DE4040753A1 (en) 1992-06-25

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