EP0486249B1 - Eprom array - Google Patents
Eprom array Download PDFInfo
- Publication number
- EP0486249B1 EP0486249B1 EP91310406A EP91310406A EP0486249B1 EP 0486249 B1 EP0486249 B1 EP 0486249B1 EP 91310406 A EP91310406 A EP 91310406A EP 91310406 A EP91310406 A EP 91310406A EP 0486249 B1 EP0486249 B1 EP 0486249B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- line
- read
- transistor
- memory
- lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0491—Virtual ground arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Description
- CRL =
- read line segment capacitance
- CBL =
- bit line capacitance
- CWL =
- word line capacitance
- TBL =
- thickness of the bit line oxide
- VRL =
- voltage on the read line
- OB =
- length of bird beak between the field oxide and the transistor channel regions obtained using recessed oxide isolation.
Claims (13)
- A virtual ground EPROM array comprising a plurality of memory cells (Q) connected to a plurality of alternating bit lines (BL) and read lines (RL), wherein the bit lines (BL) are continuous or non-segmented and provide a reference potential to selected memory cells (Q) during a read, the array being characterised in that the read lines (RL) are each broken into a plurality of electrically-isolatable segments.
- An EPROM array as claimed in Claim 1, having a selected number of memory cells (Q) connected between each bit line (BL) and read line (RL).
- An EPROM array as claimed in Claim 1, wherein a multiplicity of the bit lines (BL) alternates with the plurality of read lines (RL) such that each read line (RL) is between two bit lines (BL), and wherein the memory cells comprise a column of memory transistors (Qic) placed between each adjacent bit line (BL) and read line (RL).
- An EPROM array as claimed in Claim 3, having at least one pass or select transistor (Qn) to connect each read line (RL) segment to a corresponding electrical conductor.
- An EPROM array as claimed in Claim 4, having two select transistors (Qn) to connect each read line (RL) segment to the corresponding electrical conductor.
- An EPROM array as claimed in Claim 4 or 5, wherein each electrical conductor comprises a metal line formed over but insulated from the underlying read line (RL), and wherein electrical contacts extend from the metal line through the insulation to one terminal of the or each select transistor (Qn) to allow the metal conductor to be connected to the read line (RL) segment.
- An EPROM array as claimed in Claim 3, wherein a multiplicity of the select transistors (Qn) located in the periphery of the memory array are connected on a one-to-one basis to the multiplicity of bit lines (BL), each select transistor (Qn) being of a size sufficient to allow a programming voltage and current to be applied to the bit line (BL) thereby to allow a selected memory transistor connected to the bit line (BL) to be programmed.
- An EPROM array as claimed in Claim 1, wherein the plurality of memory cells comprisesa plurality P of floating gate or memory transistors (Q) formed in and on a semiconductor substrate, and arranged in rows and columns, where P equals the total number of floating gate transistors in the array, and the plurality of alternating bit lines and read lines comprisesa multiplicity of bit lines BL1, ... Blm, BL(m+1) ... BLM, where M is an integer equal to the maximum number of bit lines and where m, an integer given by O<m<M, represents any one of the bit lines in the array, anda plurality of read lines RL1, ... RLm, RL(m+1), ... RL(M-1) interleaved with the bit lines such that each read line Rlm is placed between bit line Blm and bit line BL(m+1),wherein each of the read lines is formed in the semiconductor substrate and is divided into a plurality of electrically isolatable segments, each segment having two ends.
- An EPROM array as claimed in Claim 8, including a first column of memory transistors (Qic) formed between bit line (BLm) and read line (RLm), and a second column of memory transistors (Qic) formed between read line (RLm) and bit line (BL(m+1)), such that during programming of a given memory transistor (Qic) in one of the two columns of memory transistors (Qic), the bit line connected to the memory transistor acts as the drain and the read line connected to the memory transistor acts as the source and during the readout of information stored in a given cell the read line (RLm) connected to the memory transistor acts as the drain and the bit line connected to the memory transistor acts as the source.
- An EPROM array as claimed in Claim 9, wherein the memory transistors (Qic) in the first column and the memory transistors (Qic) in the second column are arranged symmetrically with respect to the read line (RLm).
- An EPROM array as claimed in Claim 8, 9 or 10, having a metal line formed over but insulated from each of the read line (RL), a plurality of electrical contacts running from each overlying metal line to the underlying read line (RL) between adjacent segments of the read line (RL), and a pass or select transistor (Qn) formed at each end of each segment of the read line thereby to allow the segment to be connected to the contacts between segments and thereby to be connected to the metal line.
- An EPROM array as claimed in any one of Claims 3-11, wherein each memory transistor (Qic) is an asymmetric structure comprising both the floating gate transistor and a control transistor.
- An EPROM array as claimed in any one of Claims 3-11, wherein each memory transistor (Qic) comprises a floating gate transistor.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US61234690A | 1990-11-13 | 1990-11-13 | |
US612346 | 1990-11-13 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0486249A2 EP0486249A2 (en) | 1992-05-20 |
EP0486249A3 EP0486249A3 (en) | 1993-05-19 |
EP0486249B1 true EP0486249B1 (en) | 1998-02-11 |
Family
ID=24452772
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP91310406A Expired - Lifetime EP0486249B1 (en) | 1990-11-13 | 1991-11-12 | Eprom array |
Country Status (4)
Country | Link |
---|---|
US (1) | US5862076A (en) |
EP (1) | EP0486249B1 (en) |
JP (1) | JP3002309B2 (en) |
DE (1) | DE69128909D1 (en) |
Families Citing this family (53)
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EP0851426A3 (en) | 1996-12-27 | 1999-11-24 | STMicroelectronics S.r.l. | Memory block for realizing semiconductor memory devices and corresponding manufacturing process |
US6768165B1 (en) * | 1997-08-01 | 2004-07-27 | Saifun Semiconductors Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
US6011710A (en) * | 1997-10-30 | 2000-01-04 | Hewlett-Packard Company | Capacitance reducing memory system, device and method |
US5963465A (en) * | 1997-12-12 | 1999-10-05 | Saifun Semiconductors, Ltd. | Symmetric segmented memory array architecture |
US6633496B2 (en) | 1997-12-12 | 2003-10-14 | Saifun Semiconductors Ltd. | Symmetric architecture for memory cells having widely spread metal bit lines |
US6430077B1 (en) | 1997-12-12 | 2002-08-06 | Saifun Semiconductors Ltd. | Method for regulating read voltage level at the drain of a cell in a symmetric array |
US6633499B1 (en) | 1997-12-12 | 2003-10-14 | Saifun Semiconductors Ltd. | Method for reducing voltage drops in symmetric array architectures |
US6396741B1 (en) * | 2000-05-04 | 2002-05-28 | Saifun Semiconductors Ltd. | Programming of nonvolatile memory cells |
US6928001B2 (en) * | 2000-12-07 | 2005-08-09 | Saifun Semiconductors Ltd. | Programming and erasing methods for a non-volatile memory cell |
US6614692B2 (en) * | 2001-01-18 | 2003-09-02 | Saifun Semiconductors Ltd. | EEPROM array and method for operation thereof |
US6677805B2 (en) | 2001-04-05 | 2004-01-13 | Saifun Semiconductors Ltd. | Charge pump stage with body effect minimization |
US6584017B2 (en) | 2001-04-05 | 2003-06-24 | Saifun Semiconductors Ltd. | Method for programming a reference cell |
US6636440B2 (en) | 2001-04-25 | 2003-10-21 | Saifun Semiconductors Ltd. | Method for operation of an EEPROM array, including refresh thereof |
KR100416599B1 (en) * | 2001-05-31 | 2004-02-05 | 삼성전자주식회사 | Memory cell structure of metal programmable ROM capable of improving memory density and read speed and reducing power consumption |
US6480422B1 (en) | 2001-06-14 | 2002-11-12 | Multi Level Memory Technology | Contactless flash memory with shared buried diffusion bit line architecture |
US6643181B2 (en) | 2001-10-24 | 2003-11-04 | Saifun Semiconductors Ltd. | Method for erasing a memory cell |
US7098107B2 (en) * | 2001-11-19 | 2006-08-29 | Saifun Semiconductor Ltd. | Protective layer in memory device and method therefor |
US6885585B2 (en) * | 2001-12-20 | 2005-04-26 | Saifun Semiconductors Ltd. | NROM NOR array |
ATE448549T1 (en) * | 2002-01-11 | 2009-11-15 | Texas Instruments Inc | SPATIAL LIGHT MODULATOR WITH CHARGE PUMP PIXEL CELL |
US6975536B2 (en) * | 2002-01-31 | 2005-12-13 | Saifun Semiconductors Ltd. | Mass storage array and methods for operation thereof |
US6700818B2 (en) * | 2002-01-31 | 2004-03-02 | Saifun Semiconductors Ltd. | Method for operating a memory device |
US6914820B1 (en) | 2002-05-06 | 2005-07-05 | Multi Level Memory Technology | Erasing storage nodes in a bi-directional nonvolatile memory cell |
US7221591B1 (en) * | 2002-05-06 | 2007-05-22 | Samsung Electronics Co., Ltd. | Fabricating bi-directional nonvolatile memory cells |
US6747896B2 (en) | 2002-05-06 | 2004-06-08 | Multi Level Memory Technology | Bi-directional floating gate nonvolatile memory |
US6917544B2 (en) * | 2002-07-10 | 2005-07-12 | Saifun Semiconductors Ltd. | Multiple use memory chip |
US6826107B2 (en) * | 2002-08-01 | 2004-11-30 | Saifun Semiconductors Ltd. | High voltage insertion in flash memory cards |
US7136304B2 (en) | 2002-10-29 | 2006-11-14 | Saifun Semiconductor Ltd | Method, system and circuit for programming a non-volatile memory array |
US7178004B2 (en) * | 2003-01-31 | 2007-02-13 | Yan Polansky | Memory array programming circuit and a method for using the circuit |
US7123532B2 (en) * | 2003-09-16 | 2006-10-17 | Saifun Semiconductors Ltd. | Operating array cells with matched reference cells |
US7095655B2 (en) * | 2004-08-12 | 2006-08-22 | Saifun Semiconductors Ltd. | Dynamic matching of signal path and reference path for sensing |
US20060036803A1 (en) * | 2004-08-16 | 2006-02-16 | Mori Edan | Non-volatile memory device controlled by a micro-controller |
US7638850B2 (en) * | 2004-10-14 | 2009-12-29 | Saifun Semiconductors Ltd. | Non-volatile memory structure and method of fabrication |
US20060146624A1 (en) * | 2004-12-02 | 2006-07-06 | Saifun Semiconductors, Ltd. | Current folding sense amplifier |
EP1684307A1 (en) * | 2005-01-19 | 2006-07-26 | Saifun Semiconductors Ltd. | Method, circuit and systems for erasing one or more non-volatile memory cells |
US8053812B2 (en) | 2005-03-17 | 2011-11-08 | Spansion Israel Ltd | Contact in planar NROM technology |
JP2007027760A (en) * | 2005-07-18 | 2007-02-01 | Saifun Semiconductors Ltd | High density nonvolatile memory array and manufacturing method |
US7668017B2 (en) | 2005-08-17 | 2010-02-23 | Saifun Semiconductors Ltd. | Method of erasing non-volatile memory cells |
US20070096199A1 (en) * | 2005-09-08 | 2007-05-03 | Eli Lusky | Method of manufacturing symmetric arrays |
US20070120180A1 (en) * | 2005-11-25 | 2007-05-31 | Boaz Eitan | Transition areas for dense memory arrays |
US7352627B2 (en) * | 2006-01-03 | 2008-04-01 | Saifon Semiconductors Ltd. | Method, system, and circuit for operating a non-volatile memory array |
US7808818B2 (en) * | 2006-01-12 | 2010-10-05 | Saifun Semiconductors Ltd. | Secondary injection for NROM |
US20070173017A1 (en) * | 2006-01-20 | 2007-07-26 | Saifun Semiconductors, Ltd. | Advanced non-volatile memory array and method of fabrication thereof |
US7760554B2 (en) * | 2006-02-21 | 2010-07-20 | Saifun Semiconductors Ltd. | NROM non-volatile memory and mode of operation |
US7692961B2 (en) * | 2006-02-21 | 2010-04-06 | Saifun Semiconductors Ltd. | Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection |
US8253452B2 (en) * | 2006-02-21 | 2012-08-28 | Spansion Israel Ltd | Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same |
US20070255889A1 (en) * | 2006-03-22 | 2007-11-01 | Yoav Yogev | Non-volatile memory device and method of operating the device |
US7701779B2 (en) * | 2006-04-27 | 2010-04-20 | Sajfun Semiconductors Ltd. | Method for programming a reference cell |
US7605579B2 (en) * | 2006-09-18 | 2009-10-20 | Saifun Semiconductors Ltd. | Measuring and controlling current consumption and output current of charge pumps |
US7965551B2 (en) * | 2007-02-07 | 2011-06-21 | Macronix International Co., Ltd. | Method for metal bit line arrangement |
US20080239599A1 (en) * | 2007-04-01 | 2008-10-02 | Yehuda Yizraeli | Clamping Voltage Events Such As ESD |
US8320191B2 (en) | 2007-08-30 | 2012-11-27 | Infineon Technologies Ag | Memory cell arrangement, method for controlling a memory cell, memory array and electronic device |
US7590001B2 (en) | 2007-12-18 | 2009-09-15 | Saifun Semiconductors Ltd. | Flash memory with optimized write sector spares |
JP2010021492A (en) | 2008-07-14 | 2010-01-28 | Toshiba Corp | Nonvolatile semiconductor memory device and its control method |
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US5204835A (en) * | 1990-06-13 | 1993-04-20 | Waferscale Integration Inc. | Eprom virtual ground array |
US5245570A (en) * | 1990-12-21 | 1993-09-14 | Intel Corporation | Floating gate non-volatile memory blocks and select transistors |
US5197029A (en) * | 1991-02-07 | 1993-03-23 | Texas Instruments Incorporated | Common-line connection for integrated memory array |
-
1991
- 1991-11-11 JP JP29464691A patent/JP3002309B2/en not_active Expired - Fee Related
- 1991-11-12 EP EP91310406A patent/EP0486249B1/en not_active Expired - Lifetime
- 1991-11-12 DE DE69128909T patent/DE69128909D1/en not_active Expired - Lifetime
-
1992
- 1992-06-30 US US07/908,595 patent/US5862076A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0758299A (en) | 1995-03-03 |
US5862076A (en) | 1999-01-19 |
EP0486249A2 (en) | 1992-05-20 |
EP0486249A3 (en) | 1993-05-19 |
DE69128909D1 (en) | 1998-03-19 |
JP3002309B2 (en) | 2000-01-24 |
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