EP0456374A3 - Programmable logic device power controller - Google Patents
Programmable logic device power controller Download PDFInfo
- Publication number
- EP0456374A3 EP0456374A3 EP19910303673 EP91303673A EP0456374A3 EP 0456374 A3 EP0456374 A3 EP 0456374A3 EP 19910303673 EP19910303673 EP 19910303673 EP 91303673 A EP91303673 A EP 91303673A EP 0456374 A3 EP0456374 A3 EP 0456374A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- programmable logic
- logic device
- power controller
- device power
- controller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Read Only Memory (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US520673 | 1990-05-08 | ||
US07/520,673 US5247213A (en) | 1990-05-08 | 1990-05-08 | Programmable sense amplifier power reduction |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0456374A2 EP0456374A2 (en) | 1991-11-13 |
EP0456374A3 true EP0456374A3 (en) | 1992-04-15 |
Family
ID=24073610
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19910303673 Ceased EP0456374A3 (en) | 1990-05-08 | 1991-04-24 | Programmable logic device power controller |
Country Status (3)
Country | Link |
---|---|
US (1) | US5247213A (en) |
EP (1) | EP0456374A3 (en) |
JP (1) | JPH05315943A (en) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5396635A (en) * | 1990-06-01 | 1995-03-07 | Vadem Corporation | Power conservation apparatus having multiple power reduction levels dependent upon the activity of the computer system |
JPH0676085A (en) * | 1992-07-03 | 1994-03-18 | Seiko Epson Corp | Semiconductor device provided with wiring switching circuit |
US5315177A (en) * | 1993-03-12 | 1994-05-24 | Micron Semiconductor, Inc. | One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture |
US5450608A (en) * | 1993-04-15 | 1995-09-12 | Intel Corporation | Programmable logic having selectable output states for initialization and resets asynchronously using control bit associated with each product term |
JP3080830B2 (en) * | 1994-02-28 | 2000-08-28 | 株式会社東芝 | Semiconductor integrated circuit |
US5563527A (en) * | 1995-04-21 | 1996-10-08 | Xilinx, Inc. | Power-managed sense amplifier for programmable logic device |
US5565791A (en) * | 1995-07-07 | 1996-10-15 | Cypress Semiconductor Corporation | Method and apparatus for disabling unused sense amplifiers |
US7552350B2 (en) | 2000-09-27 | 2009-06-23 | Huron Ip Llc | System and method for activity or event base dynamic energy conserving server reconfiguration |
US7032119B2 (en) | 2000-09-27 | 2006-04-18 | Amphus, Inc. | Dynamic power and workload management for multi-server system |
USRE40866E1 (en) | 2000-09-27 | 2009-08-04 | Huron Ip Llc | System, method, and architecture for dynamic server power management and dynamic workload management for multiserver environment |
US7822967B2 (en) * | 2000-09-27 | 2010-10-26 | Huron Ip Llc | Apparatus, architecture, and method for integrated modular server system providing dynamically power-managed and work-load managed network devices |
US7228441B2 (en) | 2000-09-27 | 2007-06-05 | Huron Ip Llc | Multi-server and multi-CPU power management system and method |
US20030196126A1 (en) | 2002-04-11 | 2003-10-16 | Fung Henry T. | System, method, and architecture for dynamic server power management and dynamic workload management for multi-server environment |
US20060248360A1 (en) * | 2001-05-18 | 2006-11-02 | Fung Henry T | Multi-server and multi-CPU power management system and method |
US6617874B2 (en) * | 2002-01-02 | 2003-09-09 | Intel Corporation | Power-up logic reference circuit and related method |
US7388248B2 (en) * | 2004-09-01 | 2008-06-17 | Micron Technology, Inc. | Dielectric relaxation memory |
US7245555B2 (en) * | 2005-12-12 | 2007-07-17 | Atmel Corporation | Automatic address transition detection (ATD) control for reduction of sense amplifier power consumption |
WO2011139503A1 (en) | 2010-04-30 | 2011-11-10 | Rambus Inc. | Low power edge and data sampling |
FR3044460B1 (en) | 2015-12-01 | 2018-03-30 | Stmicroelectronics (Rousset) Sas | PLAYBACK AMPLIFIER FOR MEMORY, ESPECIALLY EEPROM MEMORY |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4839539A (en) * | 1986-09-11 | 1989-06-13 | Ricoh Company, Ltd. | Partially enabled programmable logic device |
EP0357213A2 (en) * | 1988-09-02 | 1990-03-07 | Cypress Semiconductor Corporation | Low power sense amplifier for programmable logic device |
US4963769A (en) * | 1989-05-08 | 1990-10-16 | Cypress Semiconductor | Circuit for selective power-down of unused circuitry |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4930098A (en) * | 1988-12-30 | 1990-05-29 | Intel Corporation | Shift register programming for a programmable logic device |
US4942319A (en) * | 1989-01-19 | 1990-07-17 | National Semiconductor Corp. | Multiple page programmable logic architecture |
US4972102A (en) * | 1989-05-08 | 1990-11-20 | Motorola, Inc. | Single-ended sense amplifier with dual feedback and a latching disable mode that saves power |
-
1990
- 1990-05-08 US US07/520,673 patent/US5247213A/en not_active Expired - Lifetime
-
1991
- 1991-04-24 EP EP19910303673 patent/EP0456374A3/en not_active Ceased
- 1991-05-07 JP JP10137491A patent/JPH05315943A/en not_active Withdrawn
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4839539A (en) * | 1986-09-11 | 1989-06-13 | Ricoh Company, Ltd. | Partially enabled programmable logic device |
EP0357213A2 (en) * | 1988-09-02 | 1990-03-07 | Cypress Semiconductor Corporation | Low power sense amplifier for programmable logic device |
US4963769A (en) * | 1989-05-08 | 1990-10-16 | Cypress Semiconductor | Circuit for selective power-down of unused circuitry |
Non-Patent Citations (1)
Title |
---|
Proceedings of the IEEE 1989 Custom Integrated Circuits Conference, May 15 - 18, 1989, IEEE New York US, pages 5.5.1 - 5.5.4; S. P. GOWNI et al. "A 12ns, CMOS Programmable Logic Device for Combinatorial Applications" * |
Also Published As
Publication number | Publication date |
---|---|
JPH05315943A (en) | 1993-11-26 |
EP0456374A2 (en) | 1991-11-13 |
US5247213A (en) | 1993-09-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AT BE CH DE DK ES FR GB GR IT LI LU NL SE |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): AT BE CH DE DK ES FR GB GR IT LI LU NL SE |
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17P | Request for examination filed |
Effective date: 19920727 |
|
17Q | First examination report despatched |
Effective date: 19951207 |
|
GRAG | Despatch of communication of intention to grant |
Free format text: ORIGINAL CODE: EPIDOS AGRA |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION HAS BEEN REFUSED |
|
18R | Application refused |
Effective date: 19970125 |