EP0452966A3 - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

Info

Publication number
EP0452966A3
EP0452966A3 EP19910106362 EP91106362A EP0452966A3 EP 0452966 A3 EP0452966 A3 EP 0452966A3 EP 19910106362 EP19910106362 EP 19910106362 EP 91106362 A EP91106362 A EP 91106362A EP 0452966 A3 EP0452966 A3 EP 0452966A3
Authority
EP
European Patent Office
Prior art keywords
semiconductor device
manufacturing semiconductor
manufacturing
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19910106362
Other versions
EP0452966A2 (en
Inventor
Hirohito C/O Intellectual Property Div. Taneda
Masataka C/O Intellectual Property Div Takebuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Publication of EP0452966A2 publication Critical patent/EP0452966A2/en
Publication of EP0452966A3 publication Critical patent/EP0452966A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/945—Special, e.g. metal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
EP19910106362 1990-04-20 1991-04-19 Method of manufacturing semiconductor device Withdrawn EP0452966A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP10456690 1990-04-20
JP104566/90 1990-04-20

Publications (2)

Publication Number Publication Date
EP0452966A2 EP0452966A2 (en) 1991-10-23
EP0452966A3 true EP0452966A3 (en) 1993-09-29

Family

ID=14384005

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19910106362 Withdrawn EP0452966A3 (en) 1990-04-20 1991-04-19 Method of manufacturing semiconductor device

Country Status (3)

Country Link
US (1) US5190894A (en)
EP (1) EP0452966A3 (en)
KR (1) KR930008866B1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5403781A (en) * 1992-07-17 1995-04-04 Yamaha Corporation Method of forming multilayered wiring
JPH06333924A (en) * 1993-05-20 1994-12-02 Fujitsu Ltd Manufacture of semiconductor device
DE19521006C2 (en) 1994-06-08 2000-02-17 Hyundai Electronics Ind Semiconductor component and method for its production
JP2830812B2 (en) * 1995-12-27 1998-12-02 日本電気株式会社 Manufacturing method of multilayer printed wiring board
US5952156A (en) * 1997-07-11 1999-09-14 Vanguard International Semiconductor Corporation Enhanced reflectivity coating (ERC) for narrow aperture width contact and interconnection lithography

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1986001914A1 (en) * 1984-09-13 1986-03-27 Advanced Micro Devices, Inc. Photolithography process using positive photoresist containing unbleachable light absorbing agent
EP0181457A2 (en) * 1984-10-01 1986-05-21 International Business Machines Corporation Method for making contacts to integrated circuits
US4631806A (en) * 1985-05-22 1986-12-30 Gte Laboratories Incorporated Method of producing integrated circuit structures
EP0402482A1 (en) * 1988-12-28 1990-12-19 Oki Electric Industry Company, Limited Method of forming pattern
US4997790A (en) * 1990-08-13 1991-03-05 Motorola, Inc. Process for forming a self-aligned contact structure

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4557797A (en) * 1984-06-01 1985-12-10 Texas Instruments Incorporated Resist process using anti-reflective coating
JP2588192B2 (en) * 1987-04-30 1997-03-05 株式会社東芝 Pattern forming method
US5135891A (en) * 1988-01-19 1992-08-04 Mitsubishi Denki Kabushiki Kaisha Method for forming film of uniform thickness on semiconductor substrate having concave portion
US5057462A (en) * 1989-09-27 1991-10-15 At&T Bell Laboratories Compensation of lithographic and etch proximity effects
US5126289A (en) * 1990-07-20 1992-06-30 At&T Bell Laboratories Semiconductor lithography methods using an arc of organic material

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1986001914A1 (en) * 1984-09-13 1986-03-27 Advanced Micro Devices, Inc. Photolithography process using positive photoresist containing unbleachable light absorbing agent
EP0181457A2 (en) * 1984-10-01 1986-05-21 International Business Machines Corporation Method for making contacts to integrated circuits
US4631806A (en) * 1985-05-22 1986-12-30 Gte Laboratories Incorporated Method of producing integrated circuit structures
EP0402482A1 (en) * 1988-12-28 1990-12-19 Oki Electric Industry Company, Limited Method of forming pattern
US4997790A (en) * 1990-08-13 1991-03-05 Motorola, Inc. Process for forming a self-aligned contact structure

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
JAPANESE JOURNAL OF APPLIED PHYSICS, vol. 28, no. 10, October 1989, TOKYO, JP; pages 2049 - 2052; YOSHIHIKO HIRAI ET AL.: 'Computer aided proximity effect correction system in photolithography' *
PATENT ABSTRACTS OF JAPAN vol. 13, no. 97 (E-723)7 March 1989 *
PATENT ABSTRACTS OF JAPAN vol. 14, no. 298 (P-1068)27 June 1990 ( NEC CORP. ) *
PATENT ABSTRACTS OF JAPAN, vol. 13, no. 97 (E-723) 7 March 1989; & JP-A-63 272 030 (TOSHIBA CORP.) 9 November 1988 *

Also Published As

Publication number Publication date
US5190894A (en) 1993-03-02
KR910019194A (en) 1991-11-30
EP0452966A2 (en) 1991-10-23
KR930008866B1 (en) 1993-09-16

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