EP0450052A1 - Micro-ordinateur a architecture de bimemoire deconnectee, ouverte, independante - Google Patents

Micro-ordinateur a architecture de bimemoire deconnectee, ouverte, independante

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Publication number
EP0450052A1
EP0450052A1 EP19900916852 EP90916852A EP0450052A1 EP 0450052 A1 EP0450052 A1 EP 0450052A1 EP 19900916852 EP19900916852 EP 19900916852 EP 90916852 A EP90916852 A EP 90916852A EP 0450052 A1 EP0450052 A1 EP 0450052A1
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EP
European Patent Office
Prior art keywords
bicpu
circuits
microcomputer
bus
logically
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19900916852
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German (de)
English (en)
Inventor
Maurice E. Mitchell
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Individual
Original Assignee
Individual
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Filing date
Publication date
Priority claimed from US07/422,489 external-priority patent/US5116953A/en
Application filed by Individual filed Critical Individual
Publication of EP0450052A1 publication Critical patent/EP0450052A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8015—One dimensional arrays, e.g. rings, linear arrays, buses

Definitions

  • each cell would be configured as interacting, almost spherical ellipsoids of influence, with each ellipsoidal cell enclosing essentially 25 cubic miles and with only a 25 mile layer of contiguous ellipsoidal cells being formed about the earth, approximately 200 million cells would be required. A smaller cell size or increasing the volume to be considered would, of course, increase the number of ellipsoidal cells required. In any case, let each cell contain information requiring, say 1,000 floating point calculations per second. A computer system designed to handle information for the various cells would thus be required to perform 200 billion interacting floating point calculations per second.
  • SDIO Strategic Defense Initiative Organization
  • the individual, independent microcomputer should be able to individually “decide” to work with the other microcomputers, or not to work with the other microcomputers in the system, when the logic in it's standard memory circuits, written by human programmers and human field application system designers, instruct the microcomputer to work, or not to work, with the other microcomputers.
  • the third basic problem of present multiprocessor systems is the inability to make existing multiprocessor systems work as truly "parallel processors".
  • the Strategic Defense Initiative Organization problem and the World climate Prediction problem probably both require very highly parallel architectures to be effective. Over 200 billion interacting floating point calculations are required per second on the World climate Prediction problem as a minimum, and the SDIO requirement is very much larger. The SDIO problem could probably use 20 trillion interacting floating point calculations per second.
  • the fourth basic problem of present multiprocessor systems is removing individual processors that have failed or have been damaged by enemy action from a running system without causing further failure of the overall program logic of the balance of the remaining running system.
  • the fifth basic problem of present multiprocessor systems is adding individual processors to a running system without causing failure of the overall program logic of the balance of the running system.
  • the sixth basic problem of present multiprocessor systems is some of the switching circuits and some of the arbitration logic circuits and some of the error checking logic circuits needed to effectively interconnect several thousand processors, are being placed outside of the individual processors.
  • These different external logic circuits and BLOCK/SHORT circuits in circulating Pierce loop circuits preclude using one standard group of circuits made up of simple, dedicated purpose, single line conductors, where the standard group of circuits can be of various random lengths — less than a maximum length — to interconnect any two processors.
  • the seventh basic problem of present multiprocessor systems is that more than one standard group of circuits are used in the multiprocessor system to interconnect processors on different hierarchy levels.
  • some present multiprocessor systems like the "Restructurable Integrated Circuit For Implementing Digital Systems" as described by Rob Budzinski, John Linn, and Satish Thatte, COMPUTER. March 1982, pages 43 through 54, use the concept of external coordination of microprocessors as developed by R. G. Arnold and E.
  • the Bimemory Independent Central Processing Unit microcomputer (BICPU microcomputer) invention solves all seven of these basic problems.
  • the BICPU microcomputer is actually capable of mimicking the human thinking of the field application system designers and the human programmers involved in the system. If the human programmer can think of a solution, or the human field application system designer can think of a solution, several thousand BICPU microcomputers, mechanically interconnected in one of several billion different unique systems, where the programmers, at computer speeds, can logically connect and logically disconnect the thousands of BICPU microcomputers in several billion additional unique ways, using logical bimemory "S” hookups and logical bimemory "Y” hookups, probably will "be capable of mimicking human thinking" to the required degree.
  • VAX 8974 The announcement today, at a news conference in New York, is expected to involve two new machines, the VAX 8974 and 8978. Both link VAX 8700 computers, the 8974 in a cluster of four processors, the 8978 in a cluster of eight.
  • VAX computers accelerate an industry trend toward the combination of several processors in a single computer. But strictly speaking, the new VAX's are not “parallel processors" because their ability to divide a single problem and parcel it out to different processors is severely limited. "That's a software problem that still requires some additional work," said
  • the invention is a Bimemory Independent CPU (BICPU) microcomputer which is comprised of a known CPU chip provided with additional circuitry to enable the CPU to interact in a multi BICPU microcomputer system.
  • BICPU microcomputer in a system is supplied with an assigned standard memory mechanically and logically connected to it's BICPLTs "A" bus circuits.
  • the BICPU microcomputer is also provided with connectors enabling the CPU to be connected to system buses.
  • BICPU microcomputers can be logically chained, linked and treed in a simple logical bimemory independent pattern infinitely in as many dimensions as is reasonably desired, using one standard set of dedicated, simple, single line conductors (system buses) to mechanically interconnect any "B" or "C” bus circuits of two different BICPU microcomputers.
  • Packaging considerations will tend to be the limiting factor in the number of BICPU microcomputers that can be mechanically interconnected in large multi-BICPU microcomputer systems.
  • the BICPU microcomputer system might be as small as a single stand alone application of one Bimemory Independent CPU microcomputer utilizing its given memory, to a system with thousands of Bimemory Independent CPU microcomputers (BICPU microcomputers) in a world weather prediction system, or in an oil field geological survey, or in the Strategic Defense Initiative Organization computer system.
  • BICPU microcomputers Bimemory Independent CPU microcomputers
  • the invention can be retrofitted on certain types of highly successful microcomputers with dedicated pinout circuits being built today so that most, if not all, of the present software of these highly successful microcomputers can be run on the new Bimemory Independent CPU microcomputer invention with very little, if any, modifications.
  • the memory access circuits (address, data, control) of the CPU are connected to a switching unit. Three buses, "A", "B” and “C” are connected to the switching unit.
  • the internal structure of the switching unit is configured solely by the CPU to create a signal path connecting the memory access circuits of the CPU to the desired bus or buses or any selected portion thereof.
  • the CPU is further provided with circuitry, including two dedicated function processors (ILUs), to enable the CPU to communicate and interact with other CPUs on either of the system buses "B" or "C".
  • ILUs dedicated function processors
  • the CPU is also provided with additional registers to store switching unit configurations, system addresses etc.
  • page 42 of the above MOS microcomputer HARDWARE MANUAL, there are 8 dedicated pins connected to the 8 Data Bus circuits, 8 dedicated pins connected to the 8 Address Bus Low circuits, 8 dedicated pins connected to the 8 Address Bus High circuits, 10 dedicated pins connected to computer and memory control circuits, 3 dedicated pins connected to Power circuits and 3 pins are not connected.
  • the MCS6502 On Page 41, in lines 9 through 11, of the above MOS microcomputer HARDWARE MANUAL, the MCS6502 has the oscillator and clock driver on-chip, thus eliminating the need of an external high-level two- phase clock generator. Therefore with the MCS6502, in Figure 1.1 of the MOS microcomputer HARDWARE MANUAL above, the microcomputer independently, directly, logically controls all of the Program Memory (ROM), the Data Memory (RAM), and the Peripheral Interface Device shown, by independently, directly, logically reading and independently, directly, logically writing to the dedicated standard memory circuits mechanically and logically connected to the 40 pins of the MCS6502 Pinout Designation as shown in Figure 1.15 on page 42 of the above MOS microcomputer HARDWARE MANUAL.
  • ROM Program Memory
  • RAM Data Memory
  • Peripheral Interface Device the Peripheral Interface Device
  • the MCS6502 is a CPU that can independently, directly, logically read or write, in a logical manner, 256 pages of 256 characters each, where each character can be any of 256 different characters.
  • the phrase, in a logical manner, is meant to include all of the CPU's present and potential set of microinstructions, which in the case of the MCS6502 consists of 256 different microinstructions of which essentially 156 have been implemented.
  • the MCS6502 independently, directly, logically controls everything that is read or written on these 256 pages of memory space.
  • the MCS6502 essentially is an 8-bit microcomputer addressing a 16-bit address space. (With essentially 16-bit MCS650X type microcomputers addressing a 32-bit address space, the numbers 256 above can be changed to 65-536. In the World climate and SDIO problems above, 16-bit BICPU microcomputers addressing 32-bit address space can be used).
  • the BICPU microcomputer invention takes the MCS6502 and the dedicated address, data and control circuits presently connected to the 40 pins in Figure 1.15 on page 42 of the MOS microcomputer HARDWARE MANUAL (or some other similar type highly successful microcomputer), and defines these circuits the "A" bus circuits 520 of Figure 19 (the power circuits are not changed by the invention and for clarity are not shown in Figure 19).
  • the new bimemory switching circuits 502, 504, 506, and 508, of Figure 19 are inserted in these "A" bus circuits between the CPU and the pins of Figure 1.15 on page 42 above, (but are not inserted in the BICPU microcomputer power circuits).
  • bimemory switching circuits are also connected to the "B" bus circuits 522, and the "C” bus circuits 524 in a bimemory manner where at any one time the individual address circuits, data circuits and the read write circuit from the microcomputer of Figure 1.1 page 5, is logically directly connected to only one of the dedicated off chip pins in the "A" bus circuits 520, "B" bus circuits 522 or “C” bus circuits 524.
  • the remainder of the circuits utilized for memory control eg. clock timing circuits, ready circuit, sync circuit, interrupt circuits etc., remain connected between the CPU and its memory during bimemory operations.
  • BIC-BUS Bimemory Interconnecting Control-BUS
  • BIM mode - BJMemory mode - This is one of eight different logical bimemory modes a BICPU can assume. In these eight BIM modes, a first BICPU microcomputer is in a logical bimemory hookup, controlling part or all of two standard memory circuits in a bimemory manner. FLT mode - ELoaling mode - This is one of four different logical bimemory modes a "consenting"
  • BICPU microcomputer can assume.
  • a "consenting" BICPU microcomputer has logically connected some or all of its "A" bus circuits and the standard memory circuits connected thereto, to the BICPU microcomputer in the BIM mode in a logical bimemory hookup, and gone into a "floating" state waiting for the BICPU microcomputer in the BIM mode to complete the logical bimemory hookup.
  • PRM mode - ERimary Mode - This is one of three different logical modes a BICPU microcomputer can assume.
  • BIC-CTRB - BJCrBUS ConlRol Bus - These circuits comprise the BIC-AD circuits and the "BCR", “BEN” and “BRQ" lines. They are connected to the new buffers and Interconnect Switch on one end and connected to the "B" and “C” bus circuits on the other end. They join and run parallel with the other circuits in the BIC-BUS circuits. They are monitored and controlled by the ILUs, under the control of the CPU of the BICPU microcomputer. Essentially these circuits are new interrupt circuits between two CPUs of two different BICPU microcomputers. These BIC-CTRB circuits are always unique to one set of BIC-BUS circuits. The BIC-CTRB circuits of two different sets of BIC-BUS circuits are never interconnected, and remain unique to just the one set of BIC-BUS circuits they are in. The BICPU microcomputers never directly interconnect the
  • BCR line - Bus ControlleR line - This line is set TRUE by the "calling" ILU of a BICPU microcomputer and determines which ILU has control of a set of BIC-CTRB circuits.
  • the "BCR” line is set FALSE by the ILU of the BICPU microcomputer in the BIM mode in a logical bimemory hookup, to initiate logical hang up.
  • the "BEN" line is set FALSE by an ILU of a BICPU microcomputer, the logical bimemory hookup is logically hung up, saving the program logic in a logical hang up procedure.
  • BRQ line - Bus ReQuest line - This line is used by the ILUs to generate the "Not Active", “Active BICPU” or “Two or More” signals without requiring external logic circuits outside of the BICPU microcomputers involved in the logical bimemory hookup. This enables simple, single line circuits, without logic, to be used in the BIC-BUS circuits.
  • BIC-AD lines Bimemory Interconnecting Control Bus- ⁇ Ddress lines - These BIC-AD lines are part of the BIC-CTRB circuits. These BIC-AD lines are not to be confused with the standard address circuits of the CPU of the BICPU microcomputer. These BIC-AD lines are unique to one set of BIC-BUS circuits, and carry the assigned "B" or "C” register number of a BICPU microcomputer being "called” to participate in a logical bimemory hookup.
  • the standard address circuits of the CPU of the BICPU microcomputer can be interconnected between two sets of BIC-BUS circuits by the ILUs of the BICPU microcomputers involved in the logical bimemory hookup.
  • the BIC-AD circuits of two different sets of BIC-BUS circuits are never interconnected.
  • the ILUs monitor these BIC-AD circuits to determine when the address on these circuits match the valid assigned bus number stored in the correct "B" or "C” register, so that the ILUs can determine when they are being "called” by another ILU on this set of BIC-BUS circuits.
  • DHU - Directed Hang Up - New bimemory instruction causing an ILU to place a special code on the BIC-AD line, subsequently causing both "BEN" lines of each BICPU microcomputer in a given set of BIC-BUS circuits to go FALSE, thereby causing all logical bimemory hookups utilizing all involved BIC-BUS circuits to terminate logically.
  • NHU - Normal Hang Up - New bimemory instruction causing a normal logical hang up of the various sets of BIC-BUS circuits involved in a logical bimemory hookup. This is used by the programmer to hang up a logical bimemory hookup and return to a PRM mode. It can be compared to the RTN (return) instruction after a subroutine has been completed and the programmer directs the program logic to return to the instruction after the gosubroutine instruction.
  • GBH - Go Bimemory Hookup - New bimemory instruction causing the BICPU microcomputer to attempt to create a logical bimemory hookup between this BICPU microcomputer and another BICPU microcomputer.
  • This instruction can be compared to a gosubroutine instruction, where the subroutine includes many conditional tests.
  • standard memory circuits will be used to refer to "standard dedicated memory circuits” and the phrase “BIC-BUS circuits” will be used to refer to "dedicated BIC-BUS circuits" as all standard memory circuits and all BIC-BUS circuits are dedicated circuits in the BICPU microcomputer invention. Since all standard memory circuits are always mechanically connected to "A" bus circuits, and all BIC-BUS circuits are always mechanically connected to "B” or “C” bus circuits, the phrases “connected standard memory circuits” and “connected “B” or “C” bus circuits” always means “mechanically connected”.
  • first BICPU microcomputer will generally be used to refer to a BICPU microcomputer as depicted in the various bimemory modes in Figure 3 through Figure 13 and Figure 15 through Figure 17 that has standard memory circuits 217 connected to it's "A" bus circuits.
  • second BICPU microcomputer will generally be used to refer to a BICPU microcomputer connected to BIC-BUS circuits connected to the "B" bus circuits of a first BICPU microcomputer, that is in the process of being logically directly connected to, or is logically directly connected to the "B" bus circuits of a first BICPU microcomputer.
  • third BICPU microcomputer will generally be used to refer to a BICPU microcomputer connected to BIC-BUS circuits connected to the "C" bus circuits of a first BICPU microcomputer, that is in th process of being logically directly connected to, or is logically directly connected to the "C" bus circuits of a first BICPU microcomputer.
  • original calling BICPU microcomputer refers to a BICPU microcomputer that initially reads the first microcode of either a logical bimemory "S" hookup or a logical bimemory "Y” hookup.
  • the mode of the "original calling" BICPU microcomputer must be either a BIM mode or a FLT mode or a bimemor programming error has occurred.
  • interconnecting BICPU microcomputer refers to a BICPU microcomputer in either a PRM-1 mode or a PRM-2 mode, interconnecting two different sets of BIC-BUS circuits.
  • the new "B” Interrupt Logic Unit 634 in Figure 19 monitors and controls the "B" BIC-CTRB circuits 627 in Figure 19, and the new “C” Interrupt Logic Unit 636 in Figure 19, monitors and controls the "C” BIC- CTRB circuits 629 in Figure 19.
  • the new "B" register 604 in Figure 19 and the new “C” register 610 in Figure 19 hold assigned bus address numbers of this BICPU microcomputer, when this BICPU microcomputer is logically connected to the dedicated BIC-BUS circuits mechanically connected to it's "B” or "C” bus circuits.
  • the new Inter Connect Switch 660 in Figure 19 latches the status of the "BCR", and "BEN” circuits in a special bimemory way under control of the new Interrupt Logic Units (ILUs) 634 and 636.
  • the new Buffers 602 and 614 in Figure 19 latch, drive and read the BIC-AD circuits 600 and 652 in Figure 19, under the control of the new ILUs 634 and 636.
  • the standard address circuits, the standard data circuits and the standard control circuits connecting the BICPU of the BICPU microcomputer invention and the standard memory circuits are dedicated circuits such as are used in the MCS6502.
  • Figure 1.15 of the above MOS microcomputer HARDWARE MANUAL gives the
  • the Read/Write line allows the processor to control the direction of data transfers between the processor and the support chips. This line is high except when the processor is writing to memory or to a peripheral interface device.
  • the internal data bus enable function is connected directly to the phase two clock on the chip. Therefore pin 256 on the MCS6502 is not connected.
  • the implementation of the BICPU microcomputer invention requires that the standard address circuits, the standard data circuits and the standard control circuits and the standard memory circuits be of the dedicated type described in the MOS microcomputer HARDWARE MANUAL above.
  • the MCS6520 is a direct pin for pin replacement for the Motorola MC6820 Peripheral Interface Adapter, the "PIA". As such, it meets all of the "PIA" electrical specifications and is totally hardware compatible with the MC6820.
  • the BICPU microcomputer invention requires the human programmers to cause each and every logical interconnection of BIC-BUS circuits between any two BICPU microcomputers to be made by execution of appropriate program steps. This is an object of the invention.
  • the human field application system designers mechanically interconnect thousands of BICPU microcomputers in billions of different unique systems.
  • Each and every one of the individual, independent BICPU microcomputers can run all of their individual parallel programs, and each and every one of the individual, independent BICPU microcomputers can communicate in their old fashion way, using the standard memory circuits connected to their "A" bus circuits, just the same as they do now.
  • the first BICPU microcomputer modeling the first cell can write data relating to these changes in the first cell, directly logically to the "A" bus circuits of a consenting second BICPU microcomputer modeling a second cell, and the standard memory circuits connected thereto.
  • the first BICPU microcomputer modeling the first cell can read data directly logically from the "A" bus circuits, and the standard memory circuits connected thereto, of the consenting second BICPU microcomputer modeling the second cell.
  • BICPU microcomputers and the standard memory circuits connected to their "A" bus circuits — can be linked, treed and chained to closely model the interactive data flow of the modeled cells that make up the atmosphere or some other complex system.
  • the BICPU microcomputers contain all of the necessary switching circuits, arbitration logic circuits and error detecting circuits needed to effectively logically interconnect BICPU microcomputers in either the logical bimemory "S" hookup or the logical bimemory "Y” hookup, within the individual BICPU microcomputers. Since all logic switching circuits, all arbitration logic circuits and error detecting circuits are contained within the BICPU microcomputers, only simple, single circuit, BIC-BUS circuits are needed to mechanically interconnect the "B" and "C" bus circuits of two BICPU microcomputers.
  • the only logic circuits needed on the CPU side of the "A" bus circuits is the BICPU of the BICPU microcomputer invention itself.
  • the fabrication costs of multi-BICPU microcomputer systems are, therefore, notably reduced.
  • the BICPU microcomputers are also, preferably, adapted from existing highly successful microprocessor or microcomputer chips.
  • Multi-BICPU microcomputers systems require only BICPU microcomputers, standard BIC-BUS circuits, and standard memory circuits containing present standard peripherals.
  • the cost of adding the BICPU microcomputer bimemory switching circuits to present microprocessors is relatively small, and the total costs will be fairly low, compared to present multiprocessor systems.
  • the billions of man hours, that have gone into developing standard microcode routines, to handle such mundane computer tasks as monitoring the keyboard, displays, disks and other peripheral equipment, over the past twenty years, will continue to be used fully. The object of practicality is thus achieved.
  • Figure 1 is a general diagram of one simple bimemory switching circuit according to the invention, in one of the dedicated standard memory circuits between the CPU and the "A" bus circuits, the "B" bus circuits and the "C” bus circuits.
  • bimemory switching circuit connected in each BICPU microcomputer dedicated standard memory address circuit, standard memory data circuit and standard memory control circuit.
  • Figure 2 illustrates the logically disconnected and latched positions of the five major switch means in the bimemory switching circuits and the logically disconnected and latched, floating circuits of the first and second switch means in the automatic power off deactivated mode.
  • FIG. 3 represents the PRM-0 mode.
  • Figure 4 represents the PRM-1 and PRM-2 modes.
  • Figure 5 represents the BIM-0 mode.
  • Figure 6 represents the BIM-1 mode.
  • Figure 7 represents the BIM-2 mode.
  • Figure 8 represents the BIM-3 mode.
  • Figure 9 represents the BIM-4 mode.
  • Figure 10 represents the BIM-5 mode.
  • Figure 11 represents the BIM-6 mode.
  • Figure 12 represents the BIM-7 mode.
  • Figure 13 represents the FLT-0 mode.
  • Figure 14 is an illustration of the logically disconnected and latched switch means, the logically connected and latched switch means and the logically connected and unlatched switch means of two BICPU microcomputers in a logical bimemory "S" hookup.
  • Figure 15 represents the FLT-1 mode.
  • Figure 16 represents the FLT-2 mode.
  • Figure 18 is a diagram depicting one way one ILU load can be logically connected to, and logically disconnected from, the "BRQ" circuit, and how the "BEN” and “BRQ” circuits of one ILU, can be logically connected to the "BEN” and “BRQ” circuits of the "B" and “C” bus circuits.
  • FIG 20 is an illustration of BICPU microcomputers connected along dedicated standard Bimemory Interconnecting Control-BUS (BIC-BUS) circuits connected to "B" and "C” bus circuits, 522 and 524 of Figure 19.
  • Figure 21 is another illustration of BICPU microcomputers connected along dedicated BIC-BUS circuits connected to "B" and "C" bus circuits.
  • BIC-BUS Bimemory Interconnecting Control-BUS
  • the switching unit 100 is connected to buses "A", "B” and “C” through the first, second and fourth parts of a first switching mechanism divided into five parts 126, 130, 131, 134, and 135, and is connected to the CPU 102 through a second switch mechanism 104. These switches are utilized to connect the address, data and control lines necessary for the proper memory access between the buses, the switching unit 100 and the CPU,
  • the third 131 and fifth 135 parts of the first switch are utilized to connect the CPU, 102 to the system address and status lines of the "B" and "C" buses.
  • Control lines, 106 enable the CPU, 102 to logically connect and disconnect the desired switches including the above described first and second as well as the third 108, fourth 110, fifth 112, sixth 114, and seventh 116.
  • the third through seventh switches are utilized to create a data flow path through the switching unit 100 for transfer of data between the CPU 102 and the memory 120 and the "B" and "C" buses.
  • the first switch means (in 126, 130 and 134 circuits in Figure 1), the second switch means (in 104 circuits in Figure 1), the third switch means 108, the fourth switch means 110, the fifth switch means 112, the sixth switch means 114 and the seventh switch means 116 are logically disconnected and logically connected to (a) permit logical data flow, (b) to inhibit logical data flow, or (c) permit logical data flow to or from the "A" bus circuits 124 and the standard memory circuits connected thereto, of a BICPU microcomputer.
  • the logical transfer of data between CPU 102 and the "A" bus circuits and the standard memory circuits 120 connected thereto is over the first internal bus circuits 122 (via I/O circuits 104 each with second switch means, via the third switch means 108 to a common junction point), and the second internal bus circuits to it's "A" bus circuits 124 (from the common junction point, via the fourth switch means 110, via I/O circuits 126 each with first switch means).
  • the third switch means 108 and fourth switch means 110 are logically connected and latched (i.e.
  • the standard address circuits of the "B" and “C” bus circuits are bi-directional standard address circuits, similar to the bi-directional standard data circuits.
  • the "B" and “C” bus circuits are connected to BIC- BUS circuits, which are connected to other "B" or "C” bus circuits.
  • Each circuit connected to a second switch means is connected to it's common junction point in the bimemory switching circuits, and contains a third switch means (arrow mark 2221 in Figure 3), controlled by the CPU of the BICPU microcomputer, to logically disconnect and latch, to logically connect and latch, the circuit connected to the third switch means, and to operate the third switch means in a bimemory manner, when power is being supplied to the CPU power circuits.
  • a third switch means (arrow mark 2221 in Figure 3)
  • These circuits that are connected to a second and a third switch means, and to a common junction point in the bimemory switching circuits are collectively referred to as the first internal bus circuits 218, of the bimemory switching circuits 203 of Figure 3.
  • the interconnecting first BICPU microcomputer can then logically connect and latch it's second switch means, it's third switch means (108 in Figure 1), it's fourth switch means (110 in Figure 1) and it's first switch means in it's "A" bus circuits (124 in Figure 1 or 520 in Figure 19), and thus continue to directly logically read and write to it's "A" bus circuits (124 in Figure 1) and the standard memory circuits (120 in Figure 1) connected thereto, while in the PRM-1 and PRM-2 bimemory modes.
  • bimemory BIM-4, BIM-5, BIM-6 and BIM-7 modes where both a consenting second BICPU microcomputer, directly logically connected through the "B" bus circuits, and a consenting third BICPU microcomputer, directly logically connected through the "C" bus circuits, have agreed to allow a logical bimemory hookup, either the consenting second BICPU microcomputer (240 in Figure 9 or Figure 10), or the consenting third BICPU microcomputer (242 in Figure 11 or Figure 12), have also agreed to permit the first BICPU microcomputer, 2ERO Page, STACK and STANDARD VECTOR Page privileges.
  • the consenting first BICPU microcomputer after deciding to allow the third BICPU microcomputer in the BIM mode to perform the desired logical bimemory hookup, goes into one of several floating modes, by confirming it's seventh switch means (116 in Figure 1) are logically disconnected and latched, it's first switch means on it's "C” bus circuits are logically connected and latched, it's first switch means on it's "A” bus circuits are logically connected and latched, and logically disconnects and latches any address circuits in it's sixth switch means (114 in Figure 1) that are not being allowed to be used by the third BICPU microcomputer, and logically connects and latches any address circuits in it's third switch means that are being controlled by the consenting first BICPU microcomputer, and logically disconnects and latches it's fifth switch means (112 in Figure 1), and logically disconnects and latches it's first switch means connected to it's fifth switch means and logically connects
  • the new Status Registers are used to store the microcodes needed to complete this BICPU microcomputer link of a logical bimemory "S" hookup or logical bimemory "Y” hookup — the microcode for the mode of a first BICPU microcomputer being stored in one particular Status Register and the assigned bus number and mode of a linking second or third BICPU microcomputer with which a first BICPU microcomputer is to form a logical bimemory "S" or logical bimemory "Y” hookup with, being entered into other Status Registers of the first BICPU microcomputer.
  • Other Status Registers relate to patterns of full or partly connected Address High Bus circuits for the particular logical bimemory hookup to be preformed between two BICPU microcomputers.
  • This "BCR” circuit FALSE signal causes the ILUs involved in this logical bimemory hookup to unlatch in a domino fashion back through all of the interconnected sets of BIC-BUS circuits to the BICPU microcomputer in the FLT mode in the logical bimemory hookup.
  • the BICPU microcomputer in the FLT mode interprets the "BCR” circuit FALSE signal as a signal that the BICPU microcomputer in the BIM mode has finished with the logical bimemory hookup, and sets the "BEN” circuit FALSE and proceeds to return from FLT and continues on with it's operation when it was initially interrupted to help in the logical bimemory hookup.
  • the BIMEMORY SWITCHING UNIT Figure 19 is an overall drawing of a BICPU microcomputer 400 adapted from a conventional microcomputer of the MCS650X chip family.
  • the BICPU microcomputer 400 adds various elements onto the MCS650X chip to achieve the Bimemory Independent CPU effects of the invention and thereby create an improved microcomputer chip.
  • the improved microcomputer chip substantially represents the improved microcomputer chip.
  • the switches 5022, 504, 506 and 508 correspond to sets of bimemory switching circuits 100 depicted in Figure 1. That is, the bimemory switching circuits 5022, 504, 506 and 508 determine which, if any, of the circuits in the "A", “B” or “C” bus circuits 520, 522 or 524, the processor 402 is directly logically connected to at any one moment in time.
  • the bimemory switching circuits 100 are operated in a bimemory manner, at any one moment in time, the address, data and read/write circuits from the processor 402 are directly logically connected to only one of the three bus circuits, the "A" bus circuits, the "B” bus circuits, or the "C” bus circuits.
  • processor 400 When processor 400 is directly logically writing data to a specific address in the "A" bus circuits and the standard memory circuits directly connected thereto, of a consenting third BICPU microcomputer, connected to the "C" bus circuits 524, the 8 data circuits 430, (including the DB0 circuit), the 16 address circuits 431 (or the logically connected ABH circuits and the 8 ABL circuits), and the read/write circuit 458, are all directly logically connected to these circuits in the "A" bus circuits of the consenting third BICPU microcomputer, at the same moment in time.
  • BUS circuits are all on the same set of BIC-BUS circuits. Any two different sets of BIC-BUS circuits can be interconnected by a BICPU microcomputer.
  • the BICPU microcomputer "ALONE" can be symbolically mechanically connected to any black dot in the system of standard BIC-BUS circuits, by putting a large black dot on either it's "B” or "C” bus "ear” and drawing a line to any other large black dot in the system.
  • the DHU interrupt occurs when the highest order bit in BIC-AD circuits 600 or 652 is TRUE. This is when the number on the BIC-AD circuits is 128 through 255. All of the DHU numbers from 128 through 255 can be assigned any additional special meaning that creative Programmers can think of, to implement various programming concepts, in addition to the DHU interrupt. Each BICPU microcomputer in a large BICPU microcomputer system can have different additional special meanings for the same DHU interrupt number.
  • "B” ILU (4.CAT) 634 automatically logically connects one ILU load to the "BRQ” circuit and logically connects the "BRQ” and “BEN” circuits, and checks if BICPU# 4.CAT-15.DOG is "BUSY” on “C” bus circuits 524. Assume BICPU# 4.CAT-15.DOG is not busy on “C” bus circuits (Status Register 706 is 2£ERO). 10 "B” ILU (4.CAT) 634 sets maskable interrupt for BICPU# 4.CAT-15.DOG, and drives “BEN” circuit TRUE in "CAT” set of BIC-BUS circuits for the first time.
  • the simple block diagram in Figure 18 illustrates one way to logically connect one standard ILU load to the "BRQ” circuit and logically connect and latch the "BRQ" and "BEN” circuits after the "C” ILU 636 has detected a match between the "C” BIC-AD circuits 652 and the "C” register 610.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

Micro-ordinateur (101) à unité centrale indépendante à bimémoire (UCIB), comprenant une puce d'unité centrale connue dotée d'un circuit additionnel permettant à l'unité centrale d'avoir une action mutuelle dans un système de micro-ordinateur multi UCIB. Chaque micro-ordinateur à UCIB se trouvant dans un système, est alimenté par une mémoire (120) normale affectée, connectée mécaniquement et logiquement à ces circuits (124) de bus "A" d'UCIB. Le micro-ordinateur à UCIB est également doté de connecteurs (100) permettant à l'unité centrale d'être connectée à des bus de système. N'importe quel nombre de micro-ordinateurs à UCIB peut être logiquement enchaîné, lié et disposé en un arbre dans une configuration indépendante à bimémoire logique simple infiniment, dans autant de dimensions que cela est raisonnablement désiré, à l'aide d'un ensemble classique de conducteurs de lignes spécialisées, simples, uniques (bus de systèmes), afin d'interconnecter mécaniquement n'importe quel circuit de bus "B" (128) ou "C" (132) de deux micro-ordinateurs AUCIB différents.
EP19900916852 1989-10-17 1990-10-16 Micro-ordinateur a architecture de bimemoire deconnectee, ouverte, independante Withdrawn EP0450052A1 (fr)

Applications Claiming Priority (2)

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US07/422,489 US5116953A (en) 1988-10-17 1989-10-17 Method for thermally treating lactoferrin
US422489 1999-10-21

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Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3566363A (en) * 1968-07-11 1971-02-23 Ibm Processor to processor communication in a multiprocessor computer system
US3771137A (en) * 1971-09-10 1973-11-06 Ibm Memory control in a multipurpose system utilizing a broadcast
CH547590A (de) * 1973-03-21 1974-03-29 Ibm Fernmelde-vermittlungsanlage.
US3938098A (en) * 1973-12-26 1976-02-10 Xerox Corporation Input/output connection arrangement for microprogrammable computer
US4123794A (en) * 1974-02-15 1978-10-31 Tokyo Shibaura Electric Co., Limited Multi-computer system
US4130865A (en) * 1974-06-05 1978-12-19 Bolt Beranek And Newman Inc. Multiprocessor computer apparatus employing distributed communications paths and a passive task register
DE2546202A1 (de) * 1975-10-15 1977-04-28 Siemens Ag Rechnersystem aus mehreren miteinander verbundenen und zusammenwirkenden einzelrechnern und verfahren zum betrieb des rechnersystems
US4228496A (en) * 1976-09-07 1980-10-14 Tandem Computers Incorporated Multiprocessor system
DE2656086C2 (de) * 1976-12-10 1986-08-28 Siemens AG, 1000 Berlin und 8000 München Rechenanlage
DE2842288A1 (de) * 1978-09-28 1980-04-17 Siemens Ag Datentransferschalter mit assoziativer adressauswahl in einem virtuellen speicher
US4434461A (en) * 1980-09-15 1984-02-28 Motorola, Inc. Microprocessor with duplicate registers for processing interrupts
JPS5793422A (en) * 1980-11-29 1982-06-10 Omron Tateisi Electronics Co Dma controller
US4633392A (en) * 1982-04-05 1986-12-30 Texas Instruments Incorporated Self-configuring digital processor system with logical arbiter
US4589063A (en) * 1983-08-04 1986-05-13 Fortune Systems Corporation Data processing system having automatic configuration

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9106910A1 *

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WO1991006910A1 (fr) 1991-05-16

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