EP0438706A3 - High speed cmos drive circuit - Google Patents

High speed cmos drive circuit Download PDF

Info

Publication number
EP0438706A3
EP0438706A3 EP19900124056 EP90124056A EP0438706A3 EP 0438706 A3 EP0438706 A3 EP 0438706A3 EP 19900124056 EP19900124056 EP 19900124056 EP 90124056 A EP90124056 A EP 90124056A EP 0438706 A3 EP0438706 A3 EP 0438706A3
Authority
EP
European Patent Office
Prior art keywords
high speed
drive circuit
speed cmos
cmos drive
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP19900124056
Other versions
EP0438706A2 (en
EP0438706B1 (en
Inventor
Barbara A. Chappell
Terry I. Chappell
Stanley E. Schuster
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0438706A2 publication Critical patent/EP0438706A2/en
Publication of EP0438706A3 publication Critical patent/EP0438706A3/en
Application granted granted Critical
Publication of EP0438706B1 publication Critical patent/EP0438706B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
    • H03K17/145—Modifications for compensating variations of physical values, e.g. of temperature in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
EP90124056A 1990-01-26 1990-12-13 High speed cmos drive circuit Expired - Lifetime EP0438706B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US471155 1990-01-26
US07/471,155 US4998028A (en) 1990-01-26 1990-01-26 High speed CMOS logic device for providing ECL compatible logic levels

Publications (3)

Publication Number Publication Date
EP0438706A2 EP0438706A2 (en) 1991-07-31
EP0438706A3 true EP0438706A3 (en) 1992-01-29
EP0438706B1 EP0438706B1 (en) 1995-03-22

Family

ID=23870466

Family Applications (1)

Application Number Title Priority Date Filing Date
EP90124056A Expired - Lifetime EP0438706B1 (en) 1990-01-26 1990-12-13 High speed cmos drive circuit

Country Status (4)

Country Link
US (1) US4998028A (en)
EP (1) EP0438706B1 (en)
JP (1) JP2536965B2 (en)
DE (1) DE69018053T2 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5247212A (en) * 1991-01-31 1993-09-21 Thunderbird Technologies, Inc. Complementary logic input parallel (clip) logic circuit family
JP2824706B2 (en) * 1991-09-27 1998-11-18 三菱電機株式会社 Current source circuit and operation method thereof
US5280204A (en) * 1992-07-02 1994-01-18 International Business Machines Corporation ECI compatible CMOS off-chip driver using feedback to set output levels
TW247975B (en) * 1992-07-14 1995-05-21 Philips Electronics Nv
JP3080793B2 (en) * 1992-10-27 2000-08-28 株式会社東芝 Interface circuit
US5343094A (en) * 1993-01-13 1994-08-30 National Semiconductor Corporation Low noise logic amplifier with nondifferential to differential conversion
US5365127A (en) * 1993-10-18 1994-11-15 Hewlett-Packard Company Circuit for conversion from CMOS voltage levels to shifted ECL voltage levels with process compensation
US6054874A (en) * 1997-07-02 2000-04-25 Cypress Semiconductor Corp. Output driver circuit with switched current source
US6084439A (en) * 1997-07-02 2000-07-04 Cypress Semiconductor Corp. Peak detector circuit with extended input voltage range
DE19801994C1 (en) * 1998-01-20 1999-08-26 Siemens Ag Reference voltage generator
GB2351195A (en) 1999-06-10 2000-12-20 Ericsson Telefon Ab L M An MOS voltage to current converter with current to voltage output stage and MOS feedback

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3986043A (en) * 1974-12-20 1976-10-12 International Business Machines Corporation CMOS digital circuits with active shunt feedback amplifier
US4656375A (en) * 1985-12-16 1987-04-07 Ncr Corporation Temperature compensated CMOS to ECL translator
US4656372A (en) * 1985-11-25 1987-04-07 Ncr Corporation CMOS to ECL interface circuit
EP0318018A2 (en) * 1987-11-26 1989-05-31 Kabushiki Kaisha Toshiba Level shift circuit for converting a signal in an ecl level into a signal in a CMOS logic level

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0773205B2 (en) * 1983-12-20 1995-08-02 株式会社日立製作所 Level conversion circuit
DE3784285T2 (en) * 1986-08-29 1993-07-22 Mitsubishi Electric Corp INTEGRATED COMPLEMENTARY MOS CIRCUIT.
US4845381A (en) * 1987-10-01 1989-07-04 Vlsi Technology, Inc. Voltage level shifting circuit
US4835419A (en) * 1987-10-30 1989-05-30 International Business Machines Corporation Source-follower emitter-coupled-logic receiver circuit
US4947061A (en) * 1989-02-13 1990-08-07 At&T Bell Laboratories CMOS to ECL output buffer circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3986043A (en) * 1974-12-20 1976-10-12 International Business Machines Corporation CMOS digital circuits with active shunt feedback amplifier
US4656372A (en) * 1985-11-25 1987-04-07 Ncr Corporation CMOS to ECL interface circuit
US4656375A (en) * 1985-12-16 1987-04-07 Ncr Corporation Temperature compensated CMOS to ECL translator
EP0318018A2 (en) * 1987-11-26 1989-05-31 Kabushiki Kaisha Toshiba Level shift circuit for converting a signal in an ecl level into a signal in a CMOS logic level

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEEE JOURNAL OF SOLID-STATE CIRCUITS vol. 24, no. 2, April 1989, pages 478-486, New York, US; H.J. SHIN et al.: "A 250-Mbit/s CMOS Crosspoint Switch" *

Also Published As

Publication number Publication date
US4998028A (en) 1991-03-05
JPH03240315A (en) 1991-10-25
EP0438706A2 (en) 1991-07-31
JP2536965B2 (en) 1996-09-25
DE69018053D1 (en) 1995-04-27
EP0438706B1 (en) 1995-03-22
DE69018053T2 (en) 1995-09-28

Similar Documents

Publication Publication Date Title
GB2254124B (en) Mounting mechanical drive components on shafts
EP0449251A3 (en) Output circuit
EP0466245A3 (en) Circuit arrangement
GB2242960B (en) Drive shaft
GB2234872B (en) High speed CMOS differential interface circuits
EP0484878A3 (en) Wye-branching optical circuit
HU910278D0 (en) Circuit arrangement
EP0436371A3 (en) Antimetastable state circuit
EP0438706A3 (en) High speed cmos drive circuit
GB2241769B (en) Drive shaft
EP0439158A3 (en) High speed level conversion circuit
EP0472426A3 (en) Cmos flip-flop circuit
EP0846372A4 (en) Cmos buffer circuit having increased speed
GB9103461D0 (en) Logic circuit
EP0478385A3 (en) Field decision circuit
EP0446908A3 (en) High speed opto-electronic crossbar switch
EP0596864A3 (en) Speed enhancement technique for cmos circuits
TW323867U (en) Driving circuit
DE3570338D1 (en) High speed cmos circuits
GB2256982B (en) Motor circuit
GB2242959B (en) Drive shaft
GB2239956B (en) Circuit arrangement
GB2269219B (en) Drive shaft
AU630784B2 (en) Wiper drive circuit
GB9100487D0 (en) Drive circuit for hammer-solenoid

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE FR GB

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

17P Request for examination filed

Effective date: 19911112

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): DE FR GB

17Q First examination report despatched

Effective date: 19931227

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

REF Corresponds to:

Ref document number: 69018053

Country of ref document: DE

Date of ref document: 19950427

ET Fr: translation filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 19951128

Year of fee payment: 6

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 19961126

Year of fee payment: 7

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 19970116

Year of fee payment: 7

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Effective date: 19970829

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19971213

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 19971213

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19980901