EP0423825A2 - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
EP0423825A2
EP0423825A2 EP90120126A EP90120126A EP0423825A2 EP 0423825 A2 EP0423825 A2 EP 0423825A2 EP 90120126 A EP90120126 A EP 90120126A EP 90120126 A EP90120126 A EP 90120126A EP 0423825 A2 EP0423825 A2 EP 0423825A2
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EP
European Patent Office
Prior art keywords
lines
power
grounding
supply
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP90120126A
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German (de)
French (fr)
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EP0423825B1 (en
EP0423825A3 (en
Inventor
Munehiro C/O Intellectual Property Div. Yoshida
Syuso C/O Intellectual Property Div. Fujii
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Toshiba Corp
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Toshiba Corp
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Publication date
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Publication of EP0423825A2 publication Critical patent/EP0423825A2/en
Publication of EP0423825A3 publication Critical patent/EP0423825A3/en
Application granted granted Critical
Publication of EP0423825B1 publication Critical patent/EP0423825B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Definitions

  • the present invention relates to a semiconductor memory device, and more particularly to improvement of a pattern in which the power-supply and grounding lines connected to a peripheral circuit are arranged.
  • Fig. 1 denotes a semiconductor chip
  • 2 and 2′ denote memory cell array regions
  • 3 denotes a peripheral cir­cuit region
  • 4 denotes a power-supply line
  • 5 denotes a grounding line
  • 6 denotes a power-supply pad
  • 7 denotes a grounding pad.
  • two memory cell array regions 2 and 2′ are formed on the semiconductor chip 1.
  • the peripheral circuit region 3 is formed between the two memory cell array regions 2 and 2′.
  • a bonding pad region, an input protection circuit region, and other necessary circuit regions are formed in those regions around the memory cell array regions 2 and 2′, except for the peripheral circuit region 3. (For simplicity, the bonding pad region, the input protection circuit region, and other necessary circuit regions will be collectively referred to as a "bonding pad region", unless otherwise indicated.)
  • the power-supply line 4 and the grounding line 5 are formed in the regions around the memory cell array regions 2 and 2′, so as to supply a power-supply or ground potential to the peripheral circuit region 3 and the bonding pad region.
  • the power-­supply line 4 and the grounding line 5 are connected to both the peripheral circuit region 3 and the bonding pad region.
  • the power-supply line 4 is also connected to the power-supply pad 6, while the grounding line 5 is also connected to the grounding pad 7.
  • the power-supply line 4 and the grounding line 5 are arranged in the regions around the memory cell array regions 2 and 2′. Consequently, they occupy a certain area on the regions around the memory cell array regions 2 and 2′. In addi­tion, they are required to have a certain width throughout the length, because a stable power-supply potential has to be applied even to their terminating points. If their widths are decreased, the impedance of the lines will increase, with the result that the poten­tial necessary for a normal operation of the peripheral circuits will not be supplied. Moreover, the semicon­ductor memory device has to employ a larger chip in accordance with an increase of the capacity of the device.
  • the power-supply line 4 and the grounding line 5 arranged around the memory cell arrays 2 and 2′ have been lengthened year by year.
  • an increase in the resistance of the wiring lines has become a problem.
  • the power-supply line 4 and the grounding line 5 arranged around the memory cell arrays 2 and 2′ have to be widened in accordance with the increase in the capa­city. Since, therefore, the power-supply line 4 and the grounding line 5 require a wide installation area, the size of the semiconductor chip is difficult to reduce.
  • the present invention has been developed to solve the problems mentioned above, and its object is to pro­vide a semiconductor memory device, wherein a power-­supply line and a grounding line occupy only a very small installation area even in the case where they are arranged in the regions around the memory cell array regions, and wherein a power-supply or ground potential can be supplied in a stable manner even to the ter­minating ends of the power-supply and grounding lines.
  • the present invention pro­vides a semiconductor memory device which comprises: a memory cell array region; a plurality of signal lines arranged above the memory cell array region; and a plurality of power-supply lines and grounding lines regularly arranged between the signal lines in a similar pattern to that of the signal lines.
  • the present invention also provides a semiconductor device which comprises: at least two memory cell array regions; a peripheral circuit region located between the memory cell array regions; a plurality of signal lines arranged above the memory cell array regions; and a plurality of power-supply lines and grounding lines which are regularly arranged between the signal lines in a similar pattern to that of the signal lines and which are connected to the peripheral circuit region.
  • Fig. 2 is a schematic view showing how a power-­supply line and a grounding line are arranged in the embodiment of the present invention.
  • reference numeral 11 denotes a semiconductor chip
  • 12 and 12′ denote memory cell array regions, respectively
  • 13 denotes a peripheral circuit region
  • 14 denotes a power-supply pad
  • 15 denotes a grounding pad
  • d1, d2, ... dn denote power-supply lines, respectively
  • s1, s2, ... sn denote grounding lines, respectively.
  • the semiconductor chip 12 has e.g. two memory cell array regions 12 and 12′.
  • the peripheral circuit region 13 is located between these two memory cell array regions 12 and 12′.
  • a bonding pad region is formed in the regions located around the memory cell array regions 12 and 12′.
  • the power-­supply pad 14 and the grounding pad 15 are connected to this bonding pad region.
  • the power-supply lines d1, d2, ... dn are connected at one end to the power-supply pad 14 and are regularly arranged above the memory cell array regions 12 and 12′. It should be noted that the power-supply lines d1, d2, ... dn are electrically connected not to memory cell arrays but to the peripheral circuit region 13 located between the memory cell array regions 12 and 12′. It is preferable that the power-supply lines d1, d2, ... dn be connected together above the peripheral circuit region 13. If necessary, the power supply lines d1, d2, ... dn may be also connected together at their terminating ends.
  • grounding lines s1, s2, ... sn are connected at one end to the grounding pad 15 and are regularly arranged above the memory cell array regions 12 and 12′. It should be noted that the grounding lines s1, s2, ... sn are electrically connected not to the memory cell arrays but to the peripheral circuit region 13. It is preferable that the grounding lines s1, s2, ... sn be connected together on the peripheral circuit region 13. If necessary, the grounding lines s1, s2, ... sn may be also connected together at their terminating ends.
  • the power-supply lines d1, d2, ... dn and the grounding lines s1, s2, ... sn which are arranged above the memory cell array regions 12 and 12′, are connected to the peripheral circuit region 13 located between the memory cell array regions 12 and 12′.
  • the power-supply and grounding lines do not require a wide installation area in the regions around the memory cell array regions 12 and 12′; the installa­tion area can be narrow as long as the power-supply and grounding lines allow a sufficient power-supply or ground potential to an input protection circuit or other circuits. That is, the installation area around the memory cell array regions 12 and 12′ can be reduced, thus enabling the use of a small-sized chip.
  • each of the power-supply lines d1, d2, ... dn need not be widened since the number of power­supply lines d1, d2, ... dn can be increased instead.
  • each of the grounding lines s1, s2, ... sn need not be widened since the number of grounding lines s1, s2, ... dn can be increased instead. Accordingly, the impedance of each power-supply line and that of each grounding line are low. As a result, a stable power-­supply potential can be supplied even to the terminating ends of the power-supply lines d1, d2, ... dn, and a stable ground potential can be supplied even to the ter­minating points of the grounding lines s1, s2, ... sn.
  • the power-supply lines d1, d2, ... dn and the grounding lines s1, s2, ... sn need not be arranged around the memory cell array regions 12 and 12′. Accordingly, the installation area for them can be completely eliminated from around the memory cell array regions 12 and 12′.
  • Fig. 3 is a schematic view which illustrates, in a large scale, the power-supply and grounding lines arranged above one memory cell array region.
  • reference numeral 16 denotes a column-selecting line
  • 17 denotes a contact hole through which the column-­selecting line 17 and a memory cell array are connected to each other
  • dk denotes a power-supply line
  • sk deno­tes a grounding line.
  • the column-selecting lines 16 are regularly arranged on the memory cell array region 12, and are connected to the memory cell array through the contact holes 17.
  • the power-supply line dk and/or the grounding line sk are regularly arranged between the adjacent ones of the column-selecting lines 16 in a similar pattern to that of the column-selecting lines 16.
  • the power-supply line dk and the grounding line sk are alternately arranged between the column-selecting lines 16. It should be noted that the power-supply line dk and the grounding line sk are not connected to the memory cell array.
  • the power-supply lines dk and the grounding lines sk are regularly arranged in a simi­lar pattern to that of the column-selecting lines 16.
  • the power-supply and grounding lines dk and sk arranged above the memory cell array region 12 do not result in a dispersion in the parasitic capacitance of bit lines formed under the column-selecting lines 16. Since, therefore, little noise is generated in the bit lines, the reading of information is in no way adversely affected.
  • the power-supply line dk and the grounding line sk need not be alternately arranged; both of them may be regularly arranged between the adjacent ones of the column-selecting lines 16. Even where both the power-­supply line dk and the grounding line sk are arranged between two adjacent column-selecting lines 16, the advantages arising from this arrangement are substan­tially the same. Moreover, the power-supply line dk and the grounding line sk may be arranged between column signal reading/writing lines or the like, not between the column-selecting lines 16.
  • Fig. 4 is a schematic view showing a 16-M DRAM to which the semiconductor memory device of the embodiment is applied.
  • reference numeral 21 denotes a semiconductor chip
  • 22 denotes a peripheral circuit region
  • 23 denotes a memory cell array
  • 24 denotes a column decoder region
  • 25 denotes a row decoder region
  • 26 denotes a grounding pad
  • 28 denotes a grounding line
  • 29 denotes a column-selecting line.
  • both the power-supply lines d1, d2, ... dn and the grounding lines s1, s2, ... sn are arranged above the memory cell array regions 12 and 12′.
  • either the power-­supply lines d1, d2, ... dn or the grounding lines s1, s2, ... sn may be arranged above the memory cell array regions 12 and 12′.
  • the power-supply lines d1, d2, ... dn may be applied with a power-supply poten­tial reduced inside the chip, instead of being applied with a power-supply potential supplied from the power-­supply pad 14.

Abstract

A semiconductor memory device has a memory cell array region (12), a plurality of signal lines (16) arranged above the memory cell array region, and a plurality of power-supply lines (dk) and grounding lines (sk), each of which has a first end and a second end and which are regularly arranged between the signal lines (16) in a similar pattern to that of the signal lines (16).

Description

  • The present invention relates to a semiconductor memory device, and more particularly to improvement of a pattern in which the power-supply and grounding lines connected to a peripheral circuit are arranged.
  • The power-supply line and grounding line of a con­ventional semiconductor device are arranged in such a pattern as is shown in Fig. 1. In Fig. 1, reference numeral 1 denotes a semiconductor chip; 2 and 2′ denote memory cell array regions; 3 denotes a peripheral cir­cuit region; 4 denotes a power-supply line; 5 denotes a grounding line; 6 denotes a power-supply pad; and 7 denotes a grounding pad.
  • As is shown in Fig. 1, two memory cell array regions 2 and 2′ are formed on the semiconductor chip 1. The peripheral circuit region 3 is formed between the two memory cell array regions 2 and 2′. A bonding pad region, an input protection circuit region, and other necessary circuit regions are formed in those regions around the memory cell array regions 2 and 2′, except for the peripheral circuit region 3. (For simplicity, the bonding pad region, the input protection circuit region, and other necessary circuit regions will be collectively referred to as a "bonding pad region", unless otherwise indicated.)
  • The power-supply line 4 and the grounding line 5 are formed in the regions around the memory cell array regions 2 and 2′, so as to supply a power-supply or ground potential to the peripheral circuit region 3 and the bonding pad region. In other words, the power-­supply line 4 and the grounding line 5 are connected to both the peripheral circuit region 3 and the bonding pad region. The power-supply line 4 is also connected to the power-supply pad 6, while the grounding line 5 is also connected to the grounding pad 7.
  • In the pattern mentioned above, the power-supply line 4 and the grounding line 5 are arranged in the regions around the memory cell array regions 2 and 2′. Consequently, they occupy a certain area on the regions around the memory cell array regions 2 and 2′. In addi­tion, they are required to have a certain width throughout the length, because a stable power-supply potential has to be applied even to their terminating points. If their widths are decreased, the impedance of the lines will increase, with the result that the poten­tial necessary for a normal operation of the peripheral circuits will not be supplied. Moreover, the semicon­ductor memory device has to employ a larger chip in accordance with an increase of the capacity of the device. Therefore, the power-supply line 4 and the grounding line 5 arranged around the memory cell arrays 2 and 2′ have been lengthened year by year. In accor­dance with this tendency, an increase in the resistance of the wiring lines has become a problem. In other words, the power-supply line 4 and the grounding line 5 arranged around the memory cell arrays 2 and 2′ have to be widened in accordance with the increase in the capa­city. Since, therefore, the power-supply line 4 and the grounding line 5 require a wide installation area, the size of the semiconductor chip is difficult to reduce.
  • The present invention has been developed to solve the problems mentioned above, and its object is to pro­vide a semiconductor memory device, wherein a power-­supply line and a grounding line occupy only a very small installation area even in the case where they are arranged in the regions around the memory cell array regions, and wherein a power-supply or ground potential can be supplied in a stable manner even to the ter­minating ends of the power-supply and grounding lines.
  • To achieve this object, the present invention pro­vides a semiconductor memory device which comprises: a memory cell array region; a plurality of signal lines arranged above the memory cell array region; and a plurality of power-supply lines and grounding lines regularly arranged between the signal lines in a similar pattern to that of the signal lines.
  • The present invention also provides a semiconductor device which comprises: at least two memory cell array regions; a peripheral circuit region located between the memory cell array regions; a plurality of signal lines arranged above the memory cell array regions; and a plurality of power-supply lines and grounding lines which are regularly arranged between the signal lines in a similar pattern to that of the signal lines and which are connected to the peripheral circuit region.
  • This invention can be more fully understood from the following detailed description when taken in con­junction with the accompanying drawings, in which:
    • Fig. 1 is a schematic view showing how a power-­supply line and a grounding line are arranged in a con­ventional semiconductor memory device;
    • Fig. 2 is a schematic view showing how a power-­supply line and a grounding line are arranged in a semi­conductor memory device according to one embodiment of the present invention,
    • Fig. 3 is an enlarged schematic view showing how the power-supply line and the grounding line are arranged above a memory cell array region; and
    • Fig. 4 is a schematic view of a 16-M DRAM to which the semiconductor memory device of the embodiment is applied.
  • One embodiment of the present invention will now be described in detail, with reference to the accompanying drawings.
  • Fig. 2 is a schematic view showing how a power-­supply line and a grounding line are arranged in the embodiment of the present invention. In Fig. 2, reference numeral 11 denotes a semiconductor chip; 12 and 12′ denote memory cell array regions, respectively; 13 denotes a peripheral circuit region; 14 denotes a power-supply pad; 15 denotes a grounding pad; d1, d2, ... dn denote power-supply lines, respectively; and s1, s2, ... sn denote grounding lines, respectively.
  • As is shown in Fig. 2, the semiconductor chip 12 has e.g. two memory cell array regions 12 and 12′. The peripheral circuit region 13 is located between these two memory cell array regions 12 and 12′. In the regions located around the memory cell array regions 12 and 12′, a bonding pad region is formed. The power-­supply pad 14 and the grounding pad 15 are connected to this bonding pad region.
  • The power-supply lines d1, d2, ... dn are connected at one end to the power-supply pad 14 and are regularly arranged above the memory cell array regions 12 and 12′. It should be noted that the power-supply lines d1, d2, ... dn are electrically connected not to memory cell arrays but to the peripheral circuit region 13 located between the memory cell array regions 12 and 12′. It is preferable that the power-supply lines d1, d2, ... dn be connected together above the peripheral circuit region 13. If necessary, the power supply lines d1, d2, ... dn may be also connected together at their terminating ends.
  • The grounding lines s1, s2, ... sn are connected at one end to the grounding pad 15 and are regularly arranged above the memory cell array regions 12 and 12′. It should be noted that the grounding lines s1, s2, ... sn are electrically connected not to the memory cell arrays but to the peripheral circuit region 13. It is preferable that the grounding lines s1, s2, ... sn be connected together on the peripheral circuit region 13. If necessary, the grounding lines s1, s2, ... sn may be also connected together at their terminating ends.
  • In the wiring arrangement mentioned above, the power-supply lines d1, d2, ... dn and the grounding lines s1, s2, ... sn, which are arranged above the memory cell array regions 12 and 12′, are connected to the peripheral circuit region 13 located between the memory cell array regions 12 and 12′. With this arrangement, the power-supply and grounding lines do not require a wide installation area in the regions around the memory cell array regions 12 and 12′; the installa­tion area can be narrow as long as the power-supply and grounding lines allow a sufficient power-supply or ground potential to an input protection circuit or other circuits. That is, the installation area around the memory cell array regions 12 and 12′ can be reduced, thus enabling the use of a small-sized chip.
  • Moreover, each of the power-supply lines d1, d2, ... dn need not be widened since the number of power­supply lines d1, d2, ... dn can be increased instead. Likewise, each of the grounding lines s1, s2, ... sn need not be widened since the number of grounding lines s1, s2, ... dn can be increased instead. Accordingly, the impedance of each power-supply line and that of each grounding line are low. As a result, a stable power-­supply potential can be supplied even to the terminating ends of the power-supply lines d1, d2, ... dn, and a stable ground potential can be supplied even to the ter­minating points of the grounding lines s1, s2, ... sn.
  • In the case where the input protection circuit and other circuits are not formed around the memory cell array regions 12 and 12′, the power-supply lines d1, d2, ... dn and the grounding lines s1, s2, ... sn need not be arranged around the memory cell array regions 12 and 12′. Accordingly, the installation area for them can be completely eliminated from around the memory cell array regions 12 and 12′.
  • Fig. 3 is a schematic view which illustrates, in a large scale, the power-supply and grounding lines arranged above one memory cell array region. In Fig. 3, reference numeral 16 denotes a column-selecting line; 17 denotes a contact hole through which the column-­selecting line 17 and a memory cell array are connected to each other; dk denotes a power-supply line; sk deno­tes a grounding line.
  • As is shown in Fig. 3, the column-selecting lines 16 (i.e., signal lines) are regularly arranged on the memory cell array region 12, and are connected to the memory cell array through the contact holes 17. The power-supply line dk and/or the grounding line sk are regularly arranged between the adjacent ones of the column-selecting lines 16 in a similar pattern to that of the column-selecting lines 16. For example, the power-supply line dk and the grounding line sk are alternately arranged between the column-selecting lines 16. It should be noted that the power-supply line dk and the grounding line sk are not connected to the memory cell array.
  • As mentioned above, the power-supply lines dk and the grounding lines sk are regularly arranged in a simi­lar pattern to that of the column-selecting lines 16. With this arrangement, the power-supply and grounding lines dk and sk arranged above the memory cell array region 12 do not result in a dispersion in the parasitic capacitance of bit lines formed under the column-selecting lines 16. Since, therefore, little noise is generated in the bit lines, the reading of information is in no way adversely affected.
  • The power-supply line dk and the grounding line sk need not be alternately arranged; both of them may be regularly arranged between the adjacent ones of the column-selecting lines 16. Even where both the power-­supply line dk and the grounding line sk are arranged between two adjacent column-selecting lines 16, the advantages arising from this arrangement are substan­tially the same. Moreover, the power-supply line dk and the grounding line sk may be arranged between column signal reading/writing lines or the like, not between the column-selecting lines 16.
  • Fig. 4 is a schematic view showing a 16-M DRAM to which the semiconductor memory device of the embodiment is applied. In Fig. 4, reference numeral 21 denotes a semiconductor chip; 22 denotes a peripheral circuit region; 23 denotes a memory cell array; 24 denotes a column decoder region; 25 denotes a row decoder region; 26 denotes a grounding pad; 28 denotes a grounding line; and 29 denotes a column-selecting line.
  • In the embodiment mentioned above, both the power-supply lines d1, d2, ... dn and the grounding lines s1, s2, ... sn are arranged above the memory cell array regions 12 and 12′. However, either the power-­supply lines d1, d2, ... dn or the grounding lines s1, s2, ... sn may be arranged above the memory cell array regions 12 and 12′. Moreover, the power-supply lines d1, d2, ... dn may be applied with a power-supply poten­tial reduced inside the chip, instead of being applied with a power-supply potential supplied from the power-­supply pad 14.
  • Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims (20)

1. A semiconductor memory device comprising:
a memory cell array region (12);
a plurality of signal lines (16) arranged above the memory cell array region; and
a plurality of power-supply lines (dk) or grounding lines (sk), each of which has a first end and a second end and which are arranged between the signal lines in a similar pattern to that of the signal lines.
2. A semiconductor memory device according to claim 1, characterized in that said plurality of power-­supply lines or grounding lines are regularly arranged between the signal lines.
3. A semiconductor memory device according to claim 1, characterized in that said first ends of the power-supply lines are connected to one another, while said second ends of the power-supply lines are connected to one another.
4. A semiconductor memory device according to claim 1, characterized in that at least one of the first and second ends of each power-supply line is connected to a power-supply pad (14).
5. A semiconductor memory device according to claim 1, characterized in that said first ends of the grounding lines are connected to one another, while said second ends of the grounding lines are connected to one another.
6. A semiconductor memory device according to claim 1, characterized in that at least one of the first and second ends of each grounding line is connected to a grounding pad (15, 28).
7. A semiconductor memory device according to claim 1, characterized in that said power-supply lines or said grounding lines are alternately arranged between the signal lines.
8. A semiconductor memory device according to claim 1, characterized in that said signal lines are column-selecting lines.
9. A semiconductor memory device according to claim 1, characterized in that said signal lines are column signal reading/writing lines.
10. A semiconductor device comprising:
at least two memory cell array regions (12, 12′);
a peripheral circuit region (13) located between the two memory cell array regions;
a plurality of signal lines (16) arranged above the memory cell array regions, and
a plurality of power-supply lines (d1, d2 ... dn, dk) or grounding lines (s1, s2 ..., sn, sk), each of which has a first end and a second end, said power-­supply and grounding lines being arranged between the signal lines in a similar pattern to that of the signal lines and being connected to the peripheral circuit region.
11. A semiconductor memory device according to claim 10, characterized in that said plurality of power-­supply lines or grounding lines are regularly arranged between the signal lines.
12. A semiconductor memory device according to claim 10, characterized in that said first ends of the power-supply lines are connected to one another, while said second ends of the power-supply lines are connected to one another.
13. A semiconductor memory device according to claim 10, characterized in that at least one of the first and second ends of each power-supply line is con­nected to a power-supply pad (14).
14. A semiconductor memory device according to claim 10, characterized in that said first ends of the grounding lines are connected to one another, while said second ends of the grounding lines are connected to one another.
15. A semiconductor memory device according to claim 10, characterized in that at least one of the first and second ends of each grounding line is con­nected to a grounding pad (15, 28).
16. A semiconductor memory device according to claim 10, characterized in that said power-supply lines are connected to one another above the peripheral cir­cuit region.
17. A semiconductor memory device according to claim 10, characterized in that said grounding lines are connected to one another above the peripheral circuit region.
18. A semiconductor memory device according to claim 10, characterized in that said power-supply lines or said grounding lines are alternately arranged between the signal lines.
19. A semiconductor memory device according to claim 10, characterized in that said signal lines are column-selecting lines.
20. A semiconductor memory device according to claim 10, characterized in that said signal lines are column signal reading/writing lines.
EP90120126A 1989-10-19 1990-10-19 Semiconductor memory device Expired - Lifetime EP0423825B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1270381A JPH07114259B2 (en) 1989-10-19 1989-10-19 Semiconductor memory device
JP270381/89 1989-10-19

Publications (3)

Publication Number Publication Date
EP0423825A2 true EP0423825A2 (en) 1991-04-24
EP0423825A3 EP0423825A3 (en) 1992-03-04
EP0423825B1 EP0423825B1 (en) 1995-12-13

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EP90120126A Expired - Lifetime EP0423825B1 (en) 1989-10-19 1990-10-19 Semiconductor memory device

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US (1) US5231607A (en)
EP (1) EP0423825B1 (en)
JP (1) JPH07114259B2 (en)
KR (1) KR940001288B1 (en)
DE (1) DE69024167T2 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2758504B2 (en) * 1990-07-06 1998-05-28 松下電器産業株式会社 Semiconductor storage device
JP3082323B2 (en) * 1991-07-30 2000-08-28 ソニー株式会社 Memory module
US5325336A (en) * 1992-09-10 1994-06-28 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having power line arranged in a meshed shape
JP3354231B2 (en) * 1993-09-29 2002-12-09 三菱電機エンジニアリング株式会社 Semiconductor device
JPH08195083A (en) * 1995-01-17 1996-07-30 Toshiba Microelectron Corp Semiconductor memory
JPH0955482A (en) * 1995-06-08 1997-02-25 Mitsubishi Electric Corp Semiconductor memory device
JP3556388B2 (en) * 1996-04-23 2004-08-18 株式会社 沖マイクロデザイン Semiconductor memory device
US5936877A (en) 1998-02-13 1999-08-10 Micron Technology, Inc. Die architecture accommodating high-speed semiconductor devices
JP4212171B2 (en) * 1999-01-28 2009-01-21 株式会社ルネサステクノロジ Memory circuit / logic circuit integrated system
US7388289B1 (en) * 1999-09-02 2008-06-17 Micron Technology, Inc. Local multilayered metallization
US6574711B2 (en) * 1999-12-27 2003-06-03 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit
JP2012252762A (en) * 2011-06-07 2012-12-20 Elpida Memory Inc Semiconductor device
KR102601866B1 (en) 2019-01-16 2023-11-15 에스케이하이닉스 주식회사 Semiconductor device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0041844A2 (en) * 1980-06-10 1981-12-16 Fujitsu Limited Semiconductor integrated circuit devices
GB2087183A (en) * 1980-11-07 1982-05-19 Hitachi Ltd Semiconductor integrated circuit device
EP0081368A2 (en) * 1981-12-07 1983-06-15 Fujitsu Limited A semiconductor memory device
US4525809A (en) * 1981-01-26 1985-06-25 Nippon Electric Co., Ltd. Integrated circuit
US5007025A (en) * 1988-07-21 1991-04-09 Samsung Electronics Co., Ltd. Power and signal line bussing method for memory devices

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR900006221B1 (en) * 1984-11-15 1990-08-25 후지쓰 가부시끼가이샤 Semiconductor memory device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0041844A2 (en) * 1980-06-10 1981-12-16 Fujitsu Limited Semiconductor integrated circuit devices
GB2087183A (en) * 1980-11-07 1982-05-19 Hitachi Ltd Semiconductor integrated circuit device
US4525809A (en) * 1981-01-26 1985-06-25 Nippon Electric Co., Ltd. Integrated circuit
EP0081368A2 (en) * 1981-12-07 1983-06-15 Fujitsu Limited A semiconductor memory device
US5007025A (en) * 1988-07-21 1991-04-09 Samsung Electronics Co., Ltd. Power and signal line bussing method for memory devices

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
IEEE TRANSACTIONS ON ELECTRON DEVICES. vol. 26, no. 4, April 1979, NEW YORK US pages 333 - 334; COOK E.A.: '1 MICROMETER MOSFET VLSI TECHNOLOGY:PART 3;LOGIC CIRCUIT DESIGN METHODOLOGY AND APPLICATIONS.' *
MASSENGILL E.A. 'NASECODE 4;PROCEEDINGS OF THE 4TH INTERNATIONAL CONFERENCE ON NUMERICAL ANALYSIS OF SEMICONDUCTOR DEVICES AND INTEGRATED CIRCUITS;' 19 June 1985 , MILLER , DUBLIN;IRELAND VOLTAGE SPAN FOR VERY LARGE MEMORY ARRAYS;P.396-404 *
REVIEW OF THE ELECTRICAL COMMUNICATION LABORATORIES. vol. 26, no. 9,10, September 1978, TOKYO JP pages 1355 - 1366; WADA E.A.: 'MASTER SLICE LAYOUT DESIGN FOR EMITTOR-COUPLED LOGIC LSI' *

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KR910008836A (en) 1991-05-31
EP0423825B1 (en) 1995-12-13
JPH03133174A (en) 1991-06-06
JPH07114259B2 (en) 1995-12-06
DE69024167T2 (en) 1996-05-30
DE69024167D1 (en) 1996-01-25
US5231607A (en) 1993-07-27
EP0423825A3 (en) 1992-03-04
KR940001288B1 (en) 1994-02-18

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