EP0420584A2

EP0420584A2 - PLL demodulating circuit in traffic information receiver

Info

Publication number: EP0420584A2
Application number: EP90310493A
Authority: EP
Inventors: Koichi C/O Pioneer Electronic Corporation Kasa; Toshihito C/O Pioneer Electronic Co. Ichikawa
Original assignee: Pioneer Electronic Corp
Current assignee: Pioneer Corp
Priority date: 1989-09-27
Filing date: 1990-09-25
Publication date: 1991-04-03
Anticipated expiration: 2010-09-25
Also published as: EP0420584B1; EP0420584A3; JPH0736532B2; DE69023729D1; JPH03113921A

Abstract

In a traffic information receiver, the total of the locking ranges of a PLL circuit (17 for demodulating an SDK signal and a PLL circuit (10) for demodulating a DK signal is so determined as not to exceed the difference between the maximum frequency of the BK signal and the frequency of the DK signal. Even under an influence by a multi-path phenomenon, such a situation can be avoided that the locking frequency of the PLL circuit ( 10) for DK coincides with the frequency of the BK signal to cause erronous detection of the BK signal.

Description

The present invention relates to a PLL (phasr locked loop) demodulating circuit in a traffic information receiver.
There has been known a traffic information bradcasting system which supplies traffic information in such a manner as a time-sharing during a normal program of a braodcasting station for listeners to a car radio or the like. In the particular system, a subcarrier of 57 kHz equal to a ternary harmonic of a stereoponic pilot signal of 19 kHz is used as a traffic information station ID signal (hereinafter, referred to as an SK signal) indicative of a broadcasting station of traffic information, the subcarrier frequency being out of the FM carrier band. During broadcasting of the traffic information, the subcarrier of 57 kHz amplitude modulated by a region ID signal (having one of the frequencies of from 23.75 Hz to 53.98 Hz which are equal to the values of the integer fractions of 57 kHz; this signal is hereinafter referred to as a BK signal) respectively designating a region the traffic information relates to and, further, by a message ID signal (a single tone of 125 Hz; this signal is referred to as a DK signal hereinafter) indicating that the traffic information is at present being broadcasted. The amplitude modulated subcarrier modulates in frequency a main FM carrier which is transmitted as a traffic information broadcasting wave. Fig. 3(a) shows a frequency spectrum of the above signals. Fig. 3(b) shows a base band after the demodulation.
When a receiver receives the traffic information broadcasting wave it performs FM detection to produce a detection output, from which the SK signal is demodulated by a PLL circuit of 57 kHz and, further, -the DR signal is demodulated by a PLL circuit of 125 Hz from the demodulated output. Generally, a VCO (voltage controlled oscillator) in the PLL circuit of 57 kHz has a locking range of about 1 % (± 600 Hz) as shown in Fig. 4(a). On the other hand, a VCO in the PLL circuit of 125 Hz has a locking range of about ± 10 Hz as shown in Fig. 4(b).
It is now assumed that the DR signal does not exist and, on the other hand, the SK and BK signals exist. At this time, if the oscillating frequency of the VCO of the P11 circuit for the SR signal is deviated from the frequency of the SR signal and is shifted, for instance, upward due to an influence by a multi-path phenomenon or the like, the difference between the lower BR signal frequency and the oscillating frequency of the VCO is equal to about 125 kHz of the DR signal as shown in Fig. 5(a). Therefore, there is a case where as shown in Fig. 5(b), the BR signal after the demodulation lies within a locking range of the PLL circuit for the DR signal and is locked into the particular PLL circuit, thereby causing erroneous detection of, the BK signal.
The present invention is made in view of the foregoing problem and it is an object of the invention to provide a PLL demodulating circuit in a traffic information receiver in which a demodulated BR signal is not locked into a PLL circuit for DK signal even if an influence by a multi-path phenomenon or the like is exerted.
According to the present invention, there is provided a PLL demodulating circuit in a traffic information receiver which can receives an FM carrier wave carrying a subcarrier which is first ID signal indicative of a broadcasting station of traffic information is amplitude modulated by a second ID signal indicating to which region the traffic information related and by a third ID signal indicating that the traffic information is being broadcasted, the amplitude modulated subcarrier being carried by a main FM carrier. The receiver includes a first PLL circuit for demodulating the first ID signal from a detection output which is obtained by FM detection and a second PLL circuit for demodulating the third ID signal from a demodulated output of the first PLL circuit, and assuming that the maximum frequency of the second ID signal is equal to BR and a frequency of the third ID signal is equal to DR, locking ranges Δ f_SK and Δ f_DK of the first and second PLL circuits are so determined as to satisfy a condition of
(DK - BK) > (Δ f_SK + Δ f_DK).
In other words, the PLL demodulating circuit according to the present invention, the total of the locking ranges of the first and second PLL circuits is not larger than the difference between the maximum frequency of the BK signal as a second ID signal and the frequency of the DK signal as a third ID signal.
In the drawings,

Fig. 1 is a block diagram showing an outline of a fundamental construction of a FM multiplex broadcasting receiver which can receive a traffic information broadcasting;
Fig. 2 is a block diagram showing a construction of a costas loop type PLL circuit;
Fig. 3 is a diagram showing a frequency spectrum (a) of an SDK signal and a base band (b) after the demodulation;
Fig. 4 is a diagram showing each of locking ranges of PLL circuits 7 and 10; and
Fig. 5 is a diagram showing a state (a) in which an oscillating frequency of a VCO is deviated from a frequency of an SK signal due to an influence by a multipath and a state (b) in which the difference between the BK signal frequency and an oscillating frequency of the VCO is equal to about a DK signal frequency due to the frequency deviation.

An embodiment of the invention will be described in detail hereinbelow with reference to the accompanying drawings.
Fig. 1 is a block diagram showing an outline of a fundamental construction of an FM multiplex broadcasting receiver which can receive a traffic information broadcasting. The receiver can also receive an FM broadcasting wave in a radio data system which is so-called as RDS.
The radio data system is a system in which a broadcasting station braodcasts during a usual program a data signal having, information indicative of the kind of program content by means of a multiplex modulation and, a desired program content can be selected on the basis of the demodulated data on the reception side, that is, a radio listener. In the radio data system, a signal of 57 kHz is set to a subcarrier, the subcarrier of 57 kHz is amplitude modulated into the radio data signal by a data signal indicative of a program content which has been filtered and biphase encoded, and the amplitude modulated subcarrier is carried by the main carrier which is broadcasted.
As mentioned above, since the subcarrier of 57 kHz is used in both of the radio data system and the traffic information broadcasting system, in the radio data system, in order to distinguish the subcarrier (hereinafter, referred to as an RDS signal) which was amplitude modulated by the data signal from the subcarrier (hereinafter, referred to as an SDS signal) which was amplitude modulated by the data signal from the subcarrier (hereinafter, referred to as an SDK signal) which was amplitude modulated by the DK signal of the traffic information broadcasting system, the RDS signal has a phase difference of about π/2 for the SDR signal.
In Fig. 1, an FM multiplexed broadcasting wave which was received by an antenna 1 converted into an intermediate frequency (10.7 MHz) after a desired station has been selected by a front end 2. Thereafter, the converted signal is supplied to an FM detector 4 through an IF amplifier 3. A detection output of the FM detector 4 is supplied to an MPX (multiplex) demodulating circuit 5. In the case of a stereophonic broadcasting, the detection output is divided into audio signals of L (left) and R (right) channels.
On the other hand, the detection output of the FM detctor 4 passes through a filter 6, so that the RDS signal or SDR signal as a subcarrier of 57 kHz is extracted and supplied to a PLL circuit 7. In the PLL circuit 7, the RDS signal or SDR signal which has been extracted from the FM detection output is demodulated. The demodulated RDS signal is supplied to a digital (D) PLL circuit 8 and a decoder 9. The SDR signal is supplied to a PLL circuit 10 to demodulate the DK signal. The D-PLL circuit 8 produces clocks for data demodulation on the basis of the demodulated output of the PLL circuit 7. The produced clocks are supplied to the decoder 9 and are also used as clocks when a process such as an error correction or the like is executed for the output data of the decoder 9. In the decoder 9, the RDS signal as a demodulated output of the PLL circuit 7 is decoded synchronously with the clocks produced by the D-P11 circuit 8 and is output as data indicative of the kind of program content of the radio broadcasting. A locking state detecting circuit 11 detects a locking state and an unlocking state of the D-PLL circuit 8 and controls the switching operation between the locking ranges of the PLL circuit 7 and D-PLL circuit 8 on the basis of the detection output.
For instance, a costas loop type P11 circuit is used as a PLL circuit 7. Fig. 2 shows a construction of the costas loop type PLL circuit. In the diagram, in multipliers 21 and 22, the RDS signal or SDK signal is individually multiplied with an output signal of a VCO (voltage controlled oscillator) 23 and a signal whose phase has been delayed by only π/2 by passing the VCO output through a phase shifting circuit 24. The multiplied outputs are transmitted through LPFs (low pass filters) 25 and 26 and are multiplied by a mutiplier 27. A harmonic component in an error signal as an output signal of the multiplier 27 is eliminated by a loop filter 28 and the resultant signal is used as a control voltage of the VCO 23. The outputs of the multipliers 21 and 22 which have passed through the LPFs 25 and 26 are supplied to a selecting switch 29. The selecting switch 29 is switched by, for instance, a detection signal issued from an SDK detecting circuit 30 for detecting a DC component of the output of the multiplier 21 which has passed through the LPF 25, thereby selectively passing therethrough either one of the outputs of the multipliers 21 and 22. A selected output of the selecting switch 29 is derived as demodulated data. On the ther hand, the output of the multiplier 21 which has passed through the LPF 25 is extracted as an SDK signal and supplied to the PLL circuit 10 for DK (shown in Fig. 1).
The operation of the PLL circuit 7 with the construction mentioned above has been disclosed in detail in JP-A-63-87052.
It is now assumed that the maximum change amount for the SK signal of the VCO 23 in the PLL circuit 7, that is, a locking range of the PLL circuit 7 is set to Δ f_SK, the maximum change amount for the DK signal of the VCO (not shown) in the PLL circuit 10, that is, a locking range of the PLL circuit 10 is set to Δ f_DK, the mzximum frequency (53.98 Hz) of the BK signal is set to BK, and the frequency (125Hz) of the DK signal is set to DK. In this case, the locking ranges Δ f_SK andΔ f_DK of the PLL circuits 7 and 10 are determined so as to satify a condition of
(DK - DB) > (Δ f_SK + Δ F_DK)
To satisfy the above condition, for instance, a digital PLL construction is formed by using a high accurate oscillator such as a crystal oscillator or the like as an oscillating source of a reference frequency of the PLL circuit 7 of 57 kHz and its locking range is set to about ± 15 Hz. Since the PLL circuit 10 of 125 Hz generally has a locking range of about ± 10 Hz as mentioned above, the difference between the maximum frequency of the DK signal and the maximum frequency of the BK signal is as follows
(DK - BK ≒ 71
(Δ f_SK + Δ f_DK) ≒ 25
even if it is influenced by the multi-path phenomenon. Accordingly, the BK signal after the demodulation does not fall into the locking range of the PLL circuit 10 for DK.
As described above, in the PLL demodulating circuit according to the present invention, assuming that the locking range of the PLL circuit of 57 kHz to demodulate the SDK signal from the FM detection output is set to Δ f_SK, the locking range of the PLL circuit of 125 Hz to demodulate the DK signal from the PLL demodulated output is set to Δ f_DK, the maximum frequency of the BK signal is set to BK, and the frequency of the DK signal is set to DK, the locking ranges Δ f_SK and Δ f_DK of the PLL circuits are determined so as to satisfy the condition of
(DK - BK) > (Δ f_SK + Δ f_DK)
Therefore, the BK signal after the demodulation does not fall into the PLL circuit for DK of 125 Hz even if it is influenced by the multi-path noises or the like.

Claims

1. A PLL demodulating circuit in a traffic information receiver which can receive an FM carrier wave carrying thereon a subcarrier which is a first ID signal indicative of a broadcasting station of traffic information is amplitude modulated by a second ID signal indicating to which region the traffic information ralates and by a third ID signal indicating that the traffic information is being broadcasted, which comprising:
a first PLL circuit for demodulating the first ID signal from a detection output which is obtained by FM demodulation of the received FM carrier; and
a second PLL circuit for demodulating the third ID signal from a demodulated output of the first PLL circuit,
wherein assuming that maximum frequency of the second ID signal is equal to BK and a frequency of the third ID signal is equal to DK, locking ranges Δ f_SK and Δ f_DK of the first and second PLL circuits are so detertined so as to satisfy a condition of
(DK - BK) > (Δ f_SK + Δ f_DK).