EP0417547B1 - Means for obtaining the exact limits of a time interval related to a clock reference - Google Patents

Abstract

The invention relates to a means for obtaining electronically the exact limits of a time interval related to a clock reference, where the beginning and end of the interval can in each case be identified and measured by means of an event. To determine the exact limits of the time interval, a comparator (8) is provided whose current outputs are fed directly to a current latch (9), which is furthermore also driven by the clock reference, in which the instantaneous clock status is passed through or frozen in the current range with the aid of minimal voltage levels. <IMAGE>

Description

During the development of an electronic device, e.g. for measurement technology, the problem often arises of measuring a time interval. Integrating digital-to-analog converters are widespread (e.g. in digital voltmeters). A capacitor is first charged for a constant time with a current proportional to the analog value to be measured. Then it is discharged again with a constant current up to the initial value. The time required for this is the measure for the analog value. Another example is measuring the transit time that an ultrasound pulse takes to get from the emission level of the transmitter to the receiving level of the receiver.

• einem Oszillator (Taktgeber),
• einem Frequenzteiler (Untersetzungsgetriebe) und
• einer Start-Stop-Einrichtung dazwischen

zur zeitlichen Ermittlung der Grenzen des die Laufzeit charakterisierenden Zeitintervalls, die durch ein elektrisches Signal oder mehrere solcher Signale, beispielsweise über einen Komparator oder mehrere Komparatoren, möglich sind.In both cases you need an electronic stopwatch to measure the running time precisely. In principle, this works like a mechanical one and consists of

• an oscillator (clock generator),
• a frequency divider (reduction gear) and
• a start-stop facility in between

for the temporal determination of the limits of the time interval characterizing the transit time, which are possible by means of an electrical signal or a plurality of such signals, for example via a comparator or a plurality of comparators.

The possibility of starting and stopping the oscillator itself is not considered here, since precise time measurements are only possible with steady oscillators.

In the practical implementation of an electronic start-stop device Metastable flip-flop states are possible at the input of a frequency divider. These must be prevented using suitable aids. Metastable conditions and their causes as well as measures to reduce the probability of their occurrence in the construction of an edge-controlled flip-flop are described in European patent application EP-A-0 308 623.

1, with a simple AND gate 1 between a comparator 2 for generating the time interval from the event pulses with respect to a reference voltage on the one hand and an oscillator 3 for generating the clock pulses on the other hand and a frequency divider, one can short-lived clock pulse bring the counter stages CL1 to CL4 designed as a divider flip-flop 4 with the outputs D0 to D3 into a metastable state. As a result, an unknown number of vibrations then reach the counter stages and falsify the measurement result.

2, a low-pass filter 5 and a Schmitt trigger 6 are therefore arranged between the AND gate 1 and the frequency divider 4. This solves the problem, but the clock frequency must inevitably be much lower than that theoretically possible by the AND gates 1 and flip-flops CL1 to CL4 used.

The circuit according to FIG. 3 shows a digital alternative, in which the signal for the time interval before the AND gate is synchronized with the inverted clock by means of an auxiliary flip-flop 7. The clock frequency is to be chosen so low that possible metastable states of the auxiliary flip-flop 7 have decayed in the inactive clock phase.

It also follows from what has been said so far that the achievable accuracy in the time interval measurement is limited not only by the measures necessary to exclude metastable states, but also by the period of the cycle. A high Clock frequency is advantageous, but, as the examples mentioned show, it encounters difficulties in practice. This is especially true for devices that have to work with low power consumption and therefore with the lowest possible working frequency.

In many cases it is possible to synchronize the start of the interval with the clock. This is helpful, but in the end there is still the error portion of a clock period.

The circuit according to FIG. 4 can bring about a possible improvement. Instead of the AND gate, a current-state-controlled bistable multivibrator, a so-called transparent current latch 9, serves as a switch for the clock. This is followed by low pass 5 and Schmitt trigger 6 again in order to screen out possible metastable vibrations of the latch 9. At the end of the time interval, the state of the clock ("0" or "1") is also recorded and the time resolution of the measurement is approximately doubled. In contrast, there is again the disadvantage that the usable clock frequency must be considerably lower than that which the latch 9 could switch.

• das Ende des Zeitintervalls (und eventuell auch dessen Beginn) so genau wie möglich zu erfassen,
• die theoretisch mögliche Taktfrequenz trotz der gebotenen Rücksicht auf das Ausschließen des Einflusses metastabiler Zustände voll ausnutzbar zu machen,
• nach dem Ende des Zeitintervalls ein Maß für die augenblickliche Phasensituation des Taktes zu speichern und dabei nicht nur eine digitale ("0" oder "1"), sondern auch die analoge Komponente des Zeitintervalls in einer "0" oder "1" Periode zu erfassen.

The object of the invention is:

• to capture the end of the time interval (and possibly also the beginning of it) as precisely as possible,
• to make the theoretically possible clock frequency fully usable despite the necessary consideration for excluding the influence of metastable states,
• after the end of the time interval to save a measure of the instantaneous phase situation of the clock and not only to capture a digital ("0" or "1"), but also the analog component of the time interval in a "0" or "1" period .

This object is achieved by the invention specified in claim 1.

Advantageous developments of the invention according to claim 1 are described in the subclaims and in the exemplary embodiment below.

5 shows a basic illustration of the arrangement according to the invention. A comparator 8 with current outputs, which are fed directly to the current latch 9, is used to determine the exact limits of the time interval. Further current outputs of the comparator reacting in parallel are provided in order to control an analog fine evaluation stage 10 and a mixer 11. Current-voltage converters 12, 13, 14 generate the voltage levels necessary for the logical further processing. A clock driver 15 generates the clock signals in phase opposition.

To solve the tasks, the necessary data manipulations are carried out without going through voltage levels, the generation of which takes up valuable time because of the stray capacities that are always present. The current cycle state is frozen in the current range with the aid of minimal voltage levels. The amount of time until the next clock edge arises as an analog charging voltage with a current that always starts at exactly the same moment in a capacitor. The mixer monitors the correspondence of the clock phases at the outputs of the current latch 9 already in the current range with the clock phases at the input.

After the arrangement is primarily intended for integration within an integrated circuit using bipolar or MOS technology, its circuit parts are explained below at the transistor level. The bipolar transistors that are more common in analog circuits are used in the circuit examples. However, they allow any specialist to implement them easily, for example in C-MOS. Because of the better overview, the entire arrangement is also broken down into small functional blocks, some of which are shown in simplified form. It goes without saying that additional measures, for example to compensate for the Miller effect, may be necessary for current-voltage transitions.

The circuit principle of the comparator 8 is shown in FIG. 6. It consists of a conventional PNP transistor differential stage T1, T2 with the signal input "Event" and the reference input "U _ref ", the outputs of which are loaded by NPN multiple current mirrors. These, in turn, provide the required current outputs. A complementary pair T5, T11 together with the current mirror T12, T13 form a current-voltage converter and provide a voltage output signal "KOMP". Another pair of T4, T10 supplies the currents I _clock and I _latch for supplying the current latch 9, a single output T3 supplies the analog fine evaluation with the current I _ramp and a further pair of transistors T6, T9 effect a positive feedback, which is in the switching range of Comparator 8 provides an infinitely large gain (especially without hysteresis) and ensures that each output current starts immediately with 50% of its final value when switching or switches off immediately below 50%.

Fig. 7 shows the basic circuit structure of the current latch 9. The latch function is similar to that in a circuit shown in the book "Semiconductor Circuit Technology" by Tietze and Schenk, 1989, page 776, with complementary voltage outputs, but with transistors connected as diodes instead of the load resistors that form the voltage outputs in the known example, control several current outputs.

The clock is at the inputs of a first transistor differential stage T14 and T15 in the form of the components CL1 and CL2 in phase opposition and, as long as I _clock flows and I _latch does not, causes the current outputs I _mix 1 at T19 and I _mix 2 at T20. Further current outputs of the transistors T18 and T21 following the clock generate a single-phase voltage output via the current-voltage conversion with the current mirror from the transistors T23 and T24, which, for example, can directly drive a frequency divider. The latch is therefore switched to pass (transparent). If the current conditions are _reversed (I _latch begins to flow and I _clock is switched off), the second transistor differential stages T16 and T17 become active, and the current one (still) is set Clock phase position by comparing the minimum voltage difference across the transistors connected as diodes and reinforces this tendency through the positive feedback caused by their cross-coupled outputs. The current clock phase state is thus "frozen", the latch is closed.

The current latch functions in the current range and the result is initially flowing or frozen currents. Only very small voltage changes occur and extremely small delays in the logical operation due to parasitic capacitances. For the logical further processing, for example in a frequency divider, the current state corresponding to or recorded in the input clock is made evaluable by a current-voltage conversion, the switching delays due to technical reasons becoming fully effective again. This is not a disadvantage, because data manipulation has followed long before. The low-pass function described in FIG. 4 is thereby realized in a very advantageous manner. A Schmitt trigger is not necessary because the slope steepness already corresponds to the usual in the chosen technique.

The solution to the last problem posed by the invention, namely the storage of an analogue measure for the instantaneous time within a clock phase, will now be explained. When the comparator is switched over, the current I _ramp also starts. Thus, one of the capacitors C1 or C2 is charged in the analog fine evaluation (FIG. 9), controlled by the phase-phase clock components. The next time the clock phases change, the charging current jumps to the other capacitor. Now, however, and absolutely before the next change of the clock phases, something has to happen, because the measure for the phase situation of the clock is in the first capacitor and would be falsified after a further jump in the charging current.

It is now a matter of obtaining a clear control signal for a switch which is not further explained, with which the charging current can be completely switched off. The criterion is the first clock phase change after the clock freezes in the latch, ie the deviation of the clock manipulated in the latch from the original clock. The first clock phase change is determined with the aid of a mixer (FIG. 8); the fact of freezing is known to the comparator 8. The AND combination of the signals KOMP and MIX thus provides the above criterion.

For further clarification, reference is made to the time diagrams in FIG. 10. The evaluation of the voltage in the first capacitor (which it shows shows the frozen clock phase) then brings a multiple increase in the resolution of the time measuring device. The improvement is only limited by the fact that the ramp current I _ramp only starts with 50% of its final value. Thus the ramp becomes nonlinear at the beginning and this nonlinearity is a function of the slope of the end of interval signal at the comparator. This means that the compensation options for non-linearity are also limited.

The capacitor voltage is expediently evaluated by back-integration with a constant current and measuring the time with a similar arrangement and a frequency divider or the same arrangement together with a multiplexer

The previous considerations essentially relate to determining the end of a time interval. With similar means, it is also possible to store and evaluate the instantaneous phase situation of the clock at the beginning when the interval is not synchronized, but the circuit complexity can double.

Claims (6)

1. Arrangement for the precise electronic detection of the limits of a time interval relative to a reference clock pulse, with it being possible to determine and measure beginning and end of the interval in each case by means of an event, characterised in that for the purpose of determining the precise limits of the time interval it (the arrangement) contains a comparator (8), the current outputs (I_clock and I_latch) of which are supplied directly to a current latch (9) which is activated, moreover, in addition by the reference clock pulse and the function of which is the result of flowing or frozen-in currents and in which the instantaneous clock pulse state is let through or frozen in in the current range with the aid of minimum voltage levels, in that the current state is made so that it can be evaluated by a current-voltage-converter (10) for a connected frequency divider (4), as the technically conditioned switching delays which become effective with delay are utilized to fade out possible metastable states, and in that the comparator (8) has a further current output (I_ramp) which at the instant of the switch-over of the comparator (8) begins to conduct current and therewith as a result of activation of an analog fine evaluation stage (10) generates an analog measure of the time until the next clock pulse edge.
2. Arrangement according to claim 1, characterised in that the comparator (8) has a positive feedback which in the switch-over range of the comparator supplies an infinitely great amplification (straight without hysteresis) and ensures that each output current in the case of the switch-over immediately starts with 50% of its final value and immediately switches off below 50%.
3. Arrangement according to claims 1 or 2, characterised in that the analog fine evaluation stage (10) is controlled by components of the original clock pulse in such a way that one of two capacitors (C₁, C₂) is charged and with the next change of the clock pulse phases the charging current jumps to, in each case, the other capacitor.
4. Arrangement according to the previous claims, characterised that the current latch (9) also has further current outputs which follow the manipulated current state.
5. Arrangement according to the previous claims, characterised in that a current output or a complementary pair of the current outputs of the current latch (9) activates a mixer (11), the other input of which is controlled by the original clock pulse so that a signal arises at the output of the mixer (11) when manipulated clock pulse and original clock pulse deviate from each other.
6. Arrangement according to the previous claims, characterised in that the output signal of the mixer (11) is also converted into the voltage range, and alone or together with the output signal of the comparator (8) it emits a signal to the logic circuit environment of the arrangement and/or interrupts the ramp current.

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