EP0403207A2

EP0403207A2 - Diagnostic subsystem

Info

Publication number: EP0403207A2
Application number: EP90306353A
Authority: EP
Inventors: Don Steven Keener; Andrew Boyce Mcneill; Kevin Lee Scheiern
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 1989-06-12
Filing date: 1990-06-11
Publication date: 1990-12-19
Also published as: EP0403207A3; JPH0695319B2; US5033049A; JPH0328949A

Abstract

A device adapter with an on-board diagnostic capability for a SCSI controller is provided by a gate array driven by a microprocessor on board the adapter. The gate array has data and control inputs driven from the micro-processor and data and control outputs which are dot OR'ed with corresponding in/out terminals of the SCSI controller. A reset signal from a SCSI bus forms a further input to the gate array. For testing purposes the micro-processor detects the gate array inputs to simulate a fault-free or faulty device. The micro-processor detects the response of the SCSI controller to the device simulation and thereby can determine the state of health of the SCSI controller.

Description

Field of the invention

This invention relates to testing devices complying with a specific standard, and more more particularly to a diagnostic subsystem with testing and diagnostic capability for devices such as a Small Computer System Interface (SCSI) controller.

Background of the Invention

Diagnostic sub-systems have, in the past, been used in at least two different applications. In one application, diagnostic systems and sub-systems have been used as a part of the manufacturing process. More particularly, after a product is manufactured it is connected to a diagnostic system or sub-system to insure that the manufactured device meets manufacturing specifications and is in condition for sale. In an entirely different application, diagnostic sub-systems have been included as part of computer systems. Typically such a board diagnostic sub-system is initiated into operation as part of the Power On Reset (POR) sequence each time the computer system is powered up or reset. The diagnostic sub-system performs a routine of tests and either allows normal processing to be commenced if the tests are successfully passed or reports some information about any tests which are not successfully completed.
One problem faced by the diagnostic sub-system designer is typified by the expandable nature of the Personal Computer (PC). More particularly the nature and complement of devices included in the computer system cannot be predicted. This unpredictability limits the extent and nature of the diagnostics. Prior art I/O devices, for example hard files, are associated with a device controller, and the device controller is usually tested with the device connected to the controller. Prior art ST506 and Enhanced Small Device Interface (ESDI) devices are examples of this architecture.
More recently, with the advent of the SCSI standard, logic which is dedicated to operation of devices such as a hard file has been moved from the controller to the hard file assembly itself. This leaves a generic interface which actually operates as a low cost network and is capable of supporting hard files, diskette drives, CD ROM drives, printers etc. This new architecture requires a completely different method of testing the SCSI controller from those used in the ST506 and ESDI arrangements. See in this regard, "Solving the Test Problem in SCSI Disk Drives" appearing in Electronics, page 35 at seq., February 17, 1986; Robinson, "SCSI Interface Demands New Test Methods," Mini-Micro Systems, page 35, April, 1988; Squires, "Out Smarting Smart Interfaces to Test Winchester Drives," Electronics Test, February, 1988; "Western Digital Slashes SCSI Bus Overhead Time" in Electronics, August 20, 1987 and Aseo, "Disc Interfacing Gets Smart," ESD: The Electronics System Design Magazine, page 77, November 1987.
A SCSI or generic interface can be used between a system, such as a Personal Computer system, and a plurality of devices coupled to the SCSI interface through a SCSI bus. Although in prior devices the hardware between a system and a peripheral device was identified as a controller, the hardware interfacing the computer system and the SCSI devices will hereinafter be referred to as a SCSI adapter. Thus the SCSI adapter has a port coupled to a first bus which is coupled to a port of the computer system. The SCSI adapter has a second port which is coupled to the SCSI bus and via that bus to one or more SCSI devices. Typically the SCSI adapter includes a SCSI controller as a component.
One problem raised by the SCSI interface is the inability to assume a particular configuration of devices connected on the SCSI bus. It is therefore not possible to select specific test procedures, for execution, based on a particular configuration. For example a configuration may involve a collection of printers, a collection of read only CD ROMS, a plurality of read/write hard files, or a combination of all of the above. Another possibility is that future configurations will include devices not yet available. The inability to assume a particular device configuration, coupled with the limitations a particular device may entail in testing many of the modes of operation, requires a new and effective test capability which is effectively independent of the devices connected on the SCSI bus.
A second problem is the necessity to isolate defects in the drives and receivers in the SCSI adapter or more particularly, the SCSI controller contained in the adapter. Often if the drivers and receivers are defective, the defects cannot be isolated between the adapter, the cable or the device.
A third problem is the testing environment. The test sub-system may operate in an environment in which it is not the autonomous bus master, this being particularly true of the SCSI environment. In the SCSI environment the adapter usually has the highest priority, but other devices may nevertheless attain control of the bus and that condition must be respected; furthermore there may be more than a single adapter on the bus. As a result the diagnostic sub-system must take into account the presence of other devices which may be connected on the bus. If the diagnostic sub-system assumes control of the SCSI bus, it may interfere with the operation of other bus users to the detriment of the entire system.

Disclosure of the invention

Accordingly the invention provides a diagnostic subsystem for use with an adapter, wherein said adapter is capable of controlling a variety of peripheral devices each designed to comply to a specific standard and includes a microprocessor and dedicated memory coupled thereto, and a controller coupled to said microprocessor and to a multiconductor bus, said diagnostic subsystem including:
a gate array coupled to said microprocessor and to said controller, and also coupled to said multiconductor bus; and
means responsive to a diagnostic command received at said device for selecting said controller and for generating and coupling, through said gate array, signals simulating the response of an attached peripheral device.
Typically the specific standard is the SCSI standard, in which case the adapter is a SCSI adapter, and the multiconductor bus and controller are a SCSI bus and SCSI controller respectively. Coupling the SCSI controller to the SCSI bus are eight data conductors, a data parity conductor, a C/D (commands/data) conductor, a MSG (message) conductor, an I/O (input.output) conductor, a SEL (select) conductor, a BSY (busy) conductor, a REQ (request) conductor, an ACK (acknowledge conductor, and a RST (reset) conductor. Dot OR'ed to the C/D, I/O, MSG, SEL, BSY, REQ, ACK, and parity conductors of the SCSI controller are the outputs of the gate array. This diagnostic gate array also has eight data output conductors which are dot OR'ed with the eight data conductors coupled to the SCSI controller data I/O terminals.
Preferably the diagnostic subsystem further includes means responsive to a diagnostic command for generating signals simulating the response of an attached peripheral device. It is further preferred that it is possible to simulate a faulty attached peripheral device, as well as one operating in a fault free mode.
Typically the diagnostic gate array affords the possibility for the controller to be exercised by diagnostic microcode with the outputs of the diagnostic gate array driven by the microprocessor to simulate the response of the attached peripheral device operating in either a fault-free mode or a purposely simulated fault mode, and generally in both modes. Simulating the response of a device attached to the multiconductor bus tests the arbitration, selection, re-selection and read/write functions of the controller. Testing can put the controller in both an initiator and target modess using DMA and automatic PIO methods where appropriate. The diagnostic microcode can also implement phase and parity testing. The diagnostic microcode also causes the device controller to select itself, thereby eliminating the possibility of corrupting the integrity of devices connected to the multiconductor bus.
Preferably the diagnostic subsystem further includes a plurality of register stages, each coupled to an input terminal of the gate array, first logic means responsive to command signals for enabling at least one of the register stages to store information representative of a signal appearing at the input terminal, and second logic means for coupling information stored in said at least one register stage to an output terminal. It is further preferred that the second logic means includes a reset terminal coupled to a reset signal carrying conductor in said multiconductor bus; and means responsive to an active reset signal for disabling the second logic means from coupling information to the output terminal. Preferably said second logic means further includes a wrap test input terminal, and means responsive to a transition of said wrap test signal for enabling said second logic means.
Thus the outputs of the gate array are derived from a plurality of registers contained in the diagnostic gate array. The inputs to the gate array are provided by a microprocessor, dedicated to the adapter. The microprocessor output which is coupled to the diagnostic gate array includes eight data bits, write select control signals, and a wrap (test) cotrol signal. In the most common case, when the adapter is a SCSI adapter, the multiconductor bus a SCSI bus, and the controller a SCSI controller, a further input to the diagnostic gate array is a signal appearing on the RST conductor of the SCSI bus.
Diagnostic operations can be performed either in the manufacturing process or as Part of a Power on Reset sequence. Testing can be implemented with or without the multiconductor bus connected to the connector on the adapter, so long as the connector is properly terminated. Because the input/output terminals of the device controller are dot OR'ed to outputs of the gate array, the presence of the multiconductor bus and/or the presence of the peripheral devices attached to the multiconductor bus is completely immaterial to the diagnostic operation (again assuming proper termination to prevent signal reflection).
The diagnostic gate array and the controller may be implemented as separate electronic chips, or alternatively the gate array can be integrated with the controller to form a single electronic chip. This single electronic chip may include the functions attributed both to the controller and to the diagnostic array. The diagnostic subsystem can be included as part of the device adapter.
The invention also provides a device adapter capable of controlling a variety of peripheral devices each designed to comply with a specific standard, said device adapter including: a connector for connection to a multiconductor bus; a microprocessor and dedicated memory coupled thereto; a device controller coupled to and driven by said microprocessor, said device controller including dedicated input/output terminals for driving selected conductors of said multiconductor bus and for responding to selected conductors of said multiconductor bus; and a gate array with a set of inputs coupled to said microprocessor and a set of outputs coupled in common with said input/output terminals of said device controller.
Typically the specific standard is a SCSI standard, and so that the adapter is a SCSI adapter, the multiconductor bus a SCSI bus, and the device controller a SCSI controller, in which case the gate array preferably includes a Reset input coupled to the connector.

Brief Description of the Drawings

Figure 1 is a block diagram of a micro computer system including an adapter with its associated interface and a plurality of devices coupled to that interface;
Figure 2 is a detailed block diagram of the adapter of Figure 1;
Figure 3 is a further detail of the adapter of Figure 1 showing a typical SCSI controller and a diagnostic gate array; and
Figure 4 is a schematic of the diagnostic gate array of Figure 3.

Detailed Description

Figure 1 is a block diagram of a typical micro-computer system 10 showing an adapter 20 coupled to and controlling a plurality of devices 61-63 through a bus 50. The bus 50 is coupled to a port 25 on the adapter. In addition, the adapter 20 includes a port 23 through which the adapter is coupled to the bus 30. In a specific embodiment of the invention the adapter 20 comprises a SCSI adapter e.g., an adapter conforming to the SCSI standard. The adapter 20 has a port 25 coupled to a SCSI bus 50 which in turn connects each to a plurality of devices 61-63. Devices 61-63 can be any of a variety of peripheral devices conforming to the SCSI standard such as hard files, floppy disk drives, printers, CD ROMS, etc. As will be more completely described below the SCSI adapter 20 includes a diagnostic sub- system which allows the adapter 20 to test a SCSI controller included within the adapter 20.
Figure 2 is a block diagram of the adapter 20 showing several of the components therein including a peripheral device controller 201 which can, for example, be a SCSI controller. The controller 201 is coupled through the port 25 to the SCSI bus 50. The controller is also coupled over a bus 206 to a dedicated micro-processor 202 (such as the Intel 80188) and to ROM 203 and RAM 204. The micro-processor 202 is coupled to a Buffer & Data Flow Control element 205 and to a System Interface Control 216. The System Interface Control 216 is coupled via the port 23 to the bus 30. The adapter 20 also includes an intelligent buffer 207 coupled to the SCSI controller 201 through the Buffer & Data Flow Control element 205.
In addition to the elements shown in Figure 2 there is the diagnostic sub-system, which can be incorporated into the adapter as shown in Figure 3. Figure 3 shows the bus 206 coupling the micro-processor 202 to the SCSI controller 201 and the relationship of the micro-processor 202 to the RAM 203 and RAM 204. Figure 3 shows in detail a plurality of input/ output terminals of the SCSI controller 201. Input/output terminals include reset (RST), command/data (C/D), input/output (I/O), message (MSG), attention (ATN), select (SEL), busy (BSY), request (REQ), acknowledge (ACK), and parity terminals. Each of these terminals is connected via a dedicated conductor to a corresponding terminal in the port or connector 25 through which these terminals are connected to the SCSI bus 50. In addition, the SCSI controller 201 includes eight data input/output terminals each of which is connected to a different conductor and there through to a corresponding terminal in the connector or port 25.
Figure 3 also shows the diagnostic gate array 220. The diagnostic gate array 220 includes an input from the bus 206, coupling signals generated from the dedicated micro-processor 202. The diagnostic gate array includes an output terminal for each of eight data conductors, as well as for each of the following: ACK, REQ, BSY, SEL, PARITY, MSG, I/O, and C/D. Conductors from each of these output terminals are connected to the corresponding conductor coupled between a like input/output terminal of the SCSI controller 201 and the port or connector 25. The diagnostic gate array 220 also includes a further input terminal RST which is connected to the conductor coupling the SCSI controller terminal RST to the port or connector 25.
Figure 4 is a block diagram of one preferred embodiment of the diagnostic gate array 220 of figure 3. More particularly, as shown in figure 4 the bus 206 provides 12 input signals to the diagnostic gate array 220. These signals include eight bits of data D0-D7, two register select signals, CS1 and CS2, a Write control signal and a WRAP control signal. This thirteenth input to the diagnostic gate array 220 is provided at the RST terminal which is coupled to the RST terminal at port 25 and to the RST terminal of the SCI controller 201. The gate array 220 includes two registers, REGI and REG2. Each of the registers has eight data input terminals, each coupled to one of the input terminals D0 - D7. Two additional inputs to the gate array 220 are the control signals CS1 and CS2. The presence of either CS1 or CS2 selects the associated element either REG1 or REG2 for writing the contents of D0 - D7. The information is written in the joint presence of the appropriate select signal (CS1 or CS2) along with the Write signal, another input from the bus 206.
Each of the registers, REG1 and REG2, has each of its eight output terminals connected to a different one of a plurality of output gates OA1 - OA16. The other input terminal to each of the gates OA1 - OA16 is provided by the output of a gate G4 which is one element of a bistable element or flip-flop FF formed by gates G1 - G4. The two inputs to the flip-flop FF are the RST signal and the WRAP signal. Assuming that RST is absent (or inactive) then assertion of WRAP partially enables each of the gates OA1 - OA16 to repeat, at its output, the other input provided from the associated terminal of one of the registers REG1 - REG2. Eight of the outputs of the gate array 220 are the signals DATA0 - DATA7 which, as shown in figure 3 are dot OR'ed with the signals provided by the DATA terminals of the SCI controller 201. The other eight outputs of the gate array 220 are the control signals ACK, REQ, BSY, SEL, PARITY, MSG, I/O and C/D.
From the foregoing it should be apparent that the micro-processor 202 can, by providing the appropriate signals over the bus 206, drive any of the 16 output terminals of the gate array 220 in any desired sequence or pattern. More particularly, the data stored in any stage of either of the registers REG1 or REG2 is controlled by transmitting the appropriate bit on that one of the conductors, D0 - D7 associated with the selected stage of the register, and asserting either CS1 or CS2 depending on which of the registers the stage appears in, along with the Write signal. Once the registers REG1 and REG2 have been loaded with the appropriate data, assertion of WRAP will produce the corresponding data at the output of the gate array 220.
The RST input, since it is connected via the port 25 to the RST conductor on the SCSI bus, will follow the state of the RST conductor on the SCSI bus.
Accordingly, even of the gate array 220 is being driven by the micro-processor 202, the presence of the reset signal on the RST bus will be detected by the gate array 220, and that detection will cause the state of the flip-flop FF to change. The change in state of the Flip-flop FF will disable each of the gates OA1 - OA16. Accordingly, the gate array 220 will respond to the reset signal on the SCSI bus as any other SCSI device is required to respond by the standard.
In order to test the SCSI controller 201 the micro-processor 202 (driven by a micro-code from either ROM203 or RAM204) first commands the SCSI controller 201 to arbitrate for control of the SCSI bus. This ensures that testing of the SCSI controller 201 will not interfere with any other transactions which may be simultaneously taking place across the SCSI bus. On successfully arbitrating for control of the bus, the SCSI controller 201 then proceeds to select itself, e.g., it identifies the target device as the device with its own ID. The micro-processor 202 then drives the gate array 220 with a sequence of signals. Those signals can simulate the normal response of any target device to the SCSI controller 201. The micro-processor 202 then monitors the status of the SCSI controller 201 to ensure that the SCSI controller 201 properly responds to the simulated response generated by the gate array 220. In addition, or in lieu of the foregoing the micro-processor 202 can drive the gate array 220 with a simulation of an error condition (PARITY overrun, etc.) and also monitor the response of the SCSI controller 201. In this fashion the SCSI controller may be tested whether or not any device is connected to the SCSI bus (so long as the bus is properly terminated) and if a device is so connected regardless of its identity or characteristics. Furthermore, by controlling the pattern of signals written to the gate array 220 the response of the SCSI controller 201 to fault-free or faulty devices can be detected by the micro-processor 202.
Although not illustrated, in a second embodiment of the invention, the gates and registers of figure 4 are integrated into the structure of the SCSI controller 201. As a result the dot OR'ed connections of figure 3 are no longer external to the SCSI controller but rather, in this embodiment, are internal to the SCSI controller 201. In other respects the two embodiments have similar operational characteristics.

Claims

1. A diagnostic subsystem for use with an adapter (20), wherein said adapter is capable of controlling a variety of peripheral devices (61-63) each designed to comply to a specific standard and includes a microprocessor (202) and dedicated memory (203, 204) coupled thereto, and a controller (201) coupled to said microprocessor and to a multiconductor (50) bus, said diagnostic subsystem including:
a gate array (220) coupled to said microprocessor and to said controller, and also coupled to said multiconductor bus; and
means responsive to a diagnostic command received at said device for selecting said controller and for generating and coupling, through said gate array, signals simulating the response of an attached peripheral device.

2. A diagnostic subsystem as claimed in claim 1, wherein said means responsive to a diagnostic command for generating signals simulating an attached peripheral device includes means for simulating a faulty attached peripheral device.

3. A diagnostic subsystem as claimed in any preceding claim, wherein said gate array includes a plurality of register stages, each coupled to an input terminal of said gate array, first logic means responsive to command signals for enabling at least one of said register stages to store information representative of a signal appearing at said input terminal, and second logic means for coupling information stored in said at least one register stage to an output terminal.

4. A diagnostic subsystem as claimed in claim 3, wherein said second logic means includes:
a reset input terminal coupled to a reset signal carrying conductor in said multiconductor bus; and
means responsive to an active reset signal for disabling said second logic means from coupling information to said output terminal.

5. A diagnostic subsystem as claimed in claim 4, wherein said second logic means further includes a wrap test input terminal, and means responsive to a transition of said wrap test signal for enabling said second logic means.

6. A diagnostic subsystem as claimed in any preceding claim, wherein said gate array is integrated with said device controller to form a single electronic chip.

7. A diagnostic subsystem as claimed in any preceding claim, wherein said specific standard is a SCSI standard, said adapter is a SCSI adapter, said multiconductor bus is a SCSI bus, and said controller is a SCSI controller.

8. A device adapter including a diagnostic subsystem as claimed in any preceding claim.

9. A device adapter (20) capable of controlling a variety of peripheral devices (61-63) each designed to comply with a specific standard, said device adapter including:
a connector for connection to a multiconductor bus (50);
a microprocessor (202) and dedicated memory (203, 204) coupled thereto;
a device controller (201) coupled to and driven by said microprocessor, said device controller including dedicated input/output terminals for driving selected conductors of said multiconductor bus and for responding to selected conductors of said multiconductor bus; and a gate array (220) with a set of inputs coupled to said microprocessor and a set of outputs coupled in common with said input/output terminals of said device controller.

10. A device adapter as claimed in claim 9 wherein said specific standard is a Small Computer System Interface (SCSI) standard, and wherein said gate array includes a Reset input coupled to said connector.

11. A device adapter as claimed in claim 10, wherein said multiconductor bus is a SCSI bus, and said device controller is a SCSI controller.