EP0365630B1 - Process for manufacturing sources of field-emission type electrons, and application for producing emitter networks - Google Patents

Process for manufacturing sources of field-emission type electrons, and application for producing emitter networks Download PDF

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Publication number
EP0365630B1
EP0365630B1 EP89904094A EP89904094A EP0365630B1 EP 0365630 B1 EP0365630 B1 EP 0365630B1 EP 89904094 A EP89904094 A EP 89904094A EP 89904094 A EP89904094 A EP 89904094A EP 0365630 B1 EP0365630 B1 EP 0365630B1
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Prior art keywords
layer
process according
substrate
monocrystalline
points
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EP89904094A
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German (de)
French (fr)
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EP0365630A1 (en
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Dominique Dieumegard
Guy Garry
Léonidas Karapiperis
Didier Pribat
Christian Collet
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Thales SA
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Thomson CSF SA
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Priority claimed from FR8903153A external-priority patent/FR2644287B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00—Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02—Main electrodes
    • H01J1/30—Cold cathodes, e.g. field-emissive cathode
    • H01J1/304—Field-emissive cathodes
    • H01J1/3042—Field-emissive cathodes microengineered, e.g. Spindt-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02—Manufacture of electrodes or electrode systems
    • H01J9/022—Manufacture of electrodes or electrode systems of cold cathodes
    • H01J9/025—Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes

Definitions

  • the invention relates to the manufacture of electron sources of the field emission type, and more particularly to a method of manufacturing spiked emitters usable in dense networks of such sources, and is applicable in particular to triode or display screens.
  • the electron source generally consists of a metallic emitter cone deposited on a substrate, surrounded by an insulating cavity formed in a thin dielectric layer, this layer comprising its upper part a thin metallic layer forming the extraction electrode.
  • This micro-emitter is produced repeatedly on the substrate with a density of the order of 106 emitters per cm2.
  • the micro-transmitters are optionally grouped into elementary cells, for example of the order of 103 or more transmitters per cell, each cell constituting an emission area located at the node of a matrix network of rows of cathodes (tips) and columns anodes (extraction electrodes).
  • Document EP-A-278 405 discloses a method for producing spike cathodes for electron-emitting elements according to which spikes are grown on a substrate made of amorphous material on which seeds of germination are deposited. Because the growth is carried out on an amorphous substrate, the shape of the tips has a random growth. In addition, the tips cannot be centered precisely with respect to the holes formed in the metal layer serving as an electron extraction grid.
  • Document EP-A-130 650 discloses a method for producing a light wave guide on a monocrystalline substrate, but no method for producing emissive cathodes is suggested there, and all the more reason for carrying it out. of electron extraction grids.
  • the known methods therefore do not allow a network of spiked transmitters to be produced simply.
  • the subject of the invention is another type of method for manufacturing a field emission transmitter, which does not have the drawbacks of the above-mentioned methods.
  • the subject of the present invention is a process for producing electron sources and cathodes using field emission, allowing cathode tips to be obtained in a simple manner well centered with respect to the axis of the grid hole, the cathodes being formed by faceted crystal growth, the electron sources being tips associated with metallic layers or extractors comprising openings in the axis of which these points are situated.
  • the present invention also relates to devices using field emission cathodes having good self-alignment characteristics, the manufacture of which is simplified by the self-alignment method of the invention.
  • the method of manufacturing electron sources according to the invention is characterized in that it consists in using a single mask to etch, in a first layer of insulating material covering a monocrystalline substrate, windows delimiting on the substrate germination zones of the points of these sources by epitaxial and faceted growth of conductive or semiconductor material, these germination zones being at least partially electrically conductive, and for etching cavities concentric to the points in the layers of conductive and insulating materials covering said first layer of insulating material.
  • the process according to the invention is also characterized in that at least one layer of dielectric material is deposited on a monocrystalline substrate, that at least one cavity is etched in the deposited layer, and that it is formed by germinated crystal growth on the substrate and faceted, a cathode tip at the bottom of each cavity, a layer of electrically conductive material serving as a grid being formed on the layer of dielectric material.
  • a layer of dielectric material is deposited on the layer of electrically conductive material, and openings are etched in the three layers formed on the substrate until the substrate is exposed.
  • the electron source according to the invention is characterized in that it comprises, in order, a monocrystalline substrate with at least one projecting cathode tip, a dielectric layer and a layer of electrically conductive material, the cathode tip being housed in a section cavity of any shape, formed in these two layers, and being centered relative to the opening in the conductive layer.
  • the component is an electroluminescent component comprising an anode layer of electroluminescent material closing the cavity at the bottom of which the cathode tip has been formed.
  • the components according to the invention can have a matrix structure in rows and columns each crossing of the matrix comprising at least one electron source as defined above.
  • FIG. 1A The structure of an elementary emitter is shown in FIG. 1A: a monocrystalline substrate 1 made of electrically conductive material (metal or semiconductor) carries an insulating layer 2 covered with a thin conductive layer 3; a hole made in the insulating and metallic layers 2 makes it possible to produce a conductive tip 4 resting on the substrate for the emission of electrons during the application of a potential between the tip 4 (cathode) and the upper conductive layer 3 (grid).
  • a monocrystalline substrate 1 made of electrically conductive material metal or semiconductor
  • a hole made in the insulating and metallic layers 2 makes it possible to produce a conductive tip 4 resting on the substrate for the emission of electrons during the application of a potential between the tip 4 (cathode) and the upper conductive layer 3 (grid).
  • FIG. 1B differs from that of FIG. 1A in that the substrate 1 'comprises a support 1''made of insulating material coated with a layer 1''' epitaxied in material electrically conductive.
  • the layer 1 '' can itself rest on a support of a different type 10 '(see Figure 1C).
  • the manufacturing method according to the invention proceeds by selective epitaxy on a substrate of silicon or any other suitable monocrystalline and conductive material, instead of proceeding by metal deposition or by chemical etching of the silicon, as shown in FIGS. 2a to 2h and in Figures 3a to 3g where the same elements as in Figure 1 have been designated by the same references.
  • the starting substrate 1 is typically a monocrystalline orientation silicon substrate (100), whose dimensions can be from 100 to 150 mm or more, and whose resistivity is from a few 10 California3 ohm.cm to a few ohms.cm. This substrate is shown in Figures 2a and 3a.
  • the first stage of the process in the two variants consists in oxidizing the surface of the substrate by thermal oxidation of the silicon to obtain a correct thickness of silica SiO2, generally less than 1 ⁇ m but which can however be greater.
  • This layer of silica can also be obtained by any other suitable deposition method: vacuum evaporation, sputtering or CVD process such as: PECVD ("Plasma Enhanced Chemical Vapor Deposition"), LTO (“Low Temperature Oxide”) or HTO ( "High Temperature Oxide”), and ...
  • PECVD Plasma vapor Deposition
  • LTO Low Temperature Oxide
  • HTO High Temperature Oxide
  • the second step of the process consists in etching this layer of silica in the areas where the tips will have to be formed.
  • a uniform layer of resin is first deposited, sensitive to light, X-rays, electrons, or thick ions depending on the exposure method used.
  • This uniform layer of resin is then exposed through a mask for a layer sensitive to light or to X-rays, or exposed by direct writing using an electron beam or an ion beam to obtain the network.
  • of elementary figures desired Each figure elementary is an elementary zone suitably oriented with respect to the crystallographic directions of the substrate.
  • each elementary figure is a square whose sides are parallel to the directions ⁇ 100 ⁇ or ⁇ 110 ⁇ of the substrate, of length between a fraction of a micrometer and a few micrometers; the pitch of the network of elementary figures is between a few micrometers and a few tens of micrometers.
  • the resin is then developed and the silica layer 2 attacked either by chemical attack or preferably by RIE (Reactive Ion Etching) in the openings thus formed in the resin layer. These openings being made, the rest of the resin is removed.
  • RIE Reactive Ion Etching
  • the next phase is the phase in which the silicon tips 4 are produced.
  • the pyramids constituting the points are produced on the zones 1A of the substrate 1 exposed, by selective faceted epitaxy of silicon.
  • This epitaxy is said to be selective, because there is no silicon deposit on the surface of the silica 2, but only on the bottom of the opening window made of monocrystalline silicon with orientation ⁇ 100 ⁇ and which serves as germ for crystal growth.
  • the operating conditions for growth are chosen so that optimum faceting is developed; these facets are oriented at 45 ° or 54.74 ° from the surface of the substrate and are facets with a slow growth speed, the plane of the substrate being the growth plane with fast speed.
  • FIGS. 2d and 3d By epitaxy from a basic elementary area etched in the silica surface, pyramidal points are obtained, 4 represented in FIGS. 2d and 3d.
  • Selective epitaxy of silicon can be done either at atmospheric pressure or at reduced pressure.
  • the optimal gas mixture is a mixture of silane SiH4, hydrogen, H2, and hydrochloric acid HCl, at a temperature between 1000 ° and 1100 ° C.
  • the optimal gas mixture can consist of dichlorosilane, SiH2Cl2, hydrogen H2 and hydrochloric acid HCl, at a temperature between 850 and 950 ° C. From this epitaxy phase, two variants are possible.
  • the next phase is a phase of metallic deposition on the surface of the sliice and of the silicon tips.
  • This uniform metallic thin layer 5 of thickness less than 1 ⁇ m is deposited by evaporation, by spraying or by epitaxy in the vapor phase; it can advantageously be made of tungsten, a good electron emitter.
  • this layer can be a layer of silica, such as layer 2, or a layer of silicon nitride or even a layer of alumina.
  • the thickness of this layer will be of the order of 1 to a few microns.
  • the next phase is then the deposition of a second uniform metallic thin layer 3 of thickness less than 1 ⁇ m, deposited by the same techniques as above, that is to say by evaporation, or by spraying, or by chemical phase deposition. steam.
  • This second layer of metal is intended to form the extracting electrode, that is to say the grid of the emitter. It then remains to remove the second layer of metal and the dielectric layer on the tip forming the cathode 4 of the transmitter.
  • the next phase is a phase of uniform deposition of masking resin as in the phase where openings have been formed in the silica layer, this resin being sensitive to light, X-rays, electrons or ions.
  • a masking phase according to the same mask as that used for etching the silica layer makes it possible to carry out in the following phase after development of the resin, the selective attack of the second metallic thin layer and then removing the dielectric layer to reveal the tip 4, covered with the first thin metallic layer. This attack can be done chemically.
  • the final structure after etching of the metal layer and the dielectric layer is shown in Figure 2h.
  • the pitch between elementary emitters is such that it is possible to make the network necessary for controlling these emitters in the intervals between elementary emitters by etching thin metallic layers.
  • These metal layers can be made of tungsten which is particularly suitable for extracting electrons, and which does not erode under the effect of the electrons.
  • the next phase allowing the dielectric 2 ′ to be cut, consists in depositing a resin, insulating it through a mask, and developing it, then in carrying out a localized attack of the dielectric in the areas where the resin has been removed.
  • the structure at the end of this phase is shown in Figure 3f.
  • the last phase of the process consists in depositing a thin metallic layer which, because of the structure obtained at the end of the previous phase, will make it possible to deposit the metal both on the flat surface to form the grid 3 of the emitter and on the silicon tips 4 to form the emissive cathode.
  • the cathodes of the emitters with spikes are not connected to each other by a plane metallic layer and the connections as well as the supply of electrons to these spikes of emitters must be made elsewhere.
  • the starting substrate is preferably a heavily N + doped substrate so as to bring the electrons to the metal tips in tungsten for example.
  • Figure 4 is a perspective view showing the facets of a tip of a transmitter made according to the first variant of the method.
  • the process for manufacturing a tip emitter according to the invention is particularly well suited to the production of networks of transmitters since they only use manufacturing phases in which several samples are treated simultaneously in the same epitaxy chamber without it being necessary for each sample to be in rotation: the conditions necessary for the method to be correctly applied being that the monocrystalline substrate on which the silicon is grown by selective epitaxy is properly oriented and that one obtains a faceted pyramid during growth, the gas mixture used during epitaxy having the proportion of hydrochloric acid and SiH Si or SiH2Cl2 adapted.
  • a monocrystalline substrate 101 is for example made of Si or GaAs or any other suitable monocrystalline material.
  • This substrate 101 has a surface orientation (x, y, z), x, y and z being any integers. Preferably but not limited to these integers are equal to 0 or 1, which corresponds to faces such as (100), (110) or (111), which are easily accessible. Can we also use oriented substrates (211)? (221) or (311).
  • the first step of the process of the invention (FIG. 5) consists in depositing a layer of dielectric 102 on the substrate 101.
  • This dielectric is for example Si02 or Si3N4, and its thickness is advantageously around 1 to 2 microns.
  • This deposition can be carried out by known methods such as the pyrolysis of a gaseous mixture SiH4 + N20 or SiH4 + NH3 at a temperature of approximately 850 ° C or the plasma assisted deposition at a temperature of approximately 250 ° C.
  • the second step (FIG. 6) consists in depositing a metallic layer 103 serving as metallization of the extraction grid.
  • the thickness of the layer 103 is for example around 0.1 to 1 micron.
  • the deposited material is advantageously Mo, Pt or Ni.
  • the third step ( Figure 7) consists in depositing a passivating layer 104 of dielectric material.
  • This layer 104 makes it possible to avoid nucleation of polycrystalline material (for example Si) on the metallic grid layer 103 during the faceted epitaxy operation, and therefore makes it possible to render this epitaxy operation (described below with reference in Figure 10) actually selective.
  • the material of layer 104 must be different from that of layer 102, in order to allow this layer 104 to be selectively removed by chemical attack during the seventh step described below. If, for example, the layer 102 is in Si3N4, the layer 104 can be in Si02, and if the layer 102 is in Si02, the layer 104 can be in Si3N4.
  • the thickness of layer 104 is for example around 0.1 to 1 micron.
  • the fourth step (FIG. 8) consists in etching a cavity 105 in the layers 102 to 104, to expose a surface 106 of substrate 101.
  • the shape and dimensions of surface 106 can be any.
  • the invention is particularly advantageous when it comes to making a network of microcathodes with very fine pitch (characteristic diameter or dimension of the cavities 105 of the order of 0.5 to 2 microns and no repetition of the order of 10 microns or less), in particular because it is possible to use, for etching the cavities 105, a mask (not shown) of photosensitive resin deposited on the layer 104 and appropriately exposed to define the openings (of any shape) of the cavities 104.
  • the etching is then carried out by RIE ("Reactive Ion Etching"). This allows the tip of each cathode to self-align with respect to the opening of the corresponding grid, as will appear on reading the description below.
  • the fifth step (FIG. 9) which is not necessarily implemented in all cases, consists in increasing the section of the cavity 105 in the layer 102 by a slight chemical attack.
  • this layer 102 a cavity 107 is obtained and this cavity 107 leaves a surface 108 on the substrate 101 bare.
  • this attack is carried out with HF.
  • the sixth step (FIG. 10) consists in growing a pyramid 109 on the surface 108 which serves as the seed of crystallization (or on the surface 106 if one does not proceed to step 5) under conditions of selective faceted epitaxy.
  • This selectivity of the deposit (deposit only on the surface 108 or 106) is obtained, for example in the case where the substrate and the deposit material are silicon, by using a CVD reactor ("Chemical Vapor Deposition") at atmospheric pressure or at reduced pressure, into which a gaseous mixture of well defined proportions is introduced comprising, for example, SiH4 + HCl or SiH2Cl2 + HCl diluted in carrier H2, at a temperature between approximately 900 and 1100 ° C. (see for example the article by L.
  • reaction temperature conditions and the partial pressures of various gases used are set according of the orientation of the substrate, so as to preferably obtain faceting (111) on the four faces of the pyramid 9.
  • This faceting corresponds to an angle at the top of the pyramid of approximately 70 °, which is favorable to the field emission.
  • the decomposition reaction is carried out in a CVD type reactor at low pressure from WF6 diluted in H2 at a temperature of the order of 600 ° C or more. It is necessary to properly control the rate of deposition, the temperature and the size of the germination openings in order to obtain faceted growth.
  • the seventh step (FIG. 11) which is not necessarily implemented, consists in removing the layer 104 of dielectric material, advantageously by selective chemical attack.
  • the invention provides an additional step of selective chemical attack making it possible to obtain this faceting.
  • the first step consists in depositing a layer 110 of dielectric material on a substrate 111 of monocrystalline material.
  • the second step (FIG. 15) consists in etching a cavity 112 in the layer 110 by RIE.
  • the third step consists in depositing directly, without being placed in selectivity conditions, polycrystalline material 113 on the dielectric 110 and faceted monocrystalline material 114 on the surface 115 of the substrate exposed by etching of the cavity 112, this material 114 forming a pyramid. So that the layer 113 is made of a good conductive material and can serve as a grid, it is doped very strongly during the deposition phase. If the substrate 111 is made of silicon, the deposition is carried out using a mother gas phase composed of SiH4 diluted in a carrier gas (H2 or He for example).
  • a mother gas phase composed of SiH4 diluted in a carrier gas (H2 or He for example).
  • HCl can be added to the gas phase but in a controlled amount so as not to inhibit the nucleation of polysilicon 113 on silica 110.
  • the doping gas is then phosphine PH3, so as to obtain highly doped silicon of type n both at the level of the monocrystalline pyramid and at the level of the polycrystalline deposit 113 on the silica 110.
  • FIG. 17 shows a possible embodiment of an electron source according to the invention.
  • the source is formed on a monocrystalline substrate 116 on which is deposited a dielectric layer 117, then a conductive grid layer 118.
  • the cavity 119 etched in the layers 117,118 has an oblong shape which means that the cathode 120 has an elongated prism shape.
  • the cavities formed in the layers 102, 103, 104 ( Figure 8) or in the layer 110 ( Figure 15) can have any surface shape, the sides of which may or may not be aligned with particular axes of the plane of the substrate.
  • the substrate is made of GaAs, due to the growth anisotropy, care will be taken to orient the general axis of the openings in a direction allowing optimal faceting such as (111) for example or even higher indices, such as (221) or (331).
  • FIG. 18 shows, by way of nonlimiting example, an electroluminescent component 121 which comprises an electron source 122 and an anode 123 made of electroluminescent material closing the cavity 124 at the bottom of which the cathode tip 125 has been formed.
  • the source 122 comprises in order a monocrystalline substrate 126, for example made of silicon, a first dielectric layer 127, a metal gate layer 128 and a second dielectric layer 129 which may be the aforementioned passivation layer.
  • the anode layer 123 is deposited under vacuum on the layer 129, for example as described in EP-A-350 378 (French Patent Application No. 88 09303).
  • a monocrystalline insulating substrate 130 on which a conductive or semiconductor material 131 is heteroepitaxied (Figure 19B).
  • a material such as heteroepitaxied silicon on sapphire (SOS for Silicon on Sapphire) or else heteroepitaxied silicon on zirconia stabilized with Yttrium oxide (YSZ for "Yttria Stabilised Zirconia ”) or alternatively heteroepitaxial silicon on Spinel (Mg Al2 04) or any other composite substrate known to those skilled in the art.
  • the layer of heteroepitaxied silicon will be of a thickness of a few microns to a hundred microns on the other hand, this silicon will be strongly doped n so as to have a resistivity of some 10 ⁇ 3 ohm.cm.
  • FIG. 19A of the SIMOX type ("Silicon isolation by IMplantation of OXygen") in which the silicon of the thin layer 132 is isolated from the substrate 133 by a layer 134 formed by ion implantation of oxygen or nitrogen at very high doses (see eg Article HW LAM IEEE Circuits and Devices Magazine July 1987 vol 3, No. 4 page 6 for details on the method).
  • the thin layer of silicon 132 is previously brought to a thickness typically between a few microns and a hundred microns by epitaxy in the vapor phase. It is also doped during this same operation, so as to bring its resistivity to a few 10 ⁇ 3 ohm.cm. Then etched bands 135 of silicon typically width of the order of magnitude of the repetition pitch of the tips is about 10 microns, so as to expose the underlying dielectric Si02 or Si3N4 between the bands. These bands are therefore isolated from each other as shown in FIG. 20. Three layers are successively deposited on this structure: a gate dielectric 136, a gate metallization 137 and a passivation dielectric 138 (see FIG. 21); a structure identical to that shown in FIG.
  • the line j is polarized at around fifty Volts and the column k is kept for ground, for example; or else the line j is polarized at 25 V and the column k at - 25 V while keeping all the other lines and columns grounded. Only point A located at the intersection of row j and column k will emit electrons.

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Abstract

Process for manufacturing field-emission point emitters from a monocrystalline substrate (1) of suitable orientation covered with an insulating layer (2) from which square elemental zones, having a suitable orientation in relation to the substrate, have been removed. Silicon is deposited by selective epitaxy in these zones. The epitaxial growth of silicon at a high speed parallel to the substrate and at a slow speed on faces at 45° in relation to the substrate enables the production of pyramide points which, after having been covered with tungsten, form emitter points. Application, production of bidimensional networks of point emitters, in particular for display screens.

Description

L'invention se rapporte à la fabrication de sources d'électrons du type à émission de champ, et plus particulièrement à un procédé de fabrication d'émetteurs à pointes utilisables dans des réseaux denses de telles sources, et est applicable notamment aux systèmes triodes ou aux écrans de visualisation.The invention relates to the manufacture of electron sources of the field emission type, and more particularly to a method of manufacturing spiked emitters usable in dense networks of such sources, and is applicable in particular to triode or display screens.

Pour la réalisation de réseaux bidimensionnels d'émetteurs à émission de champ, la source d'électrons est généralement constituée d'un cône métallique émetteur déposé sur un substrat, entouré d'une cavité isolante formée dans une couche mince diélectrique, cette couche comportant à sa partie supérieure une couche mince métallique formant l'électrode d'extraction. Ce micro-émetteur est réalisé de façon répétitive sur le substrat avec une densité de l'ordre de 10⁶ émetteurs par cm². Les micro-émetteurs sont éventuellement groupés en cellules élémentaires, par exemple de l'ordre de 10³ émetteurs ou plus par cellule chaque cellule constituant une aire d'émission située au noeud d'un réseau matriciel de lignes de cathodes (pointes) et de colonnes d'anodes (électrodes d'extraction).For the realization of two-dimensional networks of emitters with field emission, the electron source generally consists of a metallic emitter cone deposited on a substrate, surrounded by an insulating cavity formed in a thin dielectric layer, this layer comprising its upper part a thin metallic layer forming the extraction electrode. This micro-emitter is produced repeatedly on the substrate with a density of the order of 10⁶ emitters per cm². The micro-transmitters are optionally grouped into elementary cells, for example of the order of 10³ or more transmitters per cell, each cell constituting an emission area located at the node of a matrix network of rows of cathodes (tips) and columns anodes (extraction electrodes).

On connaît des procédés de fabrication de tels émetteurs à émission de champ. Dans une première famille de procédés de fabrication du type décrit par C. A SPINDT et al - par exemple dans "Journal of applied Physics, vol. 47, no 12, p.5248, Décembre 1976" -, après avoir gravé la couche métallique déposée sur une couche de diélectrique reposant elle-même sur un substrat en silicium, la couche de diélectrique est gravée par gravure ionique ou chimique puis une couche mince est déposée sur le substrat, dans les trous ainsi formés dans la couche de diélectrique, l'échantillon tournant autour de l'axe du trou de façon à réaliser un dépôt sous forme de cône. Du fait de la rotation, il n'est pas possible de traiter simultanément un grand nombre d'échantillons.Methods are known for manufacturing such field emission transmitters. In a first family type of manufacturing processes described by C. A Spindt et al - for example in "Journal of Applied Physics, vol 47, No. 12, p.5248, in December 1976." - after etched layer metallic deposited on a dielectric layer resting itself on a silicon substrate, the dielectric layer is etched by ionic or chemical etching then a thin layer is deposited on the substrate, in the holes thus formed in the dielectric layer, the sample rotating around the axis of the hole so as to deposit in the form of a cone. Due to the rotation, it is not possible to process a large number of samples simultaneously.

Un autre de procédé pour réaliser des pointes a été décrit dans l'art antérieur : il met en oeuvre une gravure chimique par attaque d'un substrat monocristallin le long de plans préférentiels. Cette technique nécessite un contrôle très rigoureux de l'attaque chimique si l'on veut minimiser la formation de "pointes parasites" due à des inhomogénéités de gravure.Another method for making tips has been described in the prior art: it uses chemical etching by attacking a monocrystalline substrate along preferential planes. This technique requires very rigorous control of the chemical attack if we want to minimize the formation of "stray spikes" due to etching inhomogeneities.

On connaît d'après le document EP-A-278 405 un procédé de réalisation de cathodes à pointes pour éléments émetteurs d'électrons selon lequel on fait croître des pointes sur un substrat en matériau amorphe sur lequel on dépose des graines de germination. Du fait que la croissance est effectuée sur un substrat amorphe, la forme des pointes a une croissance aléatoire. De plus, les pointes ne peuvent être centrées avec précision par rapport aux trous formés dans la couche métallique servant de grille d'extraction d'électrons.Document EP-A-278 405 discloses a method for producing spike cathodes for electron-emitting elements according to which spikes are grown on a substrate made of amorphous material on which seeds of germination are deposited. Because the growth is carried out on an amorphous substrate, the shape of the tips has a random growth. In addition, the tips cannot be centered precisely with respect to the holes formed in the metal layer serving as an electron extraction grid.

On connaît d'après le document EP-A-130 650 un procédé de réalisation de guide d'onde lumineuse sur un substrat monocristallin, mais il n'y est suggéré aucun procédé de réalisation de cathodes émissives, et à plus forte raison de réalisation de grilles d'extraction d'électrons.Document EP-A-130 650 discloses a method for producing a light wave guide on a monocrystalline substrate, but no method for producing emissive cathodes is suggested there, and all the more reason for carrying it out. of electron extraction grids.

On connaît d'après le document US-A-4 307 507 un procédé de réalisation de pointes de cathodes, mais rien n'y suggère la réalisation de grilles d'extraction d'électrons ni le positionnement précis de telles grilles par rapport aux cathodes.Document US-A-4 307 507 discloses a method for producing cathode tips, but nothing suggests the production of electron extraction grids or the precise positioning of such grids relative to the cathodes .

Les procédés connus ne permettent donc pas de réaliser simplement un réseau d'émetteurs à pointes.The known methods therefore do not allow a network of spiked transmitters to be produced simply.

L'invention a pour objet un autre type de procédé de fabrication d'émetteur à émission de champ, qui ne présente pas les inconvénients des procédés sus-mentionnés.The subject of the invention is another type of method for manufacturing a field emission transmitter, which does not have the drawbacks of the above-mentioned methods.

En particulier, la présente Invention a pour objet un procédé de réalisation de sources d'électrons et de cathodes à émission de champ, permettant d'obtenir de façon simple des pointes de cathodes bien centrées par rapport à l'axe du trou de grille, les cathodes étant formées par croissance cristalline facettée, les sources d'électrons étant des pointes associées à des couches métalliques ou extracteurs comportant des ouvertures dans l'axe desquelles sont situées ces pointes.In particular, the subject of the present invention is a process for producing electron sources and cathodes using field emission, allowing cathode tips to be obtained in a simple manner well centered with respect to the axis of the grid hole, the cathodes being formed by faceted crystal growth, the electron sources being tips associated with metallic layers or extractors comprising openings in the axis of which these points are situated.

La présente invention a également pour objet des dispositifs utilisant des cathodes à émission de champ présentant de bonnes caractéristiques d'autoalignement dont la fabrication est simplifiée par le procédé d'autoalignement de l'invention.The present invention also relates to devices using field emission cathodes having good self-alignment characteristics, the manufacture of which is simplified by the self-alignment method of the invention.

Le procédé de fabrication de sources d'électrons conforme à l'invention, est caractérisé par le fait qu'il consiste à utiliser un masque unique pour graver, dans une première couche de matériau isolant recouvrant un substrat monocristallin, des fenêtres délimitant sur le substrat des zones de germination des pointes de ces sources par croissance épitaxiale et facettée de matériau conducteur ou semi-conducteur, ces zones de germination étant au moins partiellement électriquement conductrices, et pour graver des cavités concentriques aux pointes dans les couches de matériaux conducteurs et isolants recouvrant ladite première couche de matériau isolant.The method of manufacturing electron sources according to the invention is characterized in that it consists in using a single mask to etch, in a first layer of insulating material covering a monocrystalline substrate, windows delimiting on the substrate germination zones of the points of these sources by epitaxial and faceted growth of conductive or semiconductor material, these germination zones being at least partially electrically conductive, and for etching cavities concentric to the points in the layers of conductive and insulating materials covering said first layer of insulating material.

Le procédé conforme à l'invention est également caractérisé par le fait que l'on dépose au moins une couche de matériau diélectrique, sur un substrat monocristallin, que l'on grave au moins une cavité dans la couche déposée, et que l'on forme par croissance cristalline germinée sur le substrat et facettée, une pointe de cathode au fond de chaque cavité, une couche de matériau électriquement conducteur servant de grille étant formée sur la couche de matériau diélectrique.The process according to the invention is also characterized in that at least one layer of dielectric material is deposited on a monocrystalline substrate, that at least one cavity is etched in the deposited layer, and that it is formed by germinated crystal growth on the substrate and faceted, a cathode tip at the bottom of each cavity, a layer of electrically conductive material serving as a grid being formed on the layer of dielectric material.

Selon un aspect avantageux de l'invention on dépose sur la couche de matériau électriquement conducteur une couche de matériau diélectrique et on grave des ouvertures dans les trois couches formées sur le substrat jusqu'à mettre à nu le substrat.According to an advantageous aspect of the invention, a layer of dielectric material is deposited on the layer of electrically conductive material, and openings are etched in the three layers formed on the substrate until the substrate is exposed.

La source d'électrons conforme à l'invention est caractérisée par le fait qu'elle comporte, dans l'ordre, un substrat monocristallin avec au moins une pointe de cathode en saillie, une couche diélectrique et une couche en matériau électriquement conducteur, la pointe de cathode étant logée dans une cavité de section à forme quelconque, pratiquée dans ces deux couches, et étant centrée par rapport à l'ouverture dans la couche conductrice.The electron source according to the invention is characterized in that it comprises, in order, a monocrystalline substrate with at least one projecting cathode tip, a dielectric layer and a layer of electrically conductive material, the cathode tip being housed in a section cavity of any shape, formed in these two layers, and being centered relative to the opening in the conductive layer.

Selon un mode de réalisation de l'invention le composant est un composant électroluminescent comportant une couche d'anode en matériau électroluminescent refermant la cavité au fond de laquelle a été formée la pointe de cathode.According to one embodiment of the invention, the component is an electroluminescent component comprising an anode layer of electroluminescent material closing the cavity at the bottom of which the cathode tip has been formed.

Les composants conformes à l'invention peuvent avoir une structure matricielle en lignes et colonnes chaque croisement de la matrice comportant au moins une source d'électrons telle que définie ci-dessus.The components according to the invention can have a matrix structure in rows and columns each crossing of the matrix comprising at least one electron source as defined above.

La présente invention sera mieux comprise à la lecture de la description détaillée d'un mode de réalisation pris comme exemple non limitatif et illustré par le dessin annexé sur lequel :

  • Les figures 1A, 1B et 1C représentent la structure générale d'un émetteur à pointe ;
  • Les figures 2a à 2h représentent différentes étapes d'une première variante du procédé de fabrication d'émetteur à émission de champ selon l'invention ;
  • Les figures 3a à 3g représentent différentes étapes d'une deuxième variante du procédé de fabrication d'émetteur à émission de champ selon l'invention ;
  • La figure 4 est une vue en perspective de la structure élémentaire obtenue selon l'invention ;
  • les figures 5 à 11 sont des vues schématiques en coupe illustrant différentes étapes successives du procédé de l'invention ;
  • les figures 12 à 14 sont des vues schématiques illustrant une étape d'attaque chimique sélective permettant d'obtenir un facettage déterminé, conformément au procédé de l'invention ;
  • les figures 15 et 16 sont des vues simplifiées illustrant une variante du procédé conforme à l'invention ;
  • la figure 17 est une coupe simplifiée en perspective d'une variante de source d'électrons conforme à l'invention, et
  • la figure 18 est une vue schématique en coupe d un élément électroluminescent comportant une source d'électrons conforme à l'invention, et
  • les figures 19 à 23 sont des vues schématiques illustrant des étapes de fabrication de composants conformes à l'invention.
The present invention will be better understood on reading the detailed description of an embodiment taken as a nonlimiting example and illustrated by the appended drawing in which:
  • Figures 1A, 1B and 1C show the general structure of a point transmitter;
  • FIGS. 2a to 2h represent different stages of a first variant of the method for manufacturing a transmitter field emission according to the invention;
  • FIGS. 3a to 3g represent different stages of a second variant of the method for manufacturing a field emission transmitter according to the invention;
  • Figure 4 is a perspective view of the elementary structure obtained according to the invention;
  • Figures 5 to 11 are schematic sectional views illustrating different successive steps of the method of the invention;
  • Figures 12 to 14 are schematic views illustrating a selective etching step for obtaining a determined faceting, according to the method of the invention;
  • Figures 15 and 16 are simplified views illustrating a variant of the method according to the invention;
  • FIG. 17 is a simplified section in perspective of a variant of an electron source according to the invention, and
  • FIG. 18 is a schematic sectional view of an electroluminescent element comprising an electron source according to the invention, and
  • Figures 19 to 23 are schematic views illustrating stages in the manufacture of components according to the invention.

La structure d'un émetteur élémentaire est représentée sur la figure 1A : un substrat monocristallin 1 en matériau électriquement conducteur (métal ou semiconducteur) porte une couche isolante 2 recouverte d'une couche mince conductrice 3 ; un trou ménagé dans les couches 2 isolante et métallique 3 permet de réaliser une pointe conductrice 4 reposant sur le substrat pour l'émission d'électrons lors de l'application d'un potentiel entre la pointe 4 (cathode) et la couche supérieure conductrice 3 (grille).The structure of an elementary emitter is shown in FIG. 1A: a monocrystalline substrate 1 made of electrically conductive material (metal or semiconductor) carries an insulating layer 2 covered with a thin conductive layer 3; a hole made in the insulating and metallic layers 2 makes it possible to produce a conductive tip 4 resting on the substrate for the emission of electrons during the application of a potential between the tip 4 (cathode) and the upper conductive layer 3 (grid).

La structure de la figure 1B diffère de celle de la figure 1A en ce que le substrat 1' comporte un support 1'' en matériau isolant revêtu d'une coucle 1''' épitaxiée en matériau électriquement conducteur. La couche 1'' peut elle-même reposer sur un support d'un type différent 10' (voir figure 1C).The structure of FIG. 1B differs from that of FIG. 1A in that the substrate 1 'comprises a support 1''made of insulating material coated with a layer 1''' epitaxied in material electrically conductive. The layer 1 '' can itself rest on a support of a different type 10 '(see Figure 1C).

Le procédé de fabrication selon l'invention procède par épitaxie sélective sur un substrat de silicium ou de tout autre matériau monocristallin et conducteur approprié, au lieu de procéder par dépôt de métal ou par gravure chimique du silicium, comme représenté sur les figures 2a à 2h et sur les figures 3a à 3g où les mêmes éléments que sur la figure 1 ont été désignés par les mêmes repères.The manufacturing method according to the invention proceeds by selective epitaxy on a substrate of silicon or any other suitable monocrystalline and conductive material, instead of proceeding by metal deposition or by chemical etching of the silicon, as shown in FIGS. 2a to 2h and in Figures 3a to 3g where the same elements as in Figure 1 have been designated by the same references.

Pour cela, le substrat de départ 1 est typiquement un substrat de silicium monocristallin d'orientation (100), dont les dimensions peuvent être de 100 à 150 mm ou plus, et dont la résistivité est de quelques 10⁻³ ohm.cm à quelques ohms.cm. Ce substrat est représenté sur les figures 2a et 3a.For this, the starting substrate 1 is typically a monocrystalline orientation silicon substrate (100), whose dimensions can be from 100 to 150 mm or more, and whose resistivity is from a few 10 quelques³ ohm.cm to a few ohms.cm. This substrate is shown in Figures 2a and 3a.

La première étape du procédé dans les deux variantes consiste à oxyder la surface du substrat par oxydation thermique du silicium pour obtenir une épaisseur de silice SiO₂ correcte, généralement inférieure à 1 µm mais pouvant toutefois être supérieure. On peut aussi obtenir cette couche de silice par toute autre méthode de dépôt appropriée : évaporation sous vide, pulvérisation cathodique ou procédé CVD tel que : PECVD ("Plasma Enhanced Chemical Vapor Deposition"), LTO ("Low Temperature Oxide") ou HTO ("High Temperature Oxide"), et...Le substrat monocristallin 1 muni de sa couche isolante de silice, 2, est représenté sur les figures 2b et 3b.The first stage of the process in the two variants consists in oxidizing the surface of the substrate by thermal oxidation of the silicon to obtain a correct thickness of silica SiO₂, generally less than 1 μm but which can however be greater. This layer of silica can also be obtained by any other suitable deposition method: vacuum evaporation, sputtering or CVD process such as: PECVD ("Plasma Enhanced Chemical Vapor Deposition"), LTO ("Low Temperature Oxide") or HTO ( "High Temperature Oxide"), and ... The monocrystalline substrate 1 provided with its silica insulating layer, 2, is shown in FIGS. 2b and 3b.

La deuxième étape du procédé consiste à graver cette couche de silice dans les zones où devront être formées les pointes. Pour cela, on dépose dans un premier temps une couche uniforme de résine, sensible à la lumière, aux rayons X, aux électrons, ou aux ions d'épaisseur fonction de la méthode d'insolation utilisée. Cette couche uniforme de résine est ensuite exposée à travers un masque pour une couche sensible à la lumière ou aux rayons X, ou insolée par écriture directe à l'aide d'un faisceau d'électrons ou un faisceau d'ions pour obtenir le réseau de figures élémentaires souhaité. Chaque figure élémentaire est une zone élémentaire convenablement orientée par rapport aux directions cristallographiques du substrat. Dans le cas présent, chaque figure élémentaire est un carré dont les côtés sont parallèles aux directions 〈100〉 ou 〈110〉 du substrat, de longueur comprise entre une fraction de micromètre et quelques micromètres ; le pas du réseau de figures élémentaires est compris entre quelques micromètres et quelques dizaines de micromètres. La résine est alors développée et la couche de silice 2 attaquée soit par attaque chimique soit de préférence par RIE (Reactive Ion Etching) dans les ouvertures ainsi formees dans la couche de résine. Ces ouvertures étant réalisées, le reste de la résine est enlevé. La structure correspondante est représentée sur les figures 2c et 3c.The second step of the process consists in etching this layer of silica in the areas where the tips will have to be formed. For this, a uniform layer of resin is first deposited, sensitive to light, X-rays, electrons, or thick ions depending on the exposure method used. This uniform layer of resin is then exposed through a mask for a layer sensitive to light or to X-rays, or exposed by direct writing using an electron beam or an ion beam to obtain the network. of elementary figures desired. Each figure elementary is an elementary zone suitably oriented with respect to the crystallographic directions of the substrate. In the present case, each elementary figure is a square whose sides are parallel to the directions 〈100〉 or 〈110〉 of the substrate, of length between a fraction of a micrometer and a few micrometers; the pitch of the network of elementary figures is between a few micrometers and a few tens of micrometers. The resin is then developed and the silica layer 2 attacked either by chemical attack or preferably by RIE (Reactive Ion Etching) in the openings thus formed in the resin layer. These openings being made, the rest of the resin is removed. The corresponding structure is shown in Figures 2c and 3c.

La phase suivante est la phase dans laquelle les pointes, 4, de silicium sont réalisées. Pour cela, dans les fenêtres ouvertes dans la couche de silice on réalise sur les zones 1A du substrat 1 mises à nu, par épitaxie sélective facettée de silicium, des pyramides constituant les pointes. Cette épitaxie est dite sélective, car il n'y a pas de dépôt de silicium sur la surface de la silice 2, mais uniquement sur le fond de la fenêtre d'ouverture constituée de silicium monocristallin d'orientation 〈100〉 et qui sert de germe pour la croissance cristalline. D'autre part les conditions opératoires de croissance sont choisies pour que se développe un facettage optimum ; ces facettes sont orientées à 45° ou à 54,74° de la surface du substrat et sont des facettes à vitesse de croissance lente le plan du substrat étant le plan de croissance à vitesse rapide. Ainsi, par épitaxie à partir d'une zone élémentaire carrée gravée dans la surface de silice on obtient des pointes pyramidales, 4 représentées sur les figures 2d et 3d. L'épitaxie sélective de silicium peut être faite soit à la pression atmosphérique, soit à une pression réduite. A la pression atmosphérique le mélange gazeux optimal est un mélange de silane SiH₄, d'hydrogène, H₂, et d'acide chlorhydrique HCl, à une température comprise entre 1000° et 1100°C. A une pression réduite, le mélange gazeux optimal peut être constitué de dichlorosilane, SiH₂Cl₂, d'hydrogène H₂ et d'acide chlorhydrique HCl, à une température comprise entre 850 et 950°C. A partir de cette phase d'épitaxie, deux variantes sont possibles.The next phase is the phase in which the silicon tips 4 are produced. For this, in the open windows in the silica layer, the pyramids constituting the points are produced on the zones 1A of the substrate 1 exposed, by selective faceted epitaxy of silicon. This epitaxy is said to be selective, because there is no silicon deposit on the surface of the silica 2, but only on the bottom of the opening window made of monocrystalline silicon with orientation 〈100〉 and which serves as germ for crystal growth. On the other hand, the operating conditions for growth are chosen so that optimum faceting is developed; these facets are oriented at 45 ° or 54.74 ° from the surface of the substrate and are facets with a slow growth speed, the plane of the substrate being the growth plane with fast speed. Thus, by epitaxy from a basic elementary area etched in the silica surface, pyramidal points are obtained, 4 represented in FIGS. 2d and 3d. Selective epitaxy of silicon can be done either at atmospheric pressure or at reduced pressure. At atmospheric pressure the optimal gas mixture is a mixture of silane SiH₄, hydrogen, H₂, and hydrochloric acid HCl, at a temperature between 1000 ° and 1100 ° C. To one reduced pressure, the optimal gas mixture can consist of dichlorosilane, SiH₂Cl₂, hydrogen H₂ and hydrochloric acid HCl, at a temperature between 850 and 950 ° C. From this epitaxy phase, two variants are possible.

Dans la variante représentée sur les figures 2e à 2f la phase suivante est une phase de dépôt métallique à la surface de la sliice et des pointes de silicium. Cette couche mince métallique uniforme 5 d'épaisseur inférieure à 1µm est déposée par évaporation, par pulvérisation ou par épitaxie en phase vapeur ; elle peut être avantageusement constituée de tungstène, bon émetteur d'électrons.In the variant shown in FIGS. 2e to 2f, the next phase is a phase of metallic deposition on the surface of the sliice and of the silicon tips. This uniform metallic thin layer 5 of thickness less than 1 μm is deposited by evaporation, by spraying or by epitaxy in the vapor phase; it can advantageously be made of tungsten, a good electron emitter.

Puis dans une phase suivante une couche mince uniforme de diélectrique 2', est déposée sur la couche métallique ; cette couche peut être une couche de silice, comme la couche 2, ou une couche de nitrure de silicium ou encore une couche d'alumine. L'épaisseur de cette couche sera de l'ordre de 1 à quelques microns.Then in a following phase a uniform thin layer of dielectric 2 ′ is deposited on the metal layer; this layer can be a layer of silica, such as layer 2, or a layer of silicon nitride or even a layer of alumina. The thickness of this layer will be of the order of 1 to a few microns.

La phase suivante est alors le dépôt d'une seconde couche mince métallique uniforme 3 d'épaisseur inférieure à 1µm, déposée par les mêmes techniques que précédemment c'est-à-dire par évaporation, ou par pulvérisation, ou par dépôt chimique en phase vapeur. Cette seconde couche de métal est destinée à former l'électrode extractrice, c'est-à-dire la grille de l'émetteur. Il reste alors à enlever la deuxième couche de métal et la couche de diélectrique sur la pointe formant la cathode 4 de l'émetteur.The next phase is then the deposition of a second uniform metallic thin layer 3 of thickness less than 1 μm, deposited by the same techniques as above, that is to say by evaporation, or by spraying, or by chemical phase deposition. steam. This second layer of metal is intended to form the extracting electrode, that is to say the grid of the emitter. It then remains to remove the second layer of metal and the dielectric layer on the tip forming the cathode 4 of the transmitter.

Pour cela la phase suivante est une phase de dépôt uniforme de résine de masquage comme dans la phase où des ouvertures ont été formées dans la couche de silice, cette résine étant sensible à la lumière, aux rayons X, aux électrons ou aux ions. Une phase de masquage selon le même masque que celui utilisé pour la gravure de la couche de silice permet de réaliser dans la phase suivante après développement de la résine, l'attaque sélective de la deuxième couche mince métallique puis l'enlèvement de la couche diélectrique pour révéler la pointe 4, recouverte de la première couche mince métallique. Cette attaque peut être faite chimiquement. La structure finale après attaque de la couche de métal et de la couche de diélectrique est représentée sur la figure 2h.For this, the next phase is a phase of uniform deposition of masking resin as in the phase where openings have been formed in the silica layer, this resin being sensitive to light, X-rays, electrons or ions. A masking phase according to the same mask as that used for etching the silica layer makes it possible to carry out in the following phase after development of the resin, the selective attack of the second metallic thin layer and then removing the dielectric layer to reveal the tip 4, covered with the first thin metallic layer. This attack can be done chemically. The final structure after etching of the metal layer and the dielectric layer is shown in Figure 2h.

Le pas entre émetteurs élémentaires est tel qu'il est possible de réaliser le réseau nécessaire à la commande de ces émetteurs dans les intervalles entre émetteurs élémentaires par gravure des couches minces métalliques. Ces couches métalliques peuvent être constituées de tungstène particulièrement adapté à l'extraction d'électrons, et qui ne s'érode pas sous l'effet des électrons.The pitch between elementary emitters is such that it is possible to make the network necessary for controlling these emitters in the intervals between elementary emitters by etching thin metallic layers. These metal layers can be made of tungsten which is particularly suitable for extracting electrons, and which does not erode under the effect of the electrons.

Dans la deuxième variante du procédé de réalisation, après la phase de croissance par épitaxie sélective de silicium dans les zones où la couche de silice a été enlevée comme représentée sur la figure 3d, on passe directement à une phase de dépôt d'une couche de diélectrique 2' sur l'ensemble formé de la couche de silice et des pointes de silicium, sans dépôt préalable de couche mince métallique. Cette couche de diélectrique 2' représentée sur la figure 3e, est constituée d'un matériau éventuellement différent de la silice pour que lors de la découpe ultérieure du diélectrique cette découpe n'affecte pas la couche sous-jacente de silice 2. Ceci n'est toutefois pas absolument nécessaire, l'attaque autour du piédestal de la pointe du matériau diélectrique n'étant pas un problème en soi.In the second variant of the production method, after the phase of growth by selective epitaxy of silicon in the zones where the layer of silica has been removed as shown in FIG. 3d, we pass directly to a phase of deposition of a layer of dielectric 2 ′ on the assembly formed by the layer of silica and the silicon tips, without prior deposition of a metallic thin layer. This dielectric layer 2 ′ shown in FIG. 3e, is made of a material possibly different from silica so that during the subsequent cutting of the dielectric this cutting does not affect the underlying layer of silica 2. This does not is however not absolutely necessary, the attack around the pedestal of the tip of the dielectric material not being a problem in itself.

La phase suivante, permettant la découpe du diélectrique 2', consiste à effectuer un dépôt de résine, à l'insoler à travers un masque, et à le développer, puis à réaliser une attaque localisée du diélectrique dans les zones où la résine a été enlevée. La structure à la fin de cette phase est représentée sur la figure 3f.The next phase, allowing the dielectric 2 ′ to be cut, consists in depositing a resin, insulating it through a mask, and developing it, then in carrying out a localized attack of the dielectric in the areas where the resin has been removed. The structure at the end of this phase is shown in Figure 3f.

La dernière phase du procédé consiste à déposer une couche mince métallique qui du fait de la structure obtenue à la fin de la phase précédente va permettre de déposer le métal à la fois sur la surface plane pour former la grille 3 de l'émetteur et sur les pointes 4 de silicium pour former la cathode émissive.The last phase of the process consists in depositing a thin metallic layer which, because of the structure obtained at the end of the previous phase, will make it possible to deposit the metal both on the flat surface to form the grid 3 of the emitter and on the silicon tips 4 to form the emissive cathode.

Dans cette variante du procédé, les cathodes des émetteurs à pointes ne sont pas reliées entre elles par une couche métallique plane et les connexions ainsi que l'apport d'électrons à ces pointes d'émetteurs doivent être effectuées par ailleurs. Dans ce cas, le substrat de départ est préférentiellement un substrat fortement dopé N+ de façon à amener les électrons aux pointes métalliques en tungstène par exemple.In this variant of the method, the cathodes of the emitters with spikes are not connected to each other by a plane metallic layer and the connections as well as the supply of electrons to these spikes of emitters must be made elsewhere. In this case, the starting substrate is preferably a heavily N + doped substrate so as to bring the electrons to the metal tips in tungsten for example.

La figure 4 est une vue en perspective montrant les facettes d'une pointe d'un émetteur réalisé selon la première variante du procédé.Figure 4 is a perspective view showing the facets of a tip of a transmitter made according to the first variant of the method.

La réalisation des connexions et des réseaux d'électrodes nécessaires pour constituer les cellules élémentaires puis le réseau matriciel de lignes de cathodes et de colonnes de grille, par exemple pour former un écran de visualisation, sera décrite en détails dans ce qui suit. Mais il ressort de la description qui précède que le procédé de fabrication d'émetteur à pointe selon l'invention est particulièrement bien adapté à la réalisation de réseaux d'émetteurs puisqu'ils n'utilisent que des phases de fabrication dans lesquelles plusieurs échantillons sont traités simultanément dans la même chambre d'épitaxie sans qu'il soit nécessaire que chaque échantillon soit en rotation : les conditions nécessaires pour que le procédé soit correctement appliqué étant que le substrat monocristallin sur lequel on fait croître le silicium par épitaxie sélective soit orienté convenablement et que l'on obtienne bien une pyramide à facettes lors de la croissance, le mélange gazeux utilisé lors de l'épitaxie ayant la proportion d'acide chlorhydrique et de SiH₄ ou SiH₂Cl₂ adaptée.The realization of the connections and the electrode networks necessary to constitute the elementary cells and then the matrix network of cathode lines and grid columns, for example to form a display screen, will be described in detail in the following. However, it emerges from the above description that the process for manufacturing a tip emitter according to the invention is particularly well suited to the production of networks of transmitters since they only use manufacturing phases in which several samples are treated simultaneously in the same epitaxy chamber without it being necessary for each sample to be in rotation: the conditions necessary for the method to be correctly applied being that the monocrystalline substrate on which the silicon is grown by selective epitaxy is properly oriented and that one obtains a faceted pyramid during growth, the gas mixture used during epitaxy having the proportion of hydrochloric acid and SiH Si or SiH₂Cl₂ adapted.

Selon une autre variante du procédé pour réaliser la source conforme à l'invention on part d'un substrat monocristallin 101. Le substrat 101 est par exemple en Si ou GaAs ou en tout autre matériau monocristallin adapté. Ce substrat 101 est d'orientation de surface (x,y,z), x,y et z étant des entiers quelconques. De préférence mais de façon non limitative ces entiers sont égaux à 0 ou à 1, ce qui correspond à des faces telles que (100), (110) ou (111), facilement accessibles. On pourra utiliser aussi des substrats orientés (211)? (221) ou (311).According to another variant of the method for producing the source according to the invention, one starts with a monocrystalline substrate 101. The substrate 101 is for example made of Si or GaAs or any other suitable monocrystalline material. This substrate 101 has a surface orientation (x, y, z), x, y and z being any integers. Preferably but not limited to these integers are equal to 0 or 1, which corresponds to faces such as (100), (110) or (111), which are easily accessible. Can we also use oriented substrates (211)? (221) or (311).

La première étape du procédé de l'invention (figure 5) consiste à déposer une couche de diélectrique 102 sur le substrat 101. Ce diélectrique est par exemple du Si0₂ ou Si₃N₄, et son épaisseur est avantageusement d'environ 1 à 2 microns. Ce dépôt peut être effectué par des procédés connus tels que la pyrolyse d'un mélange gazeux SiH₄ + N₂0 ou SiH₄ + NH₃ à une température d'environ 850°C ou le dépôt assisté par plasma à une température d'environ 250°C.The first step of the process of the invention (FIG. 5) consists in depositing a layer of dielectric 102 on the substrate 101. This dielectric is for example Si0₂ or Si₃N₄, and its thickness is advantageously around 1 to 2 microns. This deposition can be carried out by known methods such as the pyrolysis of a gaseous mixture SiH₄ + N₂0 or SiH₄ + NH₃ at a temperature of approximately 850 ° C or the plasma assisted deposition at a temperature of approximately 250 ° C.

La seconde étape (figure 6) consiste à déposer une couche métallique 103 servant de métallisation de grille d'extraction. L'épaisseur de la couche 103 est par exemple d'environ 0,1 à 1 micron. Le matériau déposé est avantageusement du Mo, Pt ou Ni.The second step (FIG. 6) consists in depositing a metallic layer 103 serving as metallization of the extraction grid. The thickness of the layer 103 is for example around 0.1 to 1 micron. The deposited material is advantageously Mo, Pt or Ni.

La troisième étape (figure 7) consiste à déposer une couche passivante 104 de matériau diélectrique. Cette couche 104 permet d'éviter la nucléation de matériau (par exemple Si) polycristallin sur la couche métallique de grille 103 pendant l'opération d'épitaxie facettée, et permet donc de rendre cette opération d'épitaxie (décrite ci-dessous en référence à la figure 10) effectivement sélective. Le matériau de la couche 104 doit être différent de celui de la couche 102, afin de permettre d'enlever sélectivement par attaque chimique cette couche 104 lors de la septième étape décrite ci-dessous. Si, par exemple, la couche 102 est en Si₃N₄, la couche 104 peut être en Si0₂, et si la couche 102 est en Si0₂, la couche 104 peut être en Si₃N₄. L'épaisseur de la couche 104 est par exemple d'environ 0,1 à 1 micron.The third step (Figure 7) consists in depositing a passivating layer 104 of dielectric material. This layer 104 makes it possible to avoid nucleation of polycrystalline material (for example Si) on the metallic grid layer 103 during the faceted epitaxy operation, and therefore makes it possible to render this epitaxy operation (described below with reference in Figure 10) actually selective. The material of layer 104 must be different from that of layer 102, in order to allow this layer 104 to be selectively removed by chemical attack during the seventh step described below. If, for example, the layer 102 is in Si₃N₄, the layer 104 can be in Si0₂, and if the layer 102 is in Si0₂, the layer 104 can be in Si₃N₄. The thickness of layer 104 is for example around 0.1 to 1 micron.

La quatrième étape (figure 8) consiste à graver une cavité 105 dans les couches 102 à 104, pour mettre à nu une surface 106 du substrat 101. La forme et les dimensions de la surface 106 peuvent être quelconques. L'invention est particulièrement avantageuse lorsqu'il s'agit de réaliser un réseau de microcathodes à pas très fin (diamètre ou dimension caractéristique des cavités 105 de l'ordre de 0,5 à 2 microns et pas de répétition de l'ordre de 10 microns ou moins), en particulier du fait que l'on peut utiliser, pour effectuer la gravure des cavités 105, un masque (non représenté) en résine photosensible déposé sur la couche 104 et insolé de façon appropriée pour définir les ouvertures (de forme quelconque) des cavités 104. La gravure est ensuite effectuée par RIE ("Reactive Ion Etching"). Ceci permet un autoalignement de la pointe de chaque cathode par rapport à l'ouverture de la grille correspondante, comme il apparaîtra à la lecture de la description ci-dessous.The fourth step (FIG. 8) consists in etching a cavity 105 in the layers 102 to 104, to expose a surface 106 of substrate 101. The shape and dimensions of surface 106 can be any. The invention is particularly advantageous when it comes to making a network of microcathodes with very fine pitch (characteristic diameter or dimension of the cavities 105 of the order of 0.5 to 2 microns and no repetition of the order of 10 microns or less), in particular because it is possible to use, for etching the cavities 105, a mask (not shown) of photosensitive resin deposited on the layer 104 and appropriately exposed to define the openings (of any shape) of the cavities 104. The etching is then carried out by RIE ("Reactive Ion Etching"). This allows the tip of each cathode to self-align with respect to the opening of the corresponding grid, as will appear on reading the description below.

La cinquième étape (figure 9) qui n'est pas nécessairement mise en oeuvre dans tous les cas, consiste à augmenter la section de la cavité 105 dans la couche 102 par une légère attaque chimique. On obtient dans cette couche 102 une cavité 107 et cette cavité 107 laisse à nu une surface 108 sur le substrat 101. De façon avantageuse, si la couche 102 est en Si0₂, on effectue cette attaque avec du HF.The fifth step (FIG. 9) which is not necessarily implemented in all cases, consists in increasing the section of the cavity 105 in the layer 102 by a slight chemical attack. In this layer 102, a cavity 107 is obtained and this cavity 107 leaves a surface 108 on the substrate 101 bare. Advantageously, if the layer 102 is made of Si0₂, this attack is carried out with HF.

La sixième étape (figure 10) consiste à faire croître en conditions d'épitaxie sélective facettée une pyramide 109 sur la surface 108 qui sert de germe de cristallisation (ou sur la surface 106 si on ne procède pas à l'étape 5). Cette sélectivité du dépôt (dépôt uniquement sur la surface 108 ou 106) est obtenue, par exemple dans le cas où le substrat et le matériau de dépôt sont du silicium, en utilisant un réacteur CVD ("Chemical Vapor Deposition") à pression atmosphérique ou à pression réduite, dans lequel on Introduit un mélange gazeux à proportions bien définies comportant par exemple du SiH₄ + HCl ou du SiH₂Cl₂ + HCl dilué dans du H₂ porteur, à température comprise entre 900 et 1100°C environ (voir par exemple l'article de L. KARAPIPERIS et al. publié dans "Proceedings of the 18th International Conference on Solid State Devices and Materials", Tokyo, 1986, page 713). Dans le cas de l'arséniure de gallium, la sélectivité du dépôt peut être obtenue en utilisant un réacteur de type VPE ("Vapor Phase Epitaxy") à une température comprise entre 600 et 800°C environ, par la méthode des chlorures (par exemple AsCl₃ dilué dans H₂ et une source de gallium solide). On peut aussi utiliser une méthode du type MOCVD ("Metal Organic Chemical Vapor Deposition") à pression réduite. Pour plus de détails sur ces différentes méthodes de dépôt sélectif, on peut se reporter par exemple à la Demande de Brevet français no 88 04437. Les conditions précitées de températures de réaction, et les pressions partielles des divers gaz utilisés, sont réglées en fonction de l'orientation du substrat, de façon à obtenir de préférence un facettage (111) sur les quatre faces de la pyramide 9. Ce facettage correspond à un angle au sommet de la pyramide d'environ 70°, ce qui est favorable à l'émission de champ.The sixth step (FIG. 10) consists in growing a pyramid 109 on the surface 108 which serves as the seed of crystallization (or on the surface 106 if one does not proceed to step 5) under conditions of selective faceted epitaxy. This selectivity of the deposit (deposit only on the surface 108 or 106) is obtained, for example in the case where the substrate and the deposit material are silicon, by using a CVD reactor ("Chemical Vapor Deposition") at atmospheric pressure or at reduced pressure, into which a gaseous mixture of well defined proportions is introduced comprising, for example, SiH₄ + HCl or SiH₂Cl₂ + HCl diluted in carrier H₂, at a temperature between approximately 900 and 1100 ° C. (see for example the article by L. KARAPIPERIS et al. published in "Proceedings of the 18th International Conference on Solid State Devices and Materials", Tokyo, 1986, page 713). In the case of gallium arsenide, the selectivity of the deposit can be obtained by using a reactor of type VPE ("Vapor Phase Epitaxy") at a temperature between approximately 600 and 800 ° C., by the chlorides method (by example AsCl₃ diluted in H₂ and a source of solid gallium). It is also possible to use a method of the MOCVD ("Metal Organic Chemical Vapor Deposition") type at reduced pressure. For details on these methods of selective deposition, one can see for example the French Patent Application No. 88 04437. The above reaction temperature conditions and the partial pressures of various gases used, are set according of the orientation of the substrate, so as to preferably obtain faceting (111) on the four faces of the pyramid 9. This faceting corresponds to an angle at the top of the pyramid of approximately 70 °, which is favorable to the field emission.

On peut par ailleurs utiliser un dépôt sélectif de tungstène W, qui permet aussi de ne faire pousser les pointes que sur les germes de substrat monocristallin dégagés par attaque du diélectrique 104 de la couche métallique 103 et de l'autre diélectrique 102 (voir par exemple I. BEINGLASS, P.A. GARCINI, Extended abstract 380, ECS Fall Meeting, Denver CO (Octobre 1981) pour des détails sur ce procédé).One can also use a selective deposit of tungsten W, which also makes it possible to push the tips only on the seeds of monocrystalline substrate released by attack of the dielectric 104 of the metal layer 103 and of the other dielectric 102 (see for example I. BEINGLASS, PA GARCINI, Extended abstract 380, ECS Fall Meeting, Denver CO (October 1981) for details on this process).

La réaction de décomposition s'effectue dans un réacteur de type CVD à basse pression à partir de WF₆ dilué dans H₂ à une température de l'ordre de 600°C ou plus. Il est nécessaire de bien contrôler la vitesse de dépôt la température et la taille des ouvertures de germination afin d'obtenir une croissance facettée.The decomposition reaction is carried out in a CVD type reactor at low pressure from WF₆ diluted in H₂ at a temperature of the order of 600 ° C or more. It is necessary to properly control the rate of deposition, the temperature and the size of the germination openings in order to obtain faceted growth.

La septième étape (figure 11) qui n'est pas nécessairement mise en oeuvre, consiste à enlever la couche 104 de matériau diélectrique, avantageusement par attaque chimique sélective.The seventh step (FIG. 11) which is not necessarily implemented, consists in removing the layer 104 of dielectric material, advantageously by selective chemical attack.

Dans le cas où le facettage obtenu par croissance sélective ne donne pas de plans (111) pour les quatre faces de la pyramide 109 (figures 10,11), l'invention prévoit une étape supplémentaire d'attaque chimique sélective permettant d'obtenir ce facettage.In the case where the faceting obtained by selective growth does not give plans (111) for the four faces of the pyramid 109 (FIGS. 10,11), the invention provides an additional step of selective chemical attack making it possible to obtain this faceting.

Par exemple (voir figure 12). si l'on utilise un substrat de silicium d'orientation superficielle (100) et si l'on procède à un dépôt à partir d'un mélange SiH₄ + HCl dans H₂ à 1060°C environ, on obtient aisément un facettage (110) de la pyramide 109 ce qui correspond à un angle au sommet A de 90° (figure 13). Cependant, du point de vue de l'émission de champ, il est préférable d'obtenir une pyramide d'angle au sommet inférieur à 90°. Ainsi, pour cet exemple de la figure 12, on utilise après dépôt une solution d'attaque à base d'ions hydroxydes (par exemple K0H ou Na0H) à une température comprise entre 25 et 80°C environ. Ce type de solution présente en effet la particularité d'attaquer le cristal de silicium beaucoup plus rapidement (de 100 à 1000 fois) selon les directions 〈100〉 ou 〈110〉 que selon les directions 〈111〉 (voir par exemple l'article de K.E. BEAN dans IEEE Transactions on Electron Devices, ED-25 10, 1185 de 1978). Ainsi pour l'exemple précité (figure 12), la structure limitée par le plan (110) disparaît pour être remplacée par une structure 109A limitée par des plans (111) passant par le sommet de la pyramide ; il n'est pas nécessaire d'effectuer une opération de masquage supplémentaire. La hauteur H de la pyramide reste inchangée, mais les dimensions de sa base diminuent. On passe d'une pyramide 109 à angle au sommet A de 90° à une pyramide 109A à angle au sommet A' d'environ 70° (figure 14).For example (see Figure 12). if a silicon substrate with a surface orientation (100) is used and if a deposit is made from a mixture of SiH₄ + HCl in H₂ at approximately 1060 ° C., faceting is easily obtained (110) of the pyramid 109 which corresponds to an angle at the apex A of 90 ° (Figure 13). However, from the point of view of the field emission, it is preferable to obtain a pyramid with an angle at the top less than 90 °. Thus, for this example of FIG. 12, an attack solution based on hydroxide ions (for example KOH or NaOH) is used after deposition at a temperature of between 25 and 80 ° C. approximately. This type of solution has the particularity of attacking the silicon crystal much faster (from 100 to 1000 times) in the directions 〈100〉 or 〈110〉 than in the directions 〈111〉 (see for example the article by KE BEAN in IEEE Transactions on Electron Devices, ED-25 10, 1185 of 1978). Thus for the above example (Figure 12), the structure limited by the plane (110) disappears to be replaced by a structure 109A limited by planes (111) passing through the top of the pyramid; it is not necessary to perform an additional masking operation. The height H of the pyramid remains unchanged, but the dimensions of its base decrease. We go from a pyramid 109 with an angle at the apex A of 90 ° to a pyramid 109A with an angle at the apex A 'of approximately 70 ° (FIG. 14).

Pour réaliser l'attaque chimique de la pyramide 109, on peut aussi utiliser une solution à base d'éthylènediamine (EDA), de pyrocatéchol et d'eau et travailler à environ 100°C. On obtient ainsi une excellente sélectivité dans les vitesses d'attaque selon les directions cristallographiques précitées.To carry out the chemical attack on pyramid 109, it is also possible to use a solution based on ethylenediamine (EDA), pyrocatechol and water and work at around 100 ° C. Excellent selectivity is thus obtained in the attack speeds along the aforementioned crystallographic directions.

On va décrire une variante du procédé de l'invention, en référence aux figures 15 et 16.We will describe a variant of the process of the invention, with reference to Figures 15 and 16.

De même que décrit ci-dessus, la première étape consiste à déposer une couche 110 de matériau diélectrique sur un substrat 111 en matériau monocristallin. La seconde étape (figure 15) consiste à graver par RIE une cavité 112 dans la couche 110.As described above, the first step consists in depositing a layer 110 of dielectric material on a substrate 111 of monocrystalline material. The second step (FIG. 15) consists in etching a cavity 112 in the layer 110 by RIE.

La troisième étape consiste à déposer directement, sans se placer en conditions de sélectivité, du matériau polycristallin 113 sur le diélectrique 110 et du matériau monocristallin facetté 114 sur la surface 115 du substrat mise à nu par gravure de la cavité 112, ce matériau 114 formant une pyramide. De façon que la couche 113 soit en matériau bon conducteur et puisse servir de grille on la dope très fortement pendant la phase de dépôt. Si le substrat 111 est en silicium, le dépôt est effectué en utilisant une phase gazeuse mère composée de SiH₄ dilué dans un gaz porteur (H₂ ou He par exemple). Afin de diminuer la vitesse de dépôt du polycristal sur la silice 110 (pour ne pas avoir une couche 113 trop épaisse lorsque la pyramide 114 est achevée), on peut ajouter du HCl dans la phase gazeuse mais en quantité contrôlée afin de ne pas inhiber la nucléation du polysilicium 113 sur la silice 110. De préférence, le gaz dopant est alors de la phosphine PH₃, de façon à obtenir du silicium fortement dopé de type n tant au niveau de la pyramide monocristalline qu'au niveau du dépôt polycristallin 113 sur la silice 110. L'avantage de cette variante est que l'on obtient directement la micropointe et la grille lors de la même opération.The third step consists in depositing directly, without being placed in selectivity conditions, polycrystalline material 113 on the dielectric 110 and faceted monocrystalline material 114 on the surface 115 of the substrate exposed by etching of the cavity 112, this material 114 forming a pyramid. So that the layer 113 is made of a good conductive material and can serve as a grid, it is doped very strongly during the deposition phase. If the substrate 111 is made of silicon, the deposition is carried out using a mother gas phase composed of SiH₄ diluted in a carrier gas (H₂ or He for example). In order to reduce the rate of deposition of the polycrystal on the silica 110 (so as not to have a layer 113 which is too thick when the pyramid 114 is completed), HCl can be added to the gas phase but in a controlled amount so as not to inhibit the nucleation of polysilicon 113 on silica 110. Preferably, the doping gas is then phosphine PH₃, so as to obtain highly doped silicon of type n both at the level of the monocrystalline pyramid and at the level of the polycrystalline deposit 113 on the silica 110. The advantage of this variant is that the microtip and the grid are obtained directly during the same operation.

On a représenté en figure 17 un mode de réalisation possible d'une source d'électrons conforme à l'invention. Pour ce mode de réalisation, la source est formée sur un substrat monocristallin 116 sur lequel est déposée une couche diélectrique 117, puis une couche conductrice de grille 118. La cavité 119 gravée dans les couches 117,118 a une forme oblongue ce qui fait que la cathode 120 a une forme de prisme allongé.FIG. 17 shows a possible embodiment of an electron source according to the invention. For this embodiment, the source is formed on a monocrystalline substrate 116 on which is deposited a dielectric layer 117, then a conductive grid layer 118. The cavity 119 etched in the layers 117,118 has an oblong shape which means that the cathode 120 has an elongated prism shape.

Il est bien entendu que les cavités pratiquées dans les couches 102,103,104 (figure 8) ou dans la couche 110 (figure 15) peuvent avoir une forme superficielle quelconque, dont les côtés peuvent être alignés ou non avec des axes particuliers du plan du substrat. En particulier si le substrat est en GaAs, du fait de l'anisotropie de croissance on veillera à orienter l'axe général des ouvertures selon une direction permettant un facettage optimal tel que (111) par exemple ou bien d'indices plus élevés encore, tels que (221) ou (331).It is understood that the cavities formed in the layers 102, 103, 104 (Figure 8) or in the layer 110 (Figure 15) can have any surface shape, the sides of which may or may not be aligned with particular axes of the plane of the substrate. In particular if the substrate is made of GaAs, due to the growth anisotropy, care will be taken to orient the general axis of the openings in a direction allowing optimal faceting such as (111) for example or even higher indices, such as (221) or (331).

La source d'électrons conforme à l'invention peut être utilisée, seule ou en réseau de microsources, pour réaliser des dispositifs très divers, en lui adjoignant une anode d'accélération d'électrons, et le cas échéant d'autres électrodes. On peut ainsi réaliser des dispositifs électroluminescents des composants hyperfréquences, etc. On a représenté à titre d'exemple non limitatif en figure 18, un composant électroluminescent 121 qui comporte une source d'électrons 122 et une anode 123 en matériau électroluminescent refermant la cavité 124 au fond de laquelle a été formée la pointe de cathode 125. La source 122 comporte dans l'ordre un substrat monocristallin 126, par exemple en silicium, une première couche diélectrique 127, une couche métallique de grille 128 et une seconde couche diélectrique 129 qui peut être la couche de passivation précitée. La couche d'anode 123 est déposée sous vide poussé sur la couche 129, par exemple comme décrit dans EP-A-350 378 (la Demande de Brevet français no 88 09303).The electron source according to the invention can be used, alone or in a network of microsources, to produce very diverse devices, by adding to it an electron acceleration anode, and if necessary other electrodes. It is thus possible to produce electroluminescent devices of microwave components, etc. FIG. 18 shows, by way of nonlimiting example, an electroluminescent component 121 which comprises an electron source 122 and an anode 123 made of electroluminescent material closing the cavity 124 at the bottom of which the cathode tip 125 has been formed. The source 122 comprises in order a monocrystalline substrate 126, for example made of silicon, a first dielectric layer 127, a metal gate layer 128 and a second dielectric layer 129 which may be the aforementioned passivation layer. The anode layer 123 is deposited under vacuum on the layer 129, for example as described in EP-A-350 378 (French Patent Application No. 88 09303).

On va maintenant décrire un procédé permettant la réalisation d'un adressage matriciel de chaque micropointe ou de groupes de micropointes.We will now describe a method for performing a matrix addressing of each microtip or groups of microtips.

On part d'un substrat isolant monocristallin 130 sur lequel est hétéroépitaxié un matériau conducteur ou semiconducteur 131 (Figure 19B). On pourra par exemple utiliser un matériau tel que silicium hétéroépitaxié sur saphir (SOS pour Silicon on Sapphire) ou bien silicium hétéroépitaxié sur zircone stabilisée à l'oxyde d'Yttrium (YSZ pour "Yttria Stabilised Zirconia") ou bien encore silicium hétéroépitaxié sur sur Spinelle (Mg Al₂ 0₄) ou tout autre substrat composite connu de l'homme de l'art. La couche de silicium hétéroépitaxié sera d'une épaisseur typique de quelques microns à une centaine de microns ; ce silicium sera d'autre part fortement dopé n de manière à présenter une résistivité de quelques 10⁻³ ohm.cm.We start from a monocrystalline insulating substrate 130 on which a conductive or semiconductor material 131 is heteroepitaxied (Figure 19B). We could for example use a material such as heteroepitaxied silicon on sapphire (SOS for Silicon on Sapphire) or else heteroepitaxied silicon on zirconia stabilized with Yttrium oxide (YSZ for "Yttria Stabilised Zirconia ") or alternatively heteroepitaxial silicon on Spinel (Mg Al₂ 0₄) or any other composite substrate known to those skilled in the art. The layer of heteroepitaxied silicon will be of a thickness of a few microns to a hundred microns on the other hand, this silicon will be strongly doped n so as to have a resistivity of some 10⁻³ ohm.cm.

Avantageusement, on pourra utiliser une structure de départ présentée sur la figure 19A du type SIMOX ("Silicon isolation by IMplantation of OXygen") dans laquelle le silicium de la couche mince 132 est isolé du substrat 133 par une couche 134 formée par implantation ionique d'oxygène ou d'azote à très fortes doses (voir par exemple l'article de H.W. LAM IEEE Circuits and Devices Magazine Juillet 1987 vol 3, no4 page 6 pour plus de détails sur la méthode). On pourra aussi utiliser toute méthode connue de l'homme de l'art, de façon à obtenir une couche mince de silicium monocristallin sur un diélectrique non nécessairement monocristallin ; on pourra utiliser une méthode de recristallisation par lampe, par laser, par faisceau d'électrons ; on pourra utiliser une méthode type SDB (Silicon Direct Bonding) où la couche mince est obtenue par collage et amincissement ; on pourra utiliser une méthode de type épitaxie latérale forcée et.... Toutes ces méthodes sont rappellées par exemple dans EP-A 374 001 (la Demande de Brevet français 88 16212).Advantageously, it is possible to use a starting structure presented in FIG. 19A of the SIMOX type ("Silicon isolation by IMplantation of OXygen") in which the silicon of the thin layer 132 is isolated from the substrate 133 by a layer 134 formed by ion implantation of oxygen or nitrogen at very high doses (see eg Article HW LAM IEEE Circuits and Devices Magazine July 1987 vol 3, No. 4 page 6 for details on the method). One can also use any method known to those skilled in the art, so as to obtain a thin layer of monocrystalline silicon on a dielectric which is not necessarily monocrystalline; a recrystallization method can be used by lamp, by laser, by electron beam; we can use a SDB (Silicon Direct Bonding) method where the thin layer is obtained by bonding and thinning; we can use a method of forced lateral epitaxy type and .... All these methods are recalled for example in EP-A 374 001 (French Patent Application 88 16212).

La suite des opérations sera décrite en relation avec un substrat de type SIMOX (Figure 19A) mais on pourrait utiliser un substrat type celui de la figure 19B.The rest of the operations will be described in relation to a substrate of the SIMOX type (FIG. 19A), but a substrate such as that of FIG. 19B could be used.

La couche mince de silicium 132 est préalablement amenée à une épaisseur comprise typiquement entre quelques microns et une centaines de microns par épitaxie en phase vapeur. Elle est aussi dopée pendant cette même opération, de façon à amener sa résistivité à quelques 10⁻³ ohm.cm. On grave ensuite des bandes 135 de silicium de largeur typiquement de l'ordre de grandeur du pas de répétition des pointes soit environ 10 µm, de façon à mettre à nu le diélectrique sous-jacent Si0₂ ou Si₃N₄ entre les bandes. Ces bandes sont donc isolées entre elles comme le montre la figure 20. On dépose successivement sur cette structure trois couches : un diélectrique de grille 136, une métallisation de grille 137 et un diélectrique de passivation 138 (voir figure 21) ; on obtient sur chaque bande 135 de silicium monocristallin précédemment découpée une structure identique à celle représentée sur la figure 7. On réitère sur chaque bande de silicium monocristallin la suite d'opérations représentées sur les figures 8,9 e 10, de façon à obtenir la structure représentée sur la figure 22, où l'on a fait pousser des rangées de micropointes 139 sur chaque bande 135 de silicium monocristallin. On enduit ensuite l'ensemble de résine photosensible et on définit un masque de résine (non représenté ) se présentant sous forme de bandes perpendiculaires aux bandes 135 de silicium monocristallin précédemment définies. On grave le diélectrique supérieur 138 et la métallisation de grille 137 de façon à isoler entre elles les différentes bandes supportant les grilles ; on peut graver le diélectrique grille 136 comme cela est représenté sur la figure 23, mais ceci n'est toutefois pas nécessaire.The thin layer of silicon 132 is previously brought to a thickness typically between a few microns and a hundred microns by epitaxy in the vapor phase. It is also doped during this same operation, so as to bring its resistivity to a few 10⁻³ ohm.cm. Then etched bands 135 of silicon typically width of the order of magnitude of the repetition pitch of the tips is about 10 microns, so as to expose the underlying dielectric Si0₂ or Si₃N₄ between the bands. These bands are therefore isolated from each other as shown in FIG. 20. Three layers are successively deposited on this structure: a gate dielectric 136, a gate metallization 137 and a passivation dielectric 138 (see FIG. 21); a structure identical to that shown in FIG. 7 is obtained on each strip 135 of monocrystalline silicon previously cut out. The sequence of operations represented in FIGS. 8.9 e 10 is repeated on each strip of monocrystalline silicon, so as to obtain the structure shown in Figure 22, where rows of microtips 139 were grown on each strip 135 of monocrystalline silicon. The assembly is then coated with photosensitive resin and a resin mask is defined (not shown) in the form of strips perpendicular to the strips 135 of monocrystalline silicon previously defined. The upper dielectric 138 and the gate metallization 137 are etched so as to isolate between them the different bands supporting the grids; the gate dielectric 136 can be etched as shown in FIG. 23, but this is however not necessary.

Pour obtenir l'émission électronique sur un point seulement, on polarise la ligne j à une cinquantaine de Volts et on maintient la colonne k à la masse par exemple ; ou bien on polarise la ligne j à 25 V et la colonne k à - 25 V en maintenant l'ensemble des autres lignes et colonnes à la masse. Seul le point A situé à l'intersection de la ligne j et de la colonne k va émettre des électrons.To obtain the electronic emission on one point only, the line j is polarized at around fifty Volts and the column k is kept for ground, for example; or else the line j is polarized at 25 V and the column k at - 25 V while keeping all the other lines and columns grounded. Only point A located at the intersection of row j and column k will emit electrons.

L'homme de l'art pourra aisément trouver d'autres variantes pour arriver à la structure représentée par la figure 23 en partant de la structure représentée figure 19A ou 19B.Those skilled in the art can easily find other variants to arrive at the structure shown in FIG. 23 starting from the structure shown in FIG. 19A or 19B.

Claims (33)

  1. Process for fabricating electron sources of the field-emission type, characterized in that it consists in using a single mask in order to etch, in a first layer (2, 102, 110, 117, 127) of insulating material covering a monocrystalline substrate (1, 1', 101, 111, 116, 126), windows defining, on the substrate, areas for nucleating the points (4, 109, 114, 120, 125) of these sources by epitaxial and facetted growth of conducting or semiconductor material, these nucleation areas being at least partially electrically conducting, and in order to etch cavities concentric with the points in the layers (3, 5, 103, 113, 128) of conducting materials and of insulating materials (2', 129) covering the said first layer of insulating material.
  2. Fabrication process according to Claim 1, characterized in that it comprises the following steps:
    - formation of a first insulating layer (2) at the surface of the monocrystalline layer;
    - removal of the insulating layer (2) from elementary areas which are suitably oriented with respect to the crystallographic directions of the plane of the substrate;
    - facetted epitaxial growth of silicon in the elementary areas of the substrate thus revealed in order to form the points (4);
    - deposition of a thin metal layer (5) and then of a second insulating layer (2') and of a second thin metal layer (3) onto the assembly,
    - removal of the second metal layer and of the second insulating layer from the points in order to reveal the points covered with the first metal layer forming the cathodes, the second metal layer enabling the array of associated gates to be formed by etching.
  3. Fabrication process according to Claim 1, characterized in that it comprises the following steps:
    - formation of a first insulating layer (2) at the surface of the highly n⁺-doped monocrystalline layer (1);
    - removal of the insulating layer (2) from square elementary areas of sides suitably oriented with respect to the crystallographic axes of the monocrystalline layer;
    - epitaxial and facetted growth of metallic or semiconductor material in the elementary areas of the monocrystalline layer which are thus revealed, in order to form the points (4);
    - deposition of a second insulating layer (2') at the surface of the assembly;
    - removal of the second insulating layer from the points;
    - deposition of a thin metal layer onto the assembly, which, because of the geometry of the assembly at the end of the previous phase, is deposited, on the one hand, onto the plane insulating layer enabling an array of gates (3) to be formed and, on the other hand, onto the facets of the pyramidal points in order to form the emitting cathodes (4).
  4. Fabrication process according to one of the preceding claims, characterised in that the epitaxial growth is carried out by using a gaseous mother phase doped and diluted in a carrier gas.
  5. Process according to Claim 4, characterized in that the mother gaseous phase comprises SiH₄ and that the carrier gas is H₂ or He.
  6. Process according to Claim 4 or 5, characterized in that HCl is added to the gaseous phase.
  7. Process according to one of Claims 4 to 6, characterized in that the doping gas is PH₃.
  8. Fabrication process according to one of Claims 2 to 7, characterized in that the first insulating layer (2) is produced by thermal oxidation of the monocrystalline layer (1), the metal layers being made of tungsten, and the second insulating layer of nitride.
  9. Process according to one of Claims 2 to 8, characterized in that at least one of the insulating layers is produced by deposition.
  10. Process according to Claim 9, characterized in that the deposition is performed by one of the following processes: evaporation, sputtering or the CVD process.
  11. Fabrication process according to one of Claims 2 to 10, characterized in that the removal of the layers from the elementary areas is carried out by deposition of a masking resin, masking and selective removal of the non-masked areas.
  12. Array of emitters obtained by the fabrication process according to any one of Claims 1 to 10, characterized in that an array of gates has been etched in the upper plane thin metal layer and in that an array of cathodes connects the emitting points.
  13. Process according to Claim 1, characterized in that at least one layer (102, 110) of dielectric material is deposited onto a monocrystalline substrate (101, 111), in that at least one cavity (105, 112) is etched in the deposited layer and in that a cathode point (109, 114) is formed at the bottom of each cavity by nucleated and crystalline growth on the substrate and facetted growth, a layer of electrically conducting material serving as a gate (104, 113) being formed on the layer of dielectric material.
  14. Process according to Claim 13, characterized in that the polycrystalline layer (113) of electrically conducting material is formed during the same deposition operation as the monocrystalline cathode point (114).
  15. Process according to Claim 14, using an Si substrate, characterized in that the layer of electrically conducting material and the cathode point are formed by using a doped mother gaseous phase doped and diluted in a carrier gas.
  16. Process according to Claim 15, characterized in that the mother gaseous phase comprises SiH₄ and that the carrier gas is H₂ or He.
  17. Process according to Claim 15 or 16, characterized in that HCl is added to the gaseous phase.
  18. Process according to one of Claims 15 to 17, characterized in that the doping gas used is PH₃.
  19. Process according to Claim 13, characterized in that the layer (104) of electrically conducting material is formed on the dielectric layer before etching the cavity.
  20. Process according to Claim 19, characterized in that a second layer (104) of dielectric material is deposited onto the layer of electrically conducting material.
  21. Process according to one Claims 19 or 20, characterized in that the material with which the second dielectric layer (104) is made is different from the material with which the first dielectric layer (102) is made and that the cross-section of the cavity in the first dielectric layer is increased by selective chemical etching.
  22. Process according to Claim 21, for a first SiO₂ dielectric layer, characterized in that the selective chemical etching is performed using HF.
  23. Process according to one of Claims 19 to 22, characterized in that the microcathode point is formed under conditions of facetted selective epitaxy.
  24. Process according to Claim 23, for an Si substrate, characterized in that the selective epitaxy is performed in a CVD reactor at a temperature between 900 and 1100°C by using a gaseous mixture comprising SiH₄ + HCl or SiH₂Cl₂ + HCl in carrier hydrogen.
  25. Process according to Claim 23, for a GaAs substrate, characterized in that the selective epitaxy is performed between 600 and 800°C in a VPE reactor using a gaseous mixture comprising AsCl₃ diluted in H₂ and a source of solid gallium.
  26. Process according to Claim 23, for a GaAs substrate, characterized in that the selective epitaxy is performed in a reduced-pressure MOCVD reactor.
  27. Process according to one of Claims 20 to 26, characterized in that the second layer (104) of dielectric material is removed by selective chemical etching.
  28. Process according to one of Claims 13 to 27, characterized in that, when the facetting of the cathode point does not make it possible to obtain (111) planes, a subsequent selective chemical etch of this point is undertaken making it possible to obtain this (111) facetting.
  29. Process according to Claim 28, for an Si substrate, characterized in that a solution based on hydroxide ions, such as KOH or NaOH, is used for the selective chemical etching.
  30. Process according to Claim 28, characterized in that a solution based on ethylenediamine is used for the selective chemical etching.
  31. Component using an electron source produced according to the process of one of Claims 1 to 11 or 13 to 30.
  32. Component according to Claim 31, characterized in that the component is an electroluminescent component (121) comprising an anode layer (123) made of electroluminescent material enclosing the cavity (124) at the bottom of which the cathode point (125) has been formed.
  33. Component according to Claim 31 or 32, characterized in that it has a matrix structure in the form of rows and columns.
EP89904094A 1988-03-25 1989-03-24 Process for manufacturing sources of field-emission type electrons, and application for producing emitter networks Expired - Lifetime EP0365630B1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FR8803949 1988-03-25
FR8803949A FR2629264B1 (en) 1988-03-25 1988-03-25 METHOD FOR MANUFACTURING FIELD-EMITTING POINT TRANSMITTERS AND ITS APPLICATION TO THE PRODUCTION OF TRANSMITTER ARRAYS
FR8903153 1989-03-10
FR8903153A FR2644287B1 (en) 1989-03-10 1989-03-10 METHOD FOR PRODUCING FIELD EMISSION TYPE ELECTRON SOURCES AND DEVICES MADE FROM SAID SOURCES

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EP0365630A1 EP0365630A1 (en) 1990-05-02
EP0365630B1 true EP0365630B1 (en) 1994-03-02

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EP (1) EP0365630B1 (en)
JP (1) JPH02503728A (en)
DE (1) DE68913419T2 (en)
WO (1) WO1989009479A1 (en)

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US5090932A (en) 1992-02-25
JPH02503728A (en) 1990-11-01
DE68913419D1 (en) 1994-04-07
EP0365630A1 (en) 1990-05-02
WO1989009479A1 (en) 1989-10-05
DE68913419T2 (en) 1994-06-01

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