EP0349392B1 - Numerical timer with constant resolution - Google Patents

Description

The present invention relates to the field of digital timers whose most common application is relay control.

An object of the present invention is to provide such a timer with an extended time range.

Another object of the present invention is to provide such a timer, the components of which can be produced essentially in the form of an integrated circuit.

EP-A-0 009 870 discloses a timer comprising a first down counter, in fact a chain of binary down counters, coding wheels of a duration to be counted down and a second down counter, or more exactly a shift register, for controlling in particular display points for counting down periods of the time to be counted down.

However, this timer does not indicate the effective time remaining during its operation.

The present invention also aims to overcome this drawback and therefore to provide a timer with display of the remaining time.

To this end, the present invention provides a digital timer with constant resolution comprising a clock, a chain of binary down counters, each of which corresponds to a time range multiple of that of the previous down counter, and display point control means, characterized by the fact that the binary outputs of the downcounters are sent in parallel to display points of a first set of display points, validation means being provided so that only the output of the most significant down-counter not zero activates the display points, and a display point of a second set of display points is associated with each down-counter so that only the display point corresponding to the most significant non-zero down-counter is actuated.

According to an embodiment of the present invention, the binary downcounters are respectively a down counter by 16, at 4 bits, receiving clock pulses at 16 hertz and three down counters by 60, at 6 bits, receiving the output of the previous down counter, to provide counts of sixteenths of seconds, seconds, minutes, and hours, the first set of display points comprising six display points and the second set of display points comprising four display points.

According to an embodiment of the present invention, there is further provided a display point controlled to be active when all the down counters are at zero.

According to an embodiment of the present invention, each down counter is associated with a memory which stores the set value of this down counter; each down-counter, except that of the highest rank to which is assigned a non-zero set value which is loaded at its set value, is initially loaded at its maximum value; each down-counter includes an end of down-count indication output which is used to validate the loading in the down-counter of immediately lower rank of the associated set value, to validate the connection of the binary outputs of this down-down down counter to the first set display points, and cause the display point of the second set associated with the down counter to be activated.

• la figure 1 représente de façon très schématique la conception d'ensemble d'une minuterie selon la présente invention ;
• la figure 2 représente sous forme de blocs et de façon simplifiée les circuits d'affichage utilisés dans une minuterie selon la présente invention ; et
• la figure 3 représente de façon plus détaillée un exemple de réalisation du dispositif d'affichage et de décomptage de temps d'une minuterie selon la présente invention.

These objects, characteristics and advantages as well as others of the present invention will be explained in more detail in the following description of particular embodiments made in relation to the attached figures, among which:

• Figure 1 very schematically shows the overall design of a timer according to the present invention;
• FIG. 2 shows in block form and in a simplified manner the display circuits used in a timer according to the present invention; and
• FIG. 3 shows in more detail an exemplary embodiment of the device for displaying and counting down a timer according to the present invention.

This timer revolves around a down count block 10 comprising for example four down counters 11, 12, 13 and 14. This block 10 is associated with a time base 20 coupled to a quartz 21. There are quartz at low cost having a piezoelectric resonant frequency at 32,768 hertz. If the time base divides this frequency by 2048, 16 hertz signals are obtained at the output, that is to say that the first countdown module 11 receives pulses at a frequency of one sixteenth of a second. From there, we can choose that the down-counter 11 is a divider by 16 and the other down-counters 12, 13 and 14 are the dividers by 60. We will thus obtain at the output of the down-counter 12 a pulse every second, at the output of the down counter 13 a pulse every minute and at the output of down counter 13 a pulse every hour. In other words, the down counter 11 will count 16ths of a second, the down counter 12 of the seconds, the down counter 13 of the minutes and the down counter 14 of the hours.

To set the duration of the timer, there is conventionally provided an adjustment block 30 actuated for example by a set of push buttons 31 making it possible to fix in a preselection block 32 selected timer durations in hours, minutes, seconds and sixteenths of a second. The information collected in this preselection block 32 will be supplied to a non-volatile memory block 33, consisting for example of EEPROM, NOVRAM, RAM saved by batteries or supercapacitors, etc. Also, a connection block 34 is provided in a conventional manner making it possible to directly couple the memory block to a bus connected to an external processor.

These blocks 30 to 34 will not be described in more detail because they are relatively conventional and there are similar devices in other devices, for example digital clocks. It should only be remembered here that the information corresponding to the chosen delay time has been stored in non-volatile memories contained in block 33. This block 33 can, as shown, be divided into word memories 33-1 33-2 33-3 and 33-4, respectively 4 bits for block 33-1 and 6 bits for blocks 33-2 at 33-4.

The total countdown output Z of the countdown block 10 is supplied to a function block 40 receiving an input from an input circuit 41, a power supply (also intended for the other blocks of the system during operation or initial adjustment) 42 , and an output circuit 43 providing a control signal intended for example to actuate an electro-mechanical or static relay. The function block makes it possible to send start (PRESET) or reset (RESET) signals to the countdown block according to programs memorized in advance, as is conventional in the field of timers, for example to obtain that the timer only starts after a specific time or after the arrival of a particular input, that the output starts with a high or a low level, etc. These blocks 40 to 43 which are also relatively conventional will not be described here in detail since they already exist in other timers.

Finally, the various blocks and in particular the countdown block 10 are connected to a display block 50 in which the display points consist of light-emitting diodes. This display unit makes it possible to activate, in a manner which will be explained in more detail below, a first set of light-emitting diodes 51 which light up as a function of the state of the binary outputs of a particular down-counter. countdown block. Six diodes are shown here designated by "1", "2", "4", "8", "16", "32", for the case where the downcounters comprise six binary outputs. A second set of light-emitting diodes 52 is provided so that one of its diodes is lit to indicate the down-counter whose value is displayed by block 51. In the case of the previous example, these diodes are marked "H", "M", "S" and "1/16" to show that they refer to each of the hours, minutes, seconds and 1 / 16th of a second counters respectively. A diode 53 is provided to light up when all the downcounters are at zero (and possibly to flash during the adjustment phase). A diode 54 reflects the start of the power supply and a diode 55 reflects the fact that the output is at high or low level.

Thus, the same diodes in the diode assembly 51 are used to indicate the time remaining during the operation of the timer.

For example, if you have chosen a timer duration of 35 hours, 30 minutes, 16 seconds, 5 / 16ths of a second, the first display will translate the value 35 (LEDs "32", "2" and "1" lit) while diode "H" of group 52 will be on. This duration in hours decreases while the down counter 14 counts down. When the down-counter 14 reaches zero, the diode "H" of group 52 will go out while the indicator "M" of this same group will light up and the value 30 will be displayed (diodes 16, 8, 4 and 2) then this countdown will be decremented until the countdown of the minute countdown 13 ends. Then, the indicator "S" will light up at the same time as the indicator "16" of group 51 to show that there are 16 seconds to go. Finally, the 1/16 indicator of group 52 will light up and the display of its countdown will appear extremely quickly.

FIG. 2 very schematically shows in the form of blocks the coupling between the downcounters 11 to 14 and the diodes of the groups of diodes 51 and 52. To simplify the figure, each downcounter is shown with only three binary outputs and therefore only three diodes in the diode group 51, these diodes being marked "1", "2" and "4". The binary outputs Q2, Q1 and Q0 of each of the down counters 11 to 14 are connected via respective validation circuits 61 to 64 to the diodes "1", "2", "4" and logic circuits are provided to validate each of circuits 61 to 64 and activate the corresponding diode of group 52 only when the corresponding down-counter is the most significant down-counter whose output is non-zero. This is symbolized by the link between the zero crossing indication outputs (Z) of each of the downcounters and the blocks 61 to 64.

In the case of this figure, it is assumed that the output (Z) of a down-counter is at 1 when it is not zero and goes to zero when this down-counter is empty. The output Z of the most significant down-counter 14 is connected directly to the validation input of circuit 64 and to the diode H. The validation inputs of circuits 61 to 63 are connected to the input Z of the corresponding down-counters 11 to 13 by means of AND gates 71 to 73, the other input of which receives the inverse of the output signal Z of the up-down counter.

FIG. 3 shows in more detail an embodiment of the present invention and more precisely connections between the downcount block 10 and the memory 33 and display 50 blocks of FIG. 1. We take the case of the numerical examples of figure 1.

• six entrées de programmation D0 à D5 (quatre pour le décompteur 11),
• six sorties binaires de décomptage Q0 à Q5 (quatre pour le décompteur 11),
• une sortie Z qui est à niveau bas (0) quand un décompteur est programmé ou est en cours de décomptage et qui passe à niveau haut (1) quand le décompteur a achevé son décomptage, si l'entrée CF est elle-même au niveau haut,
• une entrée MR de remise à zéro,
• une entrée PE permettant la programmation du décompteur à la valeur fixée par les entrées D0 à D5,
• une entrée CF de programmation du décompteur à sa valeur maximale, et
• une entrée d'horloge CL.

Each of the downcounters 11, 12, 13, 14 comprises:

• six programming inputs D0 to D5 (four for down-counter 11),
• six binary down-counting outputs Q0 to Q5 (four for down-counter 11),
• a Z output which is low level (0) when a down-counter is programmed or is in the process of down-counting and which goes to high level (1) when the downcounter has completed its downcounting, if the CF input is itself at the high level,
• a reset MR input,
• a PE input allowing the programming of the down-counter to the value fixed by the inputs D0 to D5,
• a CF input for programming the down-counter to its maximum value, and
• a clock input CL.

The input CL of each of the downcounters is connected to the binary output of highest rank of the previous downcounter except for the downcounter 11 which receives the clock signal at 16 hertz.

The PE input of the highest rank down counter, the down counter 14, receives the PRESET signal from the function block (see FIG. 1). The PE inputs of the other downcounters are connected to the output 7 of the downcounter of immediately higher rank by means of a circuit 70 for shaping pulses consisting of two inverters connected to each other by means of a differentiator.

All MR inputs of the downcounters are connected to the RESET input from the function block (see Figure 1) to allow resetting to zero.

The CF input of the highest-ranked down-counter is not connected and the CF inputs of the other down-counters are connected to the Z output of the next-highest down-counter.

As explained in the case of the simplified example of FIG. 2, the outputs Q0 to Q5 of the down counters 12, 13 and 14 and the outputs Q0 to Q3 of the down counter 11 are connected to the first set of light-emitting diodes 51, respectively "1" to "32", via validation circuits 61 to 64. These circuits validation consist of controlled inverters as shown in Figure 3. The control input of each of the validation blocks is connected to the output Z via an inverter 71 for the highest rank down counter and an ET 72 gate for the other down counters. Each gate 72 receives on a first inverting input the output Z of the corresponding down-counter and on a second non-inverting input the output Z of the down-counter of immediately superior rank. In addition, the output of the inverter 71 and those of each of the AND gates 72 are connected via inverters 73 to the respective light-emitting diodes, "H", "M", "S", "1 / 16 ", from the second group of diodes 52. In addition, the LED for displaying the end of the downcounting of the whole of the downcounter block, designated by the reference 53 in FIGS. 1 and 3, is connected to the output Z of the downcounter. lower row 11 by means of an inverter 74. This output Z of the down-counter 11 also corresponds to the output 80 of the down-count block.

The operation of this device will be described below.

It is assumed that memories 33-4 to 33-1 contain the values in hours, minutes, seconds and 16ths of a second chosen for the timer. When the down-counter start signal is supplied (the PRESET signal), the down-counter 14 is loaded with the value of memory 33-4, the down-counters 11, 12 and 13 having a level 0 on their CF inputs, each of which is connected at the output Z of the previous down-counter so that these down-counters are loaded to their maximum value (60 for down-counters 12 and 13, and 16 for down-counter 11). The downcounting of the downcounter 14 then occurs at the rate imposed by the preceding chain of downcounters, that is to say that this down-counter decrements its binary outputs by one unit every hour. The group 52 light-emitting diode "H" is on and the group 51 light-emitting diodes reflect the time remaining in hours.

Once the down-counter 14 has completed its down-counting, the passage to 1 of its output Z inhibits the input CF of the next down-counter and validates the input PE of this down-counter so that it is loaded at the value programmed in the corresponding memory. The corresponding light-emitting diode of group 52 lights up and the diodes of group 51 progressively indicate the remaining time. The process is then repeated for the following down counters until a signal is supplied on the output 80 when the down counter 11 has completed its counting.

It will be noted from the above description that the present invention can be implemented simply in the form of an integrated circuit because it includes only conventional and easily integrated components (doors and reversers). In addition, an advantage of the general organization of the structure according to the invention is that it requires a minimum number of memory points in order to keep programming information of a timer retentively.

Claims (5)

1. A digital timer with constant resolution, comprising a clock, a chain of binary down-counters (11-14) each of which corresponds to a time range which is a multiple of that of the preceding down-counter, and means for controlling display points, characterized by the fact that the binary outputs of the down-counters are fed in parallel to display points of a first set of display points (51), enabling means (61-64) being provided so that only the output of the most significant down-counter not at zero actuates the display points, and a display point of a second set of display points (52) is associated with each down-counter so that only the display point corresponding to the most significant down-counter not at zero is actuated.
2. The timer according to claim 1, characterized by the fact that said binary down-counters are respectively a four bit down-counter down-counting by 16, receiving 16 Hz clock pulses and three 6 bit down-counters down-counting by 60, receiving the output of the preceding down-counter, for delivering 1/16 second, second, minute and hour counts, the first set of display points (51) comprising six display points and the second set of display points (52) comprising four display points.
3. The timer according to claim 2, characterized by the fact that it further comprises a display point (53) controlled so as to be active when all the down-counters are at zero.
4. The timer according to any of the claims 1 to 3, characterized by the fact that :
      each down-counter is associated with a memory (33-1 to 33-4) which stores the reference value of this down-counter, each down-counter except that of the higher rank to which a non zero reference value is assigned which is loaded to its reference value, is initially loaded to its maximum value,
      each down-counter comprises an end of down-count indication output which is used for enabling loading in the down-counter of immediately lower rank the associated reference value, for enabling the connection of the binary outputs of this lower rank down-counter to the first set of display points and causing activation of the display point of the second set associated with the lower rank down-counter.
5. The timer according to any of the claims 1 to 4, wherein each display point is formed by a light emitting diode.

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