EP0334932A1 - Circuitry for processing video components - Google Patents

Circuitry for processing video components

Info

Publication number
EP0334932A1
EP0334932A1 EP88908859A EP88908859A EP0334932A1 EP 0334932 A1 EP0334932 A1 EP 0334932A1 EP 88908859 A EP88908859 A EP 88908859A EP 88908859 A EP88908859 A EP 88908859A EP 0334932 A1 EP0334932 A1 EP 0334932A1
Authority
EP
European Patent Office
Prior art keywords
chrominance
components
multiplexer
luminance
pct
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP88908859A
Other languages
German (de)
French (fr)
Inventor
Heinz-Werner Keesen
Laurent Perdrieau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Deutsche Thomson Brandt GmbH
Original Assignee
Deutsche Thomson Brandt GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche Thomson Brandt GmbH filed Critical Deutsche Thomson Brandt GmbH
Publication of EP0334932A1 publication Critical patent/EP0334932A1/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/64—Circuits for processing colour signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N11/00—Colour television systems
    • H04N11/06—Transmission systems characterised by the manner in which the individual colour picture signal components are combined
    • H04N11/08—Transmission systems characterised by the manner in which the individual colour picture signal components are combined using sequential signals only
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/64—Circuits for processing colour signals
    • H04N9/641—Multi-purpose receivers, e.g. for auxiliary information

Definitions

  • the invention relates to a circuit arrangement for processing video components.
  • the CVBS signal is processed digitally.
  • the CVBS signal is digitally processed in an A / D converter, in a digital color decoder the signal * is divided into the components of the Y signal and the components of U and V signals.
  • the signals are transmitted on the same lines at different times by means of a multiplexer at the output. They are then stored in image memories.
  • multiplexers are usually used. When using multiplexers, only one analog / digital conversion is required for all three signals. To do this, however, the analog / digital converter must operate at a high sampling rate in order to achieve the most original possible reproduction image.
  • the output signal of the multiplexer is fed to an analog / digital converter, then the samples are stored and read out at a higher frequency in order to achieve the horizontal compression of the image.
  • For vertical compression one of three or four lines of the incoming video source is analyzed. The reduction ratio is selected depending on the result. If necessary, a vertical filter is also used.
  • the reduced picture is superimposed on the main picture.
  • the invention is based on the object of specifying a circuit for the preparation of a first video image which allows the first video image to be reproduced in a second video image with little effort.
  • the subsampling entails loss of information.
  • these information losses are due to the necessary reduction ratio, which ches, for example, is a quarter of the main image reproduced, tolerable.
  • the luminance and the color difference components can be selected.
  • the two signal components luminance and chrominance
  • both the same horizontal filter structure is used and only one analog / digital converter, each of the video signal components being subjected to undersampling.
  • Fig. 1 shows a circuit arrangement for processing video components by means of a multiplexer arrangement.
  • Fig. 2 is a timing diagram
  • the 2: 1 multiplexer is switched at a frequency FH / 8 which is one eighth of the line frequency, so that after every fourth line the inputs V of the multiplexer 2 are switched of the 2: 1 multiplexer 2 and the output of the low-pass filter 5, to which the luminance signal Y is present, are routed to a 2: 1 multiplexer 3 which is switched with a frequency FV / 2.
  • the frequency FV / 2 corresponds to half
  • the inputs of the multiplexer.3 are thus switched over with every field change.
  • the switching frequencies FH / 8, FV / 2 of the multiplexers 2, 3 are centralized by the synchronous separation circuit and clock e 6 and generated by dividers 7, 8.
  • the output of the multiplexer 3 leads to an - H-
  • FIG. 2a shows the line pulses and FIG. 2b the switching frequency FH / 8 generated from them by the synchronous separation circuit and clock center 6 and the divider 8.
  • 2c shows the image pulses and FIG. 2d the switching frequency FV / 2 generated from them by the synchronous separation circuit and clock center 6 and the divider 7.
  • the half-images are converted from a frame using the multiplexers 2, 3 e.g. processed in such a way that the luminance signal Y is used in the first field and the color difference signals U and V are used in the other field.
  • the luminance signal Y is fed to the digital / analog converter 4 from incoming image signals for the first field.
  • the next field contains only the information of the two color difference signals U or V, the first four continuous lines containing the first color component U of the field and the next four continuous lines containing the second component V. This process is repeated for the entire second field.

Abstract

PCT No. PCT/EP88/00865 Sec. 371 Date May 25, 1989 Sec. 102(e) Date May 25, 1989 PCT Filed Sep. 27, 1988 PCT Pub. No. WO89/03155 PCT Pub. Date Apr. 6, 1989.A video signal processor as for generating a picture-in-picture signal, generates respective analog luminance components and first and second analog chrominance components. In order to reduce the system hardware and processing speed, multiplexing circuitry subsamples the luminance and chrominance components on a field basis to provide alternating fields of only luminance and only chrominance signal. The multiplexing circuitry further subsamples the chrominance components by providing groups of horizontal lines of only the first chrominance component alternating with groups of horizontal lines of only the second chrominance component.

Description

Schaltungsanordnung zur Bearbeitung von Videokomponenten Circuit arrangement for processing video components
Die Erfindung betrifft eine Schaltungsanordnung zur Bearbei¬ tung von Videokomponenten.The invention relates to a circuit arrangement for processing video components.
Aus "Funkschau" Band 25, Seite 53, 1985 ist eine digitale Bildwiedergabe bekannt, bei dem das FBAS Signal digital ver¬ arbeitet wird. Dazu wird das FBAS Signal in einem A/D-Wand- ler digital aufbereitet, in einen digitalen Farbdecodern wird das Signal* aufgeteilt in die Komponenten des Y-Signals und die Komponenten U- und V-Signale. Zur Vermeidung eines übermäßigen Leitungsaufwandes werden die Signale mittels ei¬ nes Multiplexers am Ausgang zeitlich versetzt auf den selben Leitungen übertragen. Anschließend werden sie in Bildspei¬ chern gespeichert.From "Funkschau" volume 25, page 53, 1985, digital image reproduction is known in which the CVBS signal is processed digitally. For this purpose, the CVBS signal is digitally processed in an A / D converter, in a digital color decoder the signal * is divided into the components of the Y signal and the components of U and V signals. To avoid excessive line expenditure, the signals are transmitted on the same lines at different times by means of a multiplexer at the output. They are then stored in image memories.
Bei der Digitalisierung eines Farbbildes, das z.B. in einem anderen Farbbild wiedergegeben werden soll und dessen Größe kleiner ist als die des anderen Farbbildes, entstehen Proble¬ me beim Multiplexen der Luminanz und der Chrominanz oder der Signale rot, grün und blau.When digitizing a color image, e.g. Should be reproduced in a different color image and its size is smaller than that of the other color image, problems arise when the luminance and chrominance or the signals red, green and blue are multiplexed.
Um den Aufwand bei der Analog/Digital-Umwandlung eines Video¬ signals zu minimieren, werden üblicherweise Multiplexer ver¬ wendet. Bei der Verwendung von Multiplexern ist nur eine Ana- log/Digital-U setzung für alle drei Signale erforderlich. Dafür muß der Analog/Digital-Wandler jedoch mit einer hohen Abtastrate arbeitet, um ein möglichst originales Wiedergabe¬ bild zu erzielen.In order to minimize the effort involved in the analog / digital conversion of a video signal, multiplexers are usually used. When using multiplexers, only one analog / digital conversion is required for all three signals. To do this, however, the analog / digital converter must operate at a high sampling rate in order to achieve the most original possible reproduction image.
Es gibt mehrere verschiedene Lösungen, die einzelnen Abtast¬ werte des Videosignals durch den Multiplexer sequentiell an¬ zuordnen. Z.B. kann eine Zeile einen YUYV Datenfluß enthal¬ ten, wobei Y das Luminanzsignal und U und V die Chrominanzsi¬ gnalanteile (U = B - Y, V = R - Y) sind. . - I -There are several different solutions that sequentially assign individual sample values of the video signal by the multiplexer. For example, a line can contain a YUYV data flow, where Y is the luminance signal and U and V are the chrominance signal components (U = B - Y, V = R - Y). , - I -
Das Ausgangssignal des Multiplexers wird einem Analog/Digi- tal-Converter zugeführt, anschließend werden die Abtastwerte gespeichert und mit einer höheren Frequenz ausgelesen, um die horizontale Kompression des Bildes zu erzielen. Für die vertikale Kompression wird eine von drei oder vier Zeilen der eingehenden Videoquelle analysiert. Abhängig von dem Er¬ gebnis wird das Reduktionsverhältnis gewählt. Falls erforder¬ lich wird ein vertikales Filter zusätzlich verwendet.The output signal of the multiplexer is fed to an analog / digital converter, then the samples are stored and read out at a higher frequency in order to achieve the horizontal compression of the image. For vertical compression, one of three or four lines of the incoming video source is analyzed. The reduction ratio is selected depending on the result. If necessary, a vertical filter is also used.
Am Ausgang der Digital/Analog-Umsetzung, für die wegen der Signale Y, U und V drei Convertern benötigt werden, wird das reduzierte Bild dem Hauptbild überlagert.At the output of the digital / analog conversion, for which three converters are required due to the signals Y, U and V, the reduced picture is superimposed on the main picture.
Die bis heute entwickelten Konzepte wurden in der Art und Weise realisiert, daß ein zusätzliches Modul zur Bildbearbei¬ tung in einem normalen Fernsehgerät eingefügt und die Verbin¬ dungen dazu minimiert wurde. Weiterhin wird eine hohe Multi- plexfrequenz verwendet, um eine korrekte Bandbreite für jede Videokomponente zu erzielen.The concepts developed to date have been implemented in such a way that an additional module for image processing is inserted in a normal television set and the connections to it have been minimized. A high multiplexing frequency is also used to achieve a correct bandwidth for each video component.
Der Erfindung liegt die Aufgabe zugrunde, eine Schaltung für die Aufbereitung eines ersten Videobildes anzugeben, welches die Wiedergabe des ersten Videobildes in einem zweiten Video¬ bild mit geringem Aufwand erlaubt.The invention is based on the object of specifying a circuit for the preparation of a first video image which allows the first video image to be reproduced in a second video image with little effort.
Diese Aufgabe wird durch die im Patentanspruch 1 angegebenen Maßnahmen gelöst.This object is achieved by the measures specified in claim 1.
Erfindungsgemäß wird vorgeschlagen, zwecks Datenreduktion das ankommende Videosignal unterabzutasten. Die Unterabtastung bringt zwar Informationsverluste mit sich. Diese Informationsverluste sind bei z.B. einer Standbildwie¬ dergabe, bei der Wiedergabe mittels eines Bildschirmes klei¬ ner Größe oder Wiedergabe eines zweiten Bildes in einem er¬ sten Bild wegen des notwendigen Reduktionsverhältnisses, wel- ches z.B. bei einem Viertel des wiedergegebenen Hauptbildes liegt, tolerierbar.According to the invention it is proposed to subsample the incoming video signal for data reduction. The subsampling entails loss of information. In the case of, for example, a still picture reproduction, when reproducing by means of a screen of small size or when reproducing a second picture in a first picture, these information losses are due to the necessary reduction ratio, which ches, for example, is a quarter of the main image reproduced, tolerable.
Für die Bearbeitung des Videosignals können z.B. die Luminanz und die Farbdifferenzkomponenten gewählt werden. Für die beide Signalanteile (Luminanz und Chrominanz) wird sowohl die selbe Horizontalfilterstruktur verwendet als auch nur ein Analog/Digital-Converter, wobei jedes der Videosi¬ gnalkomponenten einer Unterabtastung unterworfen wird.For processing the video signal e.g. the luminance and the color difference components can be selected. For the two signal components (luminance and chrominance) both the same horizontal filter structure is used and only one analog / digital converter, each of the video signal components being subjected to undersampling.
Im folgenden wird ein vorteilhaftes Ausführungsbeispiel anThe following is an advantageous embodiment
Hand der Zeichnung erläutert. Es zeigt:Hand explained the drawing. It shows:
Fig. 1 eine Schaltungsanordnung zur Bearbeitung von Video komponenten mittels einer Multiplexeranordnung. Fig. 2 ein ZeitdiagrammFig. 1 shows a circuit arrangement for processing video components by means of a multiplexer arrangement. Fig. 2 is a timing diagram
Am Eingang IN der in Fig. 1 gezeigten -Schaltungsanordnung liegt das" Videosignal an. Es wird auf den Eingang eines Farbdecoders 1, eines Tiefpaßfilters 5 und einer Synchronab¬ trennschaltung und Taktzentrale 6 geführt. Am Ausgang des Farbdecoders 1 liegen die ChrominanzSignale U, V an, die auf einen 2:1 Multiplexer 2 geführt werden. Der 2:1 Multiplexer wird mit einer Frequenz FH/8 umgeschaltet, die ein Achtel der Zeilenfrequenz beträgt. Somit werden nach jeder vierten Zeile die Eingänge V des Multiplexers 2 umgeschaltet. Der Ausgang des 2:1 Multiplexers 2 und der Ausgang des Tiefpaßfilters 5, an welchem das Luminanzsignal Y anliegt, werden auf einen 2:1 Multiplexer 3 geführt, der mit einer Frequenz FV/2 umgeschaltet wird. Die Frequenz FV/2 ent¬ spricht der halben Bildfrequenz. Die Eingönge des Multiplexer.3 werden somit bei jedem Halbbildwechsel umge¬ schaltet . Die Umschaltfrequenzen FH/8, FV/2 der Multiplexer 2, 3 werden durch die Synchronabtrennschaltung und Taktzentrale 6 und durch Dividierer 7, 8 erzeugt. Der Ausgang des Multiplexers 3 führt auf einen Ana- - H-At the input IN of the -Schaltungsanordnung shown in Fig. 1, the "video signal present. It is separation circuit to the input of a color decoder 1, a low pass filter 5 and a Synchronab¬ and out clock center 6. At the output of the color decoder 1 are the chrominance signals U, V which are routed to a 2: 1 multiplexer 2. The 2: 1 multiplexer is switched at a frequency FH / 8 which is one eighth of the line frequency, so that after every fourth line the inputs V of the multiplexer 2 are switched of the 2: 1 multiplexer 2 and the output of the low-pass filter 5, to which the luminance signal Y is present, are routed to a 2: 1 multiplexer 3 which is switched with a frequency FV / 2. The frequency FV / 2 corresponds to half The inputs of the multiplexer.3 are thus switched over with every field change. The switching frequencies FH / 8, FV / 2 of the multiplexers 2, 3 are centralized by the synchronous separation circuit and clock e 6 and generated by dividers 7, 8. The output of the multiplexer 3 leads to an - H-
log/Digital-Wandler 4, an dessen Ausgang der digitale Daten¬ strom anliegt.log / digital converter 4, at the output of which the digital data stream is present.
Fig. 2a zeigt die Zeilenimpulse und Fig. 2b die aus ihnen von der Synchronabtrennschaltung und Taktzentrale 6 und dem Dividierer 8 erzeugten Umschaltfrequenz FH/8. Fig. 2c zeigt die Bildimpulse und Fig. 2d die aus ihnen von der Synchronab- trennschaltung und Taktzentrale 6 und dem Dividierer 7 er¬ zeugten Umschaltfrequenz FV/2.FIG. 2a shows the line pulses and FIG. 2b the switching frequency FH / 8 generated from them by the synchronous separation circuit and clock center 6 and the divider 8. 2c shows the image pulses and FIG. 2d the switching frequency FV / 2 generated from them by the synchronous separation circuit and clock center 6 and the divider 7.
Es ergibt sich folgende Abtaststruktur des Videosignals: Erfindungsgemäß werden von einem Vollbild die Halbbilαer mit Hilfe der Multiplexer 2, 3 z.B. so aufbereitet, daß im er¬ sten Halbbild das Luminanzsignal Y, und im anderen Halbbild die Farbdifferenzsignale U und V verwendet werden.The result is the following scanning structure of the video signal: According to the invention, the half-images are converted from a frame using the multiplexers 2, 3 e.g. processed in such a way that the luminance signal Y is used in the first field and the color difference signals U and V are used in the other field.
Es werden somit aus ankommenden Bildsignalen für das erste Halbbild nur das Luminanzsignal Y dem Digi- tal/Analog-Wandler 4 zugeführt. Das nächste Halbbild enthält nur die Information der zwei Farbdifferenzsignale U oder V, wobei in den ersten vier fortlaufenden Zeilen die erste Farbkomponente U des Halbbildes und in den nächsten vier fortlaufenden Zeilen die zweite Komponente V enthalten sind. Dieser Vorgang wiederholt sich für das gesamte zweite Halb¬ bild. Thus, only the luminance signal Y is fed to the digital / analog converter 4 from incoming image signals for the first field. The next field contains only the information of the two color difference signals U or V, the first four continuous lines containing the first color component U of the field and the next four continuous lines containing the second component V. This process is repeated for the entire second field.
Dem Eingang des Analog/Digital-Wandlers 4 werden dann die zwei Halbbilder mit nachstehendem Informationsgehalt zuge¬ führt:The two fields with the following information content are then fed to the input of the analog / digital converter 4:
ZeilenLines

Claims

P a t e n t a n s p r u c hP a t e n t a n s r u c h
Schaltungsanordnung zur Bearbeitung von Videokompo¬ nenten bestehend aus Chrominanz- und Luminanzsignal- anteilen, dadurch gekennzeichnet, daß die Chrominanzsignalanteile (U, V) einem mit einer Fre¬ quenz (FH/8) kleiner als die Zeilenfrequenz umschal¬ tenden ersten Multiplexer (1) zugeführt werden, und daß das LuminanzSignale (Y) und das Ausgangssignal des ersten Multiplexers (1) einem zweiten Multiplexer (2) zugeführt werden, welcher mit der halben Bildfrequenz umgeschaltet wird.Circuit arrangement for processing video components consisting of chrominance and luminance signal components, characterized in that the chrominance signal components (U, V) have a first multiplexer (1) which switches over with a frequency (FH / 8) less than the line frequency. are supplied, and that the luminance signals (Y) and the output signal of the first multiplexer (1) are fed to a second multiplexer (2) which is switched at half the frame rate.
Schaltungsanordnung nach Anspruch 1, dadurch gekenn¬ zeichnet, daß die Umschaltfrequenz des ersten Multiplexers (1) ein achtel der Zeilenfrequenz (FH/8) beträgt.Circuit arrangement according to Claim 1, characterized in that the switching frequency of the first multiplexer (1) is one eighth of the line frequency (FH / 8).
Schaltungsanordnung nach Anspruch 1, dadurch gekenn¬ zeichnet, daß das Ausgangssignal des zweiten Multiplexers (2) einem Digital/Analog-Wandler (4) zugeführt wird. Circuit arrangement according to Claim 1, characterized in that the output signal of the second multiplexer (2) is fed to a digital / analog converter (4).
EP88908859A 1987-09-30 1988-09-27 Circuitry for processing video components Pending EP0334932A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3733004 1987-09-30
DE3733004 1987-09-30

Publications (1)

Publication Number Publication Date
EP0334932A1 true EP0334932A1 (en) 1989-10-04

Family

ID=6337270

Family Applications (2)

Application Number Title Priority Date Filing Date
EP88908859A Pending EP0334932A1 (en) 1987-09-30 1988-09-27 Circuitry for processing video components
EP88115853A Expired - Lifetime EP0309976B1 (en) 1987-09-30 1988-09-27 Circuit arrangement for processing video components

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP88115853A Expired - Lifetime EP0309976B1 (en) 1987-09-30 1988-09-27 Circuit arrangement for processing video components

Country Status (10)

Country Link
US (1) US4942457A (en)
EP (2) EP0334932A1 (en)
JP (1) JP2783364B2 (en)
KR (1) KR0124469B1 (en)
AT (1) ATE83114T1 (en)
DE (1) DE3876358D1 (en)
ES (1) ES2036647T3 (en)
GR (1) GR3007206T3 (en)
SG (1) SG32093G (en)
WO (1) WO1989003155A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2664779B1 (en) * 1990-07-13 1993-06-11 Europ Rech Electr Lab PROCESS FOR PROCESSING A VIDEO SIGNAL.
DE4028424A1 (en) * 1990-09-07 1992-03-12 Philips Patentverwaltung CIRCUIT ARRANGEMENT FOR A / D CONVERSION OF THE COLOR INFORMATION OF TWO IMAGE SIGNALS
US5821919A (en) * 1994-04-29 1998-10-13 Intel Corporation Apparatus for table-driven conversion of pixels from YVU to RGB format
US6323913B1 (en) * 1997-01-10 2001-11-27 Infineon Technologies Ag Circuit configuration for color decoding and decimation for a video signal
US6868124B2 (en) * 2001-06-18 2005-03-15 Webtv Networks Inc. (Microsoft) Method and systems for compressing a video stream with minimal loss after subsampled decoding
TW200917855A (en) * 2007-10-05 2009-04-16 Novatek Microelectronics Corp Video controller and method for processing video signal

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2644706C3 (en) * 1976-10-04 1985-12-05 Robert Bosch Gmbh, 7000 Stuttgart System for the transmission or storage of a color television signal
DE3020920A1 (en) * 1980-06-03 1981-12-10 Robert Bosch Gmbh, 7000 Stuttgart Upgrading method for recorded video colour quality - transfers luminance and chrominance signals in separate consecutive frame periods
JPS5985196A (en) * 1982-11-06 1984-05-17 Victor Co Of Japan Ltd Digital processing unit of color video signal
NL194023C (en) * 1983-05-06 2001-04-03 Philips Electronics Nv Color television transmission or information storage system with time-division multiplex encoding and suitable information transmitter and receiver.
US4821086A (en) * 1987-10-28 1989-04-11 Rca Licensing Corporation TV receiver having in-memory switching signal

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8903155A1 *

Also Published As

Publication number Publication date
GR3007206T3 (en) 1993-07-30
ATE83114T1 (en) 1992-12-15
KR0124469B1 (en) 1997-12-01
EP0309976B1 (en) 1992-12-02
JP2783364B2 (en) 1998-08-06
SG32093G (en) 1993-07-09
WO1989003155A1 (en) 1989-04-06
JPH02501524A (en) 1990-05-24
DE3876358D1 (en) 1993-01-14
US4942457A (en) 1990-07-17
ES2036647T3 (en) 1993-06-01
EP0309976A1 (en) 1989-04-05
KR890702376A (en) 1989-12-23

Similar Documents

Publication Publication Date Title
DE2938349C2 (en) Circuit arrangement for a compatible increase in resolution in television systems
DE69432660T2 (en) DEVICE AND METHOD FOR ENCODING / DECODING DATA FOR SUBTITLES
DE2905816B2 (en) Solid-state color image pickup device
DE2935693C2 (en) Solid-state color imaging device
DE2824561A1 (en) LINE COUNTER CONVERTER
DE19713635B4 (en) Video camera device of the digital recording type
DE3435169A1 (en) DIGITAL CONVERTER SYSTEM FOR COLOR VIDEO SIGNALS
DE3431262A1 (en) TELEVISION WORKING WITH CONTINUOUS LINE SCAN
DE3103214C2 (en)
DE2837120A1 (en) METHOD AND ARRANGEMENT FOR PROCESSING PAL COLOR TELEVISION SIGNALS IN DIGITAL FORM
DE4423226C1 (en) Digital decoding composite video, blanking and synchronisation signals
EP0309976B1 (en) Circuit arrangement for processing video components
DE3103216C2 (en) Solid state television camera
EP0114693B1 (en) High resolution colour video signal transmission system
EP0246698A2 (en) Circuit arrangement for a television receiver provided with a teletext decoder
EP0114694B1 (en) Broadband colour video signal transmission system
DE4239800C2 (en) Digital decoder device
DE3202328A1 (en) "MULTIPLEX SYSTEM FOR DIGITAL VIDEO SIGNAL PROCESSING"
EP0309859B1 (en) Method for the recording of colour signals in a videorecorder
DE4233368C1 (en)
DE3642186A1 (en) VIDEO RECORDER WITH A SECOND VIDEO SIGNAL WAY
DE69718780T2 (en) METHOD AND DEVICE FOR DECODING COMPOSED VIDEO SIGNALS
EP0873650B1 (en) Circuit for color decoding and color decimation of a video signal
DE2908273C2 (en) System for the transmission of color television signals
DE3844118A1 (en) SIGNAL SEPARATOR TO SUBSAMPLE A DIGITAL BAS SIGNAL

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 19890513

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH DE FR GB IT LI LU NL SE

XX Miscellaneous (additional remarks)

Free format text: VERFAHREN ABGESCHLOSSEN INFOLGE VERBINDUNG MIT 88115853.9/0309976 (EUROPAEISCHE ANMELDENUMMER/VEROEFFENTLICHUNGSNUMMER) VOM 06.08.91.