EP0333249A1 - Circuit arrangement for storing a speech signal in a digital speech memory - Google Patents

Circuit arrangement for storing a speech signal in a digital speech memory Download PDF

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Publication number
EP0333249A1
EP0333249A1 EP89200543A EP89200543A EP0333249A1 EP 0333249 A1 EP0333249 A1 EP 0333249A1 EP 89200543 A EP89200543 A EP 89200543A EP 89200543 A EP89200543 A EP 89200543A EP 0333249 A1 EP0333249 A1 EP 0333249A1
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EP
European Patent Office
Prior art keywords
digital
signal
speech
memory
code
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EP89200543A
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German (de)
French (fr)
Inventor
Günter Dipl.-Ing. Bierlein (FH)
Helmut Dipl.-Ing. Salbaum (Fh)
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Philips Intellectual Property and Standards GmbH
Koninklijke Philips NV
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Philips Patentverwaltung GmbH
Philips Gloeilampenfabrieken NV
Koninklijke Philips Electronics NV
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Publication of EP0333249A1 publication Critical patent/EP0333249A1/en
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    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10L—SPEECH ANALYSIS TECHNIQUES OR SPEECH SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING TECHNIQUES; SPEECH OR AUDIO CODING OR DECODING
    • G10L19/00—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis

Definitions

  • the invention relates to a circuit arrangement for storing a voice signal in a digital voice memory and for reproducing the stored voice signal, with a control circuit which supplies the control commands and clock signals for the individual components of the arrangement, the voice signal being present in one of several predetermined codes.
  • Such circuit arrangements can e.g. be used for the automatic announcement in digital communication networks, in which the message traffic can take place in several predetermined codes.
  • a separate line (highway) is provided for each of these codes in such a network.
  • a description of such a network can be found e.g. in an article by W. Böhm and M. Maisel (Böhm, W. and Maisel, M .: PKI Technische Mitteilungen 1/85, pages 18 to 26, Philips Ltdunikation Industrie AG, Thurn-und-Taxis-Str. 10, D 8500 Nuremberg).
  • DE 29 50 066 A1 discloses a method for storing and reproducing an analog signal, but this is not suitable as the basis for an automatic announcement device for one of the above-mentioned communication networks.
  • the invention has for its object to provide a circuit arrangement of the type mentioned, which is suitable as an announcement device for one of the above-mentioned networks and announcements of significant length can be stored in the digital voice memory.
  • Announcement texts of appreciable length can therefore be stored in the digital voice memory according to the invention because the storage takes place in a preferred code.
  • a code is selected as the preferred code which is particularly well suited for compressed digital voice storage (cf. DE 29 50 066 A1).
  • the control circuit is relieved by the insertion of buffer memories. It only needs to be activated when the buffer tanks have reached a certain level.
  • the code conversion can be carried out in a cost-saving manner if commercially available digital-analog or analog-digital converters are used, which are available for all common digital codes and are characterized by low power loss and small space requirements.
  • the figure shows the basic circuit diagram of an arrangement according to the invention.
  • a control circuit SS is connected to a digital voice memory SP via a data and control bus DB. Clock lines and subordinate control lines are not shown in the figure, since their necessity is obvious to the person skilled in the art and their insertion does not pose any difficulties.
  • Two buffer memories P1 and P2 are also linked to the control circuit SS via the same bus DB. Via an address bus AB, addresses of those memory locations are transmitted from the control circuit SS to the address inputs of the digital voice memory SP which are to be written to or read from.
  • the digital voice memory SS is an EEPROM
  • the buffer memories P1 and P2 are FIFO memories
  • the control circuit is part of a message network mentioned at the beginning.
  • PCM 16 digital controlled delta modulation at 16 kHz; according to DCDM 32).
  • a further form of a speech signal is indicated in the figure, namely the acoustic one. Because of the systematic treatment, this form of the speech signal should also be understood as a code in the present case.
  • a microphone with amplifier then forms an input converter EW3, which converts acoustic signals into analog (electrical), and an amplifier with loudspeaker forms an output converter AW3, which converts analog (electrical) signals into acoustic.
  • Another EW1 input converter converts DCDM 32 signals into analog signals, while an EW2 converter converts PCM signals into analog signals.
  • the inputs of the converters EW1 and EW2 are connected to a signal output of the control circuit SS.
  • the outputs of the three input converters EW1, EW2 and EW3 are routed to the inputs of a multiplexer M1.
  • the multiplexer M1 is controlled by the control circuit SS so that the transcoded and now analog voice signal of the subscriber who wishes to save an announcement text is switched through to the output of the multiplexer M1 if the subscriber's signal is below one of the output signals of the three input converters located.
  • the output signal of the multiplexer M1 is now converted from the analog form into a DCDM 16 signal by a fourth input converter EW4.
  • the DCDM 16 code is the preferred digital code in which a voice signal is written into the digital voice memory SP; this code is also among the codes that a participant of the transmission system can choose for the transmission of its signal. Therefore, the aforementioned signal output of the control circuit SS and the output of the converter EW4 are routed to a second multiplexer M2; in turn, the control circuit SS controls the multiplexer M2 so that the desired signal is present at its output.
  • a serial-parallel converter W1 the DCDM-16 signal is then fed to a FIFO memory P1 (F IRST I N F IRST O UT) and written therefrom, also controlled by the control circuit SS, in the digital voice memory SP.
  • the signal When reading out the announcement texts from the digital voice memory SP, the signal is first buffered in a second FIFO memory P2 and then passes through a parallel-series converter W2. Then it becomes - in the DCDM 16 code - a signal input of the control circuit SS as well as the input of an output converter AW4, which converts the DCDM 16 signal into an analog signal.
  • the output of converter AW4 is connected to the inputs of three further converters, namely the already mentioned electro-acoustic converter AW3, a converter AW2, which converts its analog input signal into a PCM signal, and a converter AW1, which converts its (analog) input signal converts to a DCDM 32 signal.
  • the outputs of the two converters AW1 and AW2 mentioned last are led to two further signal inputs of the control circuit SS.
  • control circuit SS With the help of the control circuit SS, it is ensured that every subscriber, regardless of the code of his voice signals, can get knowledge of the announcement text stored in the digital voice memory SP at any time.

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  • Engineering & Computer Science (AREA)
  • Computational Linguistics (AREA)
  • Signal Processing (AREA)
  • Health & Medical Sciences (AREA)
  • Audiology, Speech & Language Pathology (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Multimedia (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
  • Analogue/Digital Conversion (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

The circuit arrangement described for storing a speech signal in a digital speech memory (SP) and for reproducing the stored signal contains inter alia a control circuit (SS). The control circuit supplies control commands and clock signals for the individual modules of the arrangement. The speech signal to be stored is present in one of a plurality of predefined codes. <??>In order to be able to store speech signals of considerable length it is provided that the speech signal be read into the digital speech memory (SS) in a preferred digital code. For this purpose input converters (EW1, EW2, EW3, EW4) are used which convert the speech signal to be stored from its existing code into the preferred digital code if it is not already in this code. Controlled by the control circuit (SS), a multiplexing device (M1, M2) passes the converted speech signal on to the input of the digital speech memory (SP). Output converters (AW1, AW2, AW3, AW4) convert the speech signal read out from the digital speech memory (SP) into each of the predefined codes. <IMAGE>

Description

Die Erfindung betrifft eine Schaltungsanordnung zur Spei­cherung eines Sprachsignals in einem digitalen Sprach­speicher und zur Wiedergabe des gespeicherten Sprachsig­nals, mit einer Steuerschaltung, die die Steuerbefehle und Taktsignale für die einzelnen Bausteine der Anordnung liefert, wobei das Sprachsignal in einem von mehreren vorbestimmten Codes vorliegt.The invention relates to a circuit arrangement for storing a voice signal in a digital voice memory and for reproducing the stored voice signal, with a control circuit which supplies the control commands and clock signals for the individual components of the arrangement, the voice signal being present in one of several predetermined codes.

Derartige Schaltungsanordnungen können z.B. für die auto­matische Ansage in digitalen Nachrichtennetzen verwendet werden, in denen der Nachrichtenverkehr in mehreren vor­bestimmten Codes stattfinden kann. Für jeden dieser Codes ist in einem solchen Netz eine gesonderte Leitung (High­way) vorgesehen. Eine Beschreibung eines derartigen Ne­tzes findet man z.B. in einem Artikel von W. Böhm und M. Maisel (Böhm, W. und Maisel, M.: PKI Technische Mittei­lungen 1/85, Seite 18 bis 26 Philips Kommunikations In­dustrie AG, Thurn-und-Taxis-Str. 10, D 8500 Nürnberg).Such circuit arrangements can e.g. be used for the automatic announcement in digital communication networks, in which the message traffic can take place in several predetermined codes. A separate line (highway) is provided for each of these codes in such a network. A description of such a network can be found e.g. in an article by W. Böhm and M. Maisel (Böhm, W. and Maisel, M .: PKI Technische Mitteilungen 1/85, pages 18 to 26, Philips Kommunikation Industrie AG, Thurn-und-Taxis-Str. 10, D 8500 Nuremberg).

Aus der DE 29 50 066 A1 ist ein Verfahren zur Speicherung und Wiedergabe eines analogen Signals bekannt, das sich jedoch nicht als Grundlage einer automatischen Ansageein­richtung für eines der oben genannten Nachrichtennetze eignet. Der Erfindung liegt die Aufgabe zugrunde, eine Schaltungsanordnung der eingangs genannten Art anzugeben, die sich als Ansageeinrichtung für eines der oben erwähn­ten Netze eignet und in deren digitalem Sprachspeicher Ansagen nennenswerter Länge gespeichert werden können.DE 29 50 066 A1 discloses a method for storing and reproducing an analog signal, but this is not suitable as the basis for an automatic announcement device for one of the above-mentioned communication networks. The invention has for its object to provide a circuit arrangement of the type mentioned, which is suitable as an announcement device for one of the above-mentioned networks and announcements of significant length can be stored in the digital voice memory.

Diese Aufgabe wird gelöst durch:

  • 1.1. einen bevorzugten Digitalcode, in dem das Sprachsig­nal in den digitalen Sprachspeicher eingelesen wird,
  • 1.2. Eingangswandler, die das zu speichernde Sprachsignal aus einem vorliegenden Code in den bevorzugten Digital­code umwandeln, falls es nicht schon in diesem Code vor­liegt,
  • 1.3. eine Multiplexeinrichtung, durch die, gesteuert von der Steuerschaltung, das gewandelte Sprachsignal an den Eingang des digitalen Sprachspeichers weitergeleitet wird,
  • 1.4. Ausgangswandler, die das aus dem digitalen Sprach­speicher ausgelesene Sprachsignal in jeden der vorbe­stimmten Codes wandeln.
This task is solved by:
  • 1.1. a preferred digital code in which the voice signal is read into the digital voice memory,
  • 1.2. Input converters which convert the speech signal to be stored from an existing code into the preferred digital code, if it is not already present in this code,
  • 1.3. a multiplexing device through which, controlled by the control circuit, the converted voice signal is forwarded to the input of the digital voice memory,
  • 1.4. Output converters that convert the voice signal read from the digital voice memory into each of the predetermined codes.

Ansagetexte nennenswerter Länge können erfindungsgemäß deshalb in dem digitalen Sprachspeicher gespeichert wer­den, weil die Speicherung in einem bevorzugten Code er­folgt. Als bevorzugter Code wird ein Code gewählt, der sich besonders gut für die komprimierte digitale Sprach­speicherung eignet (vgl. hierzu die DE 29 50 066 A1).Announcement texts of appreciable length can therefore be stored in the digital voice memory according to the invention because the storage takes place in a preferred code. A code is selected as the preferred code which is particularly well suited for compressed digital voice storage (cf. DE 29 50 066 A1).

Durch die Einfügung von Pufferspeichern wird die Steuer­schaltung entlastet. Sie braucht nur dann in Aktion zu treten, wenn die Pufferspeicher einen bestimmten Füll­stand erreicht haben. Die Codewandlung läßt sich kosten­sparend durchführen, wenn handelsübliche Digital-Analog- bzw. Analog-Digital-Wandler eingesetzt werden, die für alle gängigen Digitalcodes zu haben sind und sich durch geringe Verlustleistung und geringen Platzbedarf aus­zeichnen.The control circuit is relieved by the insertion of buffer memories. It only needs to be activated when the buffer tanks have reached a certain level. The code conversion can be carried out in a cost-saving manner if commercially available digital-analog or analog-digital converters are used, which are available for all common digital codes and are characterized by low power loss and small space requirements.

Anhand eines Ausführungsbeispieles und der Figur soll die Erfindung näher erläutert werden.The invention will be explained in more detail using an exemplary embodiment and the figure.

Die Figur zeigt das Prinzipschaltbild einer erfindungsge­mäßen Anordnung.The figure shows the basic circuit diagram of an arrangement according to the invention.

Entsprechend der Schaltung nach der Figur ist eine Steu­erschaltung SS über einen Daten- und Steuerbus DB mit ei­nem digitalen Sprachspeicher SP verbunden. Taktleitungen und untergeordnete Steuerleitungen sind in der Figur nicht eingetragen, da deren Notwendigkeit für den Fach­mann offensichtlich ist und deren Einfügung keinerlei Schwierigkeiten bereitet. Über den gleichen Bus DB sind auch zwei Pufferspeicher P1 und P2 mit der Steuerschal­tung SS verknüpft. Über einen Adressenbus AB werden Adressen derjenigen Speicherstellen von der Steuerschal­tung SS an die Adreßeingänge des digitalen Sprachspei­chers SP übertragen, die beschrieben oder gelesen werden sollen.According to the circuit according to the figure, a control circuit SS is connected to a digital voice memory SP via a data and control bus DB. Clock lines and subordinate control lines are not shown in the figure, since their necessity is obvious to the person skilled in the art and their insertion does not pose any difficulties. Two buffer memories P1 and P2 are also linked to the control circuit SS via the same bus DB. Via an address bus AB, addresses of those memory locations are transmitted from the control circuit SS to the address inputs of the digital voice memory SP which are to be written to or read from.

Im Beispiel ist der digitale Sprachspeicher SS ein EEPROM, die Pufferspeicher P1 und P2 sind FIFO-Speicher und die Steuerschaltung ist Bestandteil eines eingangs erwähnten Nachrichtennetzes. In diesem Nachrichtennetz gibt es drei Highways, einen für PCM-Signale, einen für DCDM 16-Signale und einen für DCDM 32-Signale (PCM: Puls-Code-Modulation. DCDM 16: Digital-Controlled-Delta-­Modulation mit 16 kHz; entsprechend DCDM 32).In the example, the digital voice memory SS is an EEPROM, the buffer memories P1 and P2 are FIFO memories and the control circuit is part of a message network mentioned at the beginning. There are three highways in this communications network, one for PCM signals, one for DCDM 16 signals and one for DCDM 32 signals (PCM: pulse code modulation. DCDM 16: digital controlled delta modulation at 16 kHz; according to DCDM 32).

In der Figur ist noch eine weitere Form eines Sprachsig­nals angedeutet, nämlich die akustische. Der systemati­schen Behandlung wegen soll im vorliegenden Fall auch diese Form des Sprachsignals als Code verstanden werden. In diesem Sinne bildet dann ein Mikrophon mit Verstärker einen Eingangswandler EW3, der akustische Signale in ana­loge (elektrische) wandelt, und ein Verstärker mit Laut­sprecher einen Ausgangswandler AW3, der analoge (elektri­sche) Signale in akustische wandelt. Ein weiterer Ein­gangswandler EW1 wandelt DCDM 32-Signale in analoge Sig­nale, während ein Wandler EW2 PCM-Signale in analoge um­wandelt. Die Eingänge der Wandler EW1 und EW2 sind mit einem Signalausgang der Steuerschaltung SS verbunden.A further form of a speech signal is indicated in the figure, namely the acoustic one. Because of the systematic treatment, this form of the speech signal should also be understood as a code in the present case. In this sense, a microphone with amplifier then forms an input converter EW3, which converts acoustic signals into analog (electrical), and an amplifier with loudspeaker forms an output converter AW3, which converts analog (electrical) signals into acoustic. Another EW1 input converter converts DCDM 32 signals into analog signals, while an EW2 converter converts PCM signals into analog signals. The inputs of the converters EW1 and EW2 are connected to a signal output of the control circuit SS.

Die Ausgänge der drei Eingangswandler EW1, EW2 und EW3 sind an die Eingänge eines Multiplexers M1 geführt. Der Multiplexer M1 wird von der Steuerschaltung SS so gesteu­ert, daß das umcodierte und nun analog vorliegende Sprachsignal desjenigen Teilnehmers, der einen Ansagetext abzuspeichern wünscht, an den Ausgang des Multiplexers M1 durchgeschaltet wird, falls sich das Signal des Teilneh­mers unter einem der Ausgangssignale der drei Eingangs­wandler befindet.The outputs of the three input converters EW1, EW2 and EW3 are routed to the inputs of a multiplexer M1. The multiplexer M1 is controlled by the control circuit SS so that the transcoded and now analog voice signal of the subscriber who wishes to save an announcement text is switched through to the output of the multiplexer M1 if the subscriber's signal is below one of the output signals of the three input converters located.

Das Ausgangssignal des Multiplexers M1 wird jetzt durch einen vierten Eingangswandler EW4 von der analogen Form in ein DCDM 16-Signal gewandelt. Der DCDM 16-Code ist der bevorzugte Digitalcode, in dem ein Sprachsignal in den digitalen Sprachspeicher SP eingeschrieben wird; dieser Code befindet sich auch unter den Codes, die ein Teilneh­mer des Übertragungssystems für die Übertragung seines Signals wählen kann. Deshalb ist der erwähnte Signalaus­gang der Steuerschaltung SS sowie der Ausgang des Wand­lers EW4 an einen zweiten Multiplexer M2 geführt; wiede­rum steuert die Steuerschaltung SS den Multiplexer M2 so, daß das gewünschte Signal an seinem Ausgang anliegt. Über einen Serien-Parallel-Wandler W1 wird das DCDM 16-Signal nun einem FIFO-Speicher P1 (FIRST IN FIRST OUT) zugeführt und von diesem, ebenfalls gesteuert von der Steuerschal­tung SS, in den digitalen Sprachspeicher SP eingeschrie­ben.The output signal of the multiplexer M1 is now converted from the analog form into a DCDM 16 signal by a fourth input converter EW4. The DCDM 16 code is the preferred digital code in which a voice signal is written into the digital voice memory SP; this code is also among the codes that a participant of the transmission system can choose for the transmission of its signal. Therefore, the aforementioned signal output of the control circuit SS and the output of the converter EW4 are routed to a second multiplexer M2; in turn, the control circuit SS controls the multiplexer M2 so that the desired signal is present at its output. A serial-parallel converter W1 the DCDM-16 signal is then fed to a FIFO memory P1 (F IRST I N F IRST O UT) and written therefrom, also controlled by the control circuit SS, in the digital voice memory SP.

Beim Auslesen der Ansagetexte aus dem digitalen Sprach­speicher SP wird das Signal zunächst in einen zweiten FI­FO-Speicher P2 zwischengespeichert und durchläuft dann einen Parallel-Serien-Wandler W2. Danach wird es - im DCDM 16-Code - einem Signaleingang der Steuerschaltung SS sowie dem Eingang eines Ausgangswandlers AW4 zugeführt, der das DCDM 16-Signal in ein analoges Signal umwandelt. Der Ausgang des Wandlers AW4 ist mit den Eingängen dreier weiterer Wandler verbunden, nämlich dem schon erwähnten elektro-akustischen Wandler AW3, einem Wandler AW2, der sein analoges Eingangssignal in ein PCM-Signal umwandelt, und einem Wandler AW1, der sein (analoges) Eingangssignal in ein DCDM 32-Signal wandelt. Die Ausgänge der beiden zuletzt erwähnten Wandler AW1 und AW2 sind an zwei weite­re Signaleingänge der Steuerschaltung SS geführt.When reading out the announcement texts from the digital voice memory SP, the signal is first buffered in a second FIFO memory P2 and then passes through a parallel-series converter W2. Then it becomes - in the DCDM 16 code - a signal input of the control circuit SS as well as the input of an output converter AW4, which converts the DCDM 16 signal into an analog signal. The output of converter AW4 is connected to the inputs of three further converters, namely the already mentioned electro-acoustic converter AW3, a converter AW2, which converts its analog input signal into a PCM signal, and a converter AW1, which converts its (analog) input signal converts to a DCDM 32 signal. The outputs of the two converters AW1 and AW2 mentioned last are led to two further signal inputs of the control circuit SS.

So ist mit Hilfe der Steuerschaltung SS dafür gesorgt, daß jeder Teilnehmer, unabhängig vom Code seiner Sprach­signale, jederzeit Kenntnis von dem im digitalen Sprach­speicher SP gespeicherten Ansagetext bekommen kann.With the help of the control circuit SS, it is ensured that every subscriber, regardless of the code of his voice signals, can get knowledge of the announcement text stored in the digital voice memory SP at any time.

Claims (3)

1. Schaltungsanordnung zur Speicherung eines Sprachsig­nals in einem digitalen Sprachspeicher (SP) und zur Wie­dergabe des gespeicherten Signals, mit einer Steuerschal­tung (SS), die Steuerbefehle und Taktsignale für die ein­zelnen Bausteine der Anordnung liefert, wobei das Sprach­signal in einem von mehreren vorbestimmten Codes vor­liegt,
gekennzeichnet durch
1.1. einen bevorzugten Digitalcode, in dem das Sprachsig­nal in den digitalen Sprachspeicher (SS) eingelesen wird, 1.2. Eingangswandler (EW1, EW2, EW3, EW4), die das zu speichernde Sprachsignal aus seinem vorliegenden Code in den bevorzugten Digitalcode umwandeln, falls es nicht schon in diesem Code vorliegt, 1.3. eine Multiplexeinrichtung (M1, M2), durch die, ge­steuert von der Steuerschaltung (SS), das gewandelte Sprachsignal an den Eingang des Sprachspeichers (SP) wei­tergeleitet wird, 1.4. Ausgangswandler (AW1, AW2, AW3, AW4), die das aus dem digitalen Sprachspeicher (SP) ausgelesene Sprachsig­nal in jeden der vorbestimmten Codes wandeln. 1. Circuit arrangement for storing a voice signal in a digital voice memory (SP) and for reproducing the stored signal, with a control circuit (SS), which delivers control commands and clock signals for the individual components of the arrangement, the voice signal being in one of several predetermined codes ,
marked by
1.1. a preferred digital code in which the voice signal is read into the digital voice memory (SS), 1.2. Input converters (EW1, EW2, EW3, EW4), which convert the speech signal to be stored from its code into the preferred digital code, if it is not already in this code, 1.3. a multiplexing device (M1, M2) through which, controlled by the control circuit (SS), the converted speech signal is forwarded to the input of the speech memory (SP), 1.4. Output converters (AW1, AW2, AW3, AW4) which convert the speech signal read from the digital speech memory (SP) into each of the predetermined codes. 2. Schaltungsanordnung nach Anspruch 1,
dadurch gekennzeichnet,
daß dem Eingang des digitalen Sprachspeichers (SP) ein erster Pufferspeicher (P1) vorgeschaltet und seinem Aus­gang ein zweiter Pufferspeicher (P2) nachgeschaltet ist.2. Circuit arrangement according to claim 1,
characterized by
that the input of the digital voice memory (SP) is preceded by a first buffer memory (P1) and its output is followed by a second buffer memory (P2). 3. Schaltungsanordnung nach Anspruch 1 oder 2,
dadurch gekennzeichnet,
daß als Wandler (EW1...EW4, AW1....AW4) Digital-Analog- bzw. Analog-Digital-Wandler und gegebenenfalls deren Ket­tenschaltung verwendet werden.3. Circuit arrangement according to claim 1 or 2,
characterized by
that as converters (EW1 ... EW4, AW1 .... AW4) digital-to-analog or analog-to-digital converters and possibly their chain connection are used.
EP89200543A 1988-03-12 1989-03-06 Circuit arrangement for storing a speech signal in a digital speech memory Withdrawn EP0333249A1 (en)

Applications Claiming Priority (2)

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DE3808298A DE3808298A1 (en) 1988-03-12 1988-03-12 CIRCUIT ARRANGEMENT FOR STORING A VOICE SIGNAL IN A DIGITAL VOICE MEMORY
DE3808298 1988-03-12

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69835048T2 (en) * 1997-03-11 2007-05-03 Koninklijke Philips Electronics N.V. Telephone device with a digital processing circuit for voice signals and method performed in this device
US6047255A (en) * 1997-12-04 2000-04-04 Nortel Networks Corporation Method and system for producing speech signals

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3846763A (en) * 1974-01-04 1974-11-05 Honeywell Inf Systems Method and apparatus for automatic selection of translators in a data processing system
EP0185445A2 (en) * 1984-12-17 1986-06-25 VoiceTek Inc Method and apparatus for controlling digital voice recording and playback over telephone lines and adapted for use with any host computer

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2826870A1 (en) * 1978-06-19 1980-01-03 Siemens Ag SEMICONDUCTOR DEVICE FOR REPRODUCTION OF ACOUSTIC SIGNALS
US4330689A (en) * 1980-01-28 1982-05-18 The United States Of America As Represented By The Secretary Of The Navy Multirate digital voice communication processor
US4718087A (en) * 1984-05-11 1988-01-05 Texas Instruments Incorporated Method and system for encoding digital speech information
US4622680A (en) * 1984-10-17 1986-11-11 General Electric Company Hybrid subband coder/decoder method and apparatus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3846763A (en) * 1974-01-04 1974-11-05 Honeywell Inf Systems Method and apparatus for automatic selection of translators in a data processing system
EP0185445A2 (en) * 1984-12-17 1986-06-25 VoiceTek Inc Method and apparatus for controlling digital voice recording and playback over telephone lines and adapted for use with any host computer

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
N.E.C. RESEARCH AND DEVELOPMENT, SPECIAL ISSUE ON C&C OFFICE SYSTEM, 1985, Seiten 225-235, Tokyo, JP; K. FUJITA et al.: "NEAX2400 information management system (IMS)" *

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US4964168A (en) 1990-10-16
JPH01294298A (en) 1989-11-28
DE3808298A1 (en) 1989-09-21

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