EP0329528B2 - Method of controlling a matrix display screen, and device for carrying out this method - Google Patents

Description

The present invention relates to a method for controlling a matrix display screen making it possible to adjust its contrast in the case of a liquid crystal screen and its brightness in the case of a fluorescent microtip screen and a device for the implementation of this process.

The invention applies in particular to the production of liquid crystal displays of the multiplexed or non-multiplexed type or else of fluorescent microtip screens (denoted EFM in the following description), allowing the viewing of fixed or animated images. .

Various types of control methods are known for matrix display screens.

The matrix display screens include a display cell provided with crossed row and column conductors, a screen pixel being associated with each crossing of these conductors.

A description of an EFM is found in French patent application no. 87 15432 of November 6, 1987 (FR-A-2 623 013 corresponding to EP-A-0 316 214 published on 05/17/89). In an EFM the lines correspond to the grids and the columns to the cathodes.

For liquid crystal displays, the display material is contained in the display cell. Liquid crystal displays can be ordered multiplexed or non-multiplexed.

In more detail, in the case of a multiplexed display screen, the row and column conductors are constituted by row and column electrodes disposed respectively on the internal walls of the cell, a pixel being defined by the area of covering of a row electrode and a column electrode.

In the case of a non-multiplexed type display screen, the row and column conductors consist of address lines and control columns which are for example arranged on one of the walls of the cell and connected by the through transistors at point electrodes, a continuous electrode being arranged on the other wall of the cell. According to another example of this type of screen, the address lines and the control columns can be arranged respectively on the internal walls of the cell, the lines being connected by means of transistors to point electrodes and the columns being connected to columns of electrodes. In the latter two cases, a pixel is defined by the area of overlap of a point electrode with the continuous electrode or with a column electrode.

Address signals are sent to the various line conductors and control signals to the column conductors. An example, purely illustrative and in no way limiting, is given in FIG. 1, describing such signals in the case of a matrix liquid crystal display screen controlled by the technique known as direct multiplexing.

For reasons of simplicity, in no way detrimental to the description, in this example, we limit ourselves to a screen having nine pixels, that is to say three row conductors L1, L2, L3, and three column conductors C1, C2, C3.

The voltages VI applied to the line conductors are periodic, of period T known as frame time or scanning time. For each line conductor, the voltage VI is equal to a voltage Vmax during a time called line selection time Ts, it is zero for example, outside this time Ts over the rest of the time T. Each line is thus carried successively for a time Ts at the value Vmax. FIG. 1A shows a cycle of addressing the line conductors. FIG. 1B describes an example of a sequence of control voltages Vc applied to the column conductors. Depending on the reason to display the voltages applied to the column conductors will be positive or negative.

The values of the voltages applied to the line conductors and to the column conductors depend on the nature of the display used.

When the voltage applied to a row conductor is in phase with the voltage applied to a column conductor, the pixel corresponding to their crossing is off (black, for example). If the two voltages are in phase opposition, the pixel considered is lit (white for example).

When the line L1 is selected in other words when it is brought to Vmax during Ts, the voltage on the column C1 is positive, in the example proposed. The two line and column voltages are in phase and the pixel corresponding to the crossing of the line conductor L1 with the column conductor C1 is black. When line L2 is selected, the voltage on column C1 is negative, in the example proposed. The two line and column voltages are in phase opposition and the pixel corresponding to the crossing of the line conductor L2 with the column conductor C1 is white. The state of each pixel is deduced identically.

FIG. 1C gives the display of the screen for the row and column voltages proposed in FIGS. 1A and 1B. The pixels noted N are black, those noted B are white.

For the display of a given item of information, at each corresponding period T, the line and column voltages have their polarity reversed so as to apply to the display material only signals of zero mean values.

In the case of a liquid crystal screen of the non-multiplexed type or of an EFM, the selection signals of the line conductors are the same as those represented in FIG. 1A but they do not undergo inversion of polarity. On the other hand, the signals applied to the column conductors are indifferently of positive or negative polarity, their amplitude depends solely on the voltage necessary for the electrooptical effect used.

In all cases, the line selection time Ts depends on the number of line conductors to be selected by the formula Ts = T / M where M is the total number of line conductors and T is the frame time. It is understood that the more M increases the shorter the selection time Ts.

The multiplexing rate TM is defined as being the ratio between the frame time T and the time for selecting a line conductor Ts. $$\text{TM = T / Ts}$$

It can be seen that for the known screens TM = M.

When the number of line conductors increases, the multiplexing rate follows this growth and the time Ts decreases resulting in a decrease in the contrast of a liquid crystal screen and in the brightness of an EFM.

The number of lines commonly used in liquid crystal display matrix screens is about one hundred. It is therefore much lower than the number of line signals available in video, which is equal, for example, to around two hundred and eighty at the output of a video recorder.

The invention provides a method of controlling a matrix display screen which allows the use of a large number of lines without loss of contrast or of brightness or alternatively, with a number of lines equal to that of the screens of the prior art, an improvement in contrast or brightness.

This improvement cannot be interpreted independently of phenomena related to the physiology of the eye; it corresponds to an average effect of the information contained on the screen over a frame time.

In this method, the selection times of the adjacent line conductors may overlap. The adjustment of the overlap makes it possible to use a screen either in graphic or text mode, or in video mode for viewing an animated image. In the first case, the recovery must be zero or weak; contrast or brightness is limited, but the effective resolution is then maximum. In the second use, the high number of lines avoids the mosaic appearance on the screen, unpleasant to the eye. The overlap can reach up to half the selection times of two adjacent lines for high contrast or brightness. The effective resolution is then reduced, but this is not a problem for an animated image (natural image).

By this method, if we refer to the example relating to the prior art, the multiplexing rate TM is now less than or equal to the number of line conductors. At equal multiplexing rate, it is therefore possible to increase the number of line conductors and thereby improve the contrast or the brightness of the screen.

More specifically, the invention relates to a control method according to claim 1.

According to another characteristic of this control method, the duration during which the addressing signals VI have a value Vmax is adjustable.

The invention also relates to a device according to claim 3.

• un circuit d'adressage A1 relié par des connexions aux conducteurs lignes Li, i étant un entier impair tel que 1≦i≦M, M étant le nombre de conducteurs lignes,
• un circuit d'adressage A2 relié par des connexions aux conducteurs lignes Lp, p étant un entier pair, tel que 2≦p≦M.

This device, for implementing the method for controlling a display screen, comprises:

• an addressing circuit A1 connected by connections to the line conductors Li, i being an odd integer such that 1 ≦ i ≦ M, M being the number of line conductors,
• an addressing circuit A2 connected by connections to the line conductors Lp, p being an even integer, such as 2 ≦ p ≦ M.

• un circuit réalisant une fonction horloge délivrant des signaux sur une sortie Sp1,
• un circuit réalisant une fonction de verrouillage relié par une entrée Ep1 à la sortie Sp1 du circuit réalisant la fonction horloge et délivrant des signaux sur une sortie Sp4,
• un circuit de commande relié par une entrée Ep4 à la sortie Sp4 du circuit réalisant une fonction de verrouillage et par une entrée Ep3 à la sortie Sp1 du circuit réalisant une fonction horloge et délivrant des tensions VI sur les conducteurs lignes Lp qui lui sont connectés.

The addressing circuit A2 includes:

• a circuit performing a clock function delivering signals on an output Sp1,
• a circuit performing a locking function connected by an input Ep1 to the output Sp1 of the circuit performing the clock function and delivering signals to an output Sp4,
• a control circuit connected by an input Ep4 to the output Sp4 of the circuit performing a locking function and by an input Ep3 to the output Sp1 of the circuit performing a clock function and delivering voltages VI on the line conductors Lp which are connected to it.

• un circuit réalisant une fonction horloge délivrant des signaux sur une sortie Si1,
• un circuit réalisant une fonction de verrouillage relié par une entrée Ei1 à la sortie Si1 du circuit réalisant la fonction horloge et délivrant des signaux sur une sortie Si4,
• un circuit de commande relié par une entrée Ei4 à la sortie Si4 du circuit réalisant une fonction de verrouillage et par une entrée Ei3 à la sortie Si1 du circuit réalisant une fonction horloge et délivrant des tensions VI sur les conducteurs lignes Li qui lui sont connectés.

The addressing circuit A1 has a structure identical to the addressing circuit A2. The addressing circuit A1 includes:

• a circuit performing a clock function delivering signals on an output Si1,
• a circuit performing a locking function connected by an input Ei1 to the output Si1 of the circuit performing the clock function and delivering signals on an output Si4,
• a control circuit connected by an input Ei4 to the output Si4 of the circuit performing a locking function and by an input Ei3 to the output Si1 of the circuit performing a clock function and delivering voltages VI on the Li line conductors connected to it.

The circuit performing a locking function in the addressing circuit A2 is also connected by an input Ep2 to an output Si1 of the circuit performing a clock function in the addressing circuit A1, the circuit performing a locking function in the circuit d addressing A1 also being connected by an input Ei2 to the output Sp1 of the circuit performing a clock function in the addressing circuit A2.

The control circuits of circuits A1 and A2 are for example respectively of the shift register type provided with a locking function.

• soit collectivement à un potentiel de référence correspondant au potentiel de verrouillage ;
• soit sélectivement en fonction des niveaux logiques présents respectivement dans les registres à décalage au potentiel de référence (état 0) ou au potentiel de sélection ligne (état 1).

In this way, these control circuits carry the line conductors which are connected to them according to the state of their locking function:

• either collectively at a reference potential corresponding to the locking potential;
• either selectively as a function of the logic levels present respectively in the shift registers at the reference potential (state 0) or at the line selection potential (state 1).

The locking function is called in English terminology "enable" function.

• les figures 1A à 1C, déjà décrites et relatives à l'art antérieur, illustrent un procédé de commande classique d'un écran d'affichage matriciel ;
• la figure 2 représente une séquence de commande selon l'invention de trois conducteurs lignes dans le cas d'un recouvrement fort entre les temps de sélection ;
• la figure 3 représente un dispositif permettant de mettre en oeuvre le procédé selon l'invention ;
• la figure 4 représente les diagrammes temporels des signaux délivrés par les différents éléments d'un dispositif selon l'invention ;
• la figure 5 représente un exemple de réalisation d'une fonction "enable" ;
• la figure 6 représente un exemple de diagrammes temporels des signaux délivrés par les différents éléments permettant de réaliser les fonctions "enable".

Other characteristics and advantages of the invention will emerge more clearly from the description which follows, given purely by way of illustration and in no way limiting, with reference to the appended figures, in which:

• FIGS. 1A to 1C, already described and relating to the prior art, illustrate a conventional control method for a matrix display screen;
• FIG. 2 represents a control sequence according to the invention of three line conductors in the case of a strong overlap between the selection times;
• FIG. 3 represents a device making it possible to implement the method according to the invention;
• FIG. 4 represents the time diagrams of the signals delivered by the various elements of a device according to the invention;
• FIG. 5 represents an exemplary embodiment of an "enable"function;
• FIG. 6 represents an example of time diagrams of the signals delivered by the various elements making it possible to carry out the "enable" functions.

FIG. 2 represents a control sequence according to the invention of three line conductors, L1, L2 and L3 in the case of a strong overlap between the selection times. This limiting case, where the selection time Ts' is equal to twice the selection time Ts corresponding to zero overlap, illustrates the method according to the invention well. This example, restricted for reasons of simplicity of description to three line conductors, in no way limits the number of line conductors that it is possible to select by this method. Furthermore, this example is valid for both a multiplexed or non-multiplexed type liquid crystal screen and for an EFM.

The voltage VI applied to a line conductor is equal, during the selection time Ts', to the voltage Vmax and is less than Vmax (it is for example zero) during the rest of the frame time.

The total writing time of a frame is equal to: (MxTs) + (Ts'-Ts).

M is the total number of lines; Ts is the selection time of a line conductor corresponding to an overlap between the selection times of two line conductors zero; Ts' is the effective selection time of the line conductors. This writing time is greater than or equal to a frame time T of the time Ts'-Ts, the time (Ts'-Ts) is taken over the time during which the video signal carries no information, this time is commonly called frame return time.

The lengthening and overlapping of the selection times of the line conductors leads to an averaging of the light signal from one line conductor to the other. The average brightness of the screen is improved and the contours of the displayed image are softened.

FIG. 3 represents a device making it possible to implement the method according to the invention. The device comprises an addressing circuit A1 connected by connections to the line conductors Li, i being an odd integer such as 1 ≦ i ≦ M and an addressing circuit A2 connected by connections to the line conductors Lp, p being an integer even such that 2 ≦ p ≦ M. The addressing circuit A2 comprises a circuit 10 performing a clock function delivering signals to an output Sp1, a circuit 12 performing an "enable" function connected by an input Ep1 to the output Sp1 of the clock function 10 and delivering signals to a Sp4 output. An "enable" function has the effect of locking the output of the circuit to which it is connected to a reference potential (or locking potential), the reference potential is for example zero. It is through it that the line conductor selection time is adjusted. A description of an embodiment of such a function, applied to the device according to the invention, is given below. The addressing circuit A2 also includes a control circuit 14 formed by a shift register endowed with the "enable" pair function connected by an input Ep4 to the output Sp4 of the circuit performing the "enable" function 12 and by an input Ep3 at the output Sp1 of the circuit performing the clock function 10 and delivering voltages VI on the line conductors Lp of even number which are connected to it.

The addressing circuit A1 has a structure identical to the addressing circuit A2. Its connections are assigned the index "i" (odd) instead of the index "p" (even) of the connections of circuit A2, the circuit performing the odd clock function 11 having as counterpart pair the circuit performing the clock function 10, the circuit performing the odd "enable" function and the control circuit of the addressing circuit A1 bearing the references 13 and 15 respectively and having as counterparts the circuits 12 and 14. The control circuit 15 is formed by a shift register with the odd "enable" function.

In addition, the circuit performing the "enable" function 12 is also connected by an input Ep2 to the output Si3 of the circuit performing the clock function 11. Likewise, the circuit performing the "enable" function 13 is connected by an input Ei2 to the output Sp3 of the circuit performing the even clock function 10.

The time diagrams of the signals delivered on the different outputs of the elements constituting the addressing circuits are shown in FIG. 4.

The signals 20 delivered on the output Sp1 of the circuit performing the even clock function 10 are represented accompanied by the respective states of the different boxes of the shift register 14 obtained after each pulse of the even clock signal. The signals 21 are delivered by the odd clock circuit 11 on the output Si1 of this circuit. These signals are accompanied by the respective states of the different boxes of the shift register 15 obtained after each pulse of the odd clock signal.

FIG. 4 presents an example where the states of the shift registers delivering voltages VI are represented on three line conductors of even number L2, L4, L6 and three of odd number L1, L3, L5. At each clock pulse, state 1 which corresponds to the voltage VI = Vmax at the output of the shift register advances by one box in the register, state 0 corresponding to the voltage VI = 0V for example. Line conductors of even number are addressed successively by applying a voltage Vl = Vmax. The same is true for odd numbered line conductors. The signals 22, 23 are delivered respectively by the outputs Sp4 and Si4 of the "enable" even and odd functions. These are tensions in the form of periodic slots. The high state of a slot corresponds to the voltage Vl = Vmax, the low state corresponds to the voltage VI = 0V, for example. The signals 22 and 23 are phase shifted, the phase shift is constant: the even and odd lines are addressed alternately.

The signals 25, 26, 27 correspond to the voltages VI delivered by the shift registers on the connections of the line conductors L1, L2 and L3. These are periodic slots whose period is the frame time.

This example of command sequence is given in the case of a strong overlap between the times of selection of the line conductors.

According to the proposed control mode, the circuit A1 which addresses the lines Li comprises, in register 15, as many logic levels (1 or 0) as there are lines. At each instant, only one of the logical levels is at 1, all the others are at zero. If the logic level 1 is, at the instant considered, associated with the line Li, it will, after a clock stroke shifted and associated with the line Li + 1.

A shift register equipped with the locking function only selects the line corresponding to logic level 1, that is to say in the case considered brings this line to the potential Vmax only if the "enable" function for example has the high state and does not select any line if the "enable" function presents for example the low state. When the "enable" function is in the low state, all the lines are at the locking potential. When the "enable" function is high, one line (associated with logic level 1 in the shift register) is at potential Vmax, the other lines (associated with logic level 0 in the shift register) are at potential lock. Circuit A2 has the same operation

FIG. 5 presents an example of a circuit 12 carrying out an "enable" function. This circuit 12 is controlled by the two circuits performing clock functions 10, 11. The inputs Ep1 and Ep2 of circuit 12 are connected respectively to the outputs Sp1 and Si1 of clocks 10 and 11. This example corresponds to the "enable" function forming part the addressing circuit for even numbered line conductors. The inputs Ep1 and Ep2 are in fact the respective inputs of two variable capacity monostables 16, 17. The respective outputs Mp, Mi of the two monostables are connected to two inputs Pp, Pi of a logic circuit 18. The output of this circuit 18 is the output Sp4 of circuit 12 carrying out the "enable" function.

FIG. 6 represents the time diagram of the signals coming from the outputs of the various elements making it possible to carry out the "enable" functions.

The clock pulses 28, 29 are the signals delivered by the circuits performing the clock functions 10, 11 on the inputs Ep1 and Ep2 of the circuit 12. The monostables with variable capacity 16, 17 respectively transform these pulses into rectangular signals 30, 31 whose width depends on the value of their capacity.

The falling edges of the rectangular signals 31 control the rise of the rectangular signals 32 delivered to the output Sp4 of the circuit 12, the falling edges of the rectangular signals 30 control the descent of the rectangular signals 32. Thus, the width of the signals 30, 31 controls the width of the rectangular signals delivered on the Sp4 output. By adjusting the value of the variable capacities of the monostables 16, 17, it is therefore possible to decide the width of the signals delivered on the output Sp4 and thereby the overlap time between the selection times of the line conductors.

The circuit 18 is formed by any set of known elements comprising logic gates, making it possible from the signals 30, 31 to obtain the signals 32.

The circuit 13 is produced in the same way as the circuit 12, from two monostables with variable capacities and from a logic circuit, the inputs of the monostables being connected respectively to circuits 10 and 11.

The signals 30 'and 31' represent an example of output signals from the monostables of the circuit 13. The signals 30 'and 31' are rectangular signals obtained in a similar manner to the signals 30, 31 from the respective clock pulses 28, 29. The signals 33 represent the resulting rectangular signals, obtained on the output Si4 of the circuit 13 in a similar manner to the generation of the signals 32 obtained on the output Sp4 of the circuit 12.

In the figures, the overlaps of the selection time of a line with the selection time of the previous line and that of the next line are identical, but of course they can be different. To achieve different recoveries, it suffices to have even and odd "enable" functions which have rectangular signals of different durations.

Claims (3)

1. Process for the control of a matrix display screen of the multiplexed type, i.e. in which the display time of an image point corresponds to its selection time, said screen being a microdot fluorescent screen or a liquid crystal screen, said screen having rwo conductors crossing column conductors, each overlap area of a row conductor and a column conductor defining an image point of the screen; said process consisting of applying periodically to the row conductors addressing signals V1 having for a certain time, called the row selection time Ts, a value Vmax in absolute values and having the same polarity for the corresponding row selection time and during the same frame the times during which said addressing signals have a value Vmax partly overlapping for two consecutive rows and applying control signals to column conductors.
2. Process for the control of a display screen according to claim 1, characterized in that the time during which the addressing signals V1 have a value Vmax is regulatable.
3. Apparatus for performing the control process for a display screen according to claim 1, characterized in that it comprises an addressing circuit A1 connected by connections to the row conductors Li, i being an uneven integer. such that 1≤i≤M, M being the number of row conductors, an addressing circuit A2 connected by connections to the row conductors Lp, p being an even integer such that 2 ≤ p ≤ m and in that the addressing circuit A2 comprises a circuit (10) performing a clock function supplying signals on an output Sp1, a circuit (12) performing an enable function connected by an input Ep1 to the output Sp1 of the circuit (10) performing the clock function and supplying signals on an output Sp4, a control circuit (14) connected by an input Ep4 to the output Sp4 of the circuit (12) performing the enable function and by an input Ep3 to the output Sp1 of the circuit (10) performing a clock function and supplying voltages V1 on the row conductors Lp connected thereto and in that the addressing circuit A1 comprises a circuit (11) performing a clock function supplying signals on an output Si1, a circuit (13) performing an enable function connected by an input Eil to the output Sil of the circuit (11) performing a clock function and supplying signals on an output Si4, a control circuit (15) connected by an input Ei4 to the output Si4 of the circuit (13) performing an enable function and by an input Ei3 to the output Sil of the circuit (11) performing a clock function and supplying voltages V1 on row conductors Li connected thereto and in that the circuit (12) performing an enable function in the addressing circuit A2 is also connected by an input Ep2 to an output Sil of the circuit (11) performing a clock function in the addressing circuit A1, the circuit (13) performing an enable function in the addressing circuit A1 also being connected by an input Ei2 to the output Spl of the circuit (10) performing a clock function in the addressing circuit A2, and in that the control signals applied to the row conductors have times during which they have a value Vmax, which partly overlap, for two consecutive rows.

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