EP0292550B1 - Apparatus for controlling the display of characters with visual attributes applied thereto - Google Patents
Apparatus for controlling the display of characters with visual attributes applied thereto Download PDFInfo
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- EP0292550B1 EP0292550B1 EP88900291A EP88900291A EP0292550B1 EP 0292550 B1 EP0292550 B1 EP 0292550B1 EP 88900291 A EP88900291 A EP 88900291A EP 88900291 A EP88900291 A EP 88900291A EP 0292550 B1 EP0292550 B1 EP 0292550B1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
- G09G5/30—Control of display attribute
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- Theoretical Computer Science (AREA)
- Controls And Circuits For Display Device (AREA)
Abstract
Description
- The present invention is concerned with apparatus for controlling the display of characters with visual attributes applied thereto.
- In video terminal devices which display textual material such as used in computer systems, means are generally provided to provide visual attributes to characters in the text being displayed. These visual attributes cause a selected character or characters to blink, to have a high or low intensity, to be underlined, to be blanked out, to have a light character on a dark background, or to be reversed with a dark character on a light background. The attribute data is typically carried in the data string which carries the text to be displayed, and thus takes up one character position. For example, U.S. Patent No. US-A- 3,895,374 discloses a system for displaying characters on a video display means, including data source means operative to produce a plurality of characters comprising data characters the images of which are to be displayed and attribute characters interspersed with the data characters and each specifying particular display attributes which the images of data characters following the attribute character are to have when displayed.
- European patent application No. EP-A-0189140 discloses apparatus for controlling the display of characters or symbols on a video display means. Each character is displayed as a series of scan lines and data relating to each scan line is generated by a processor from data stored in a memory. The stored data comprises address information identifying the position on the display where the character is to be displayed, information identifying the character, and attribute information for the character. From this data pixel information is generated and stored for the character in a further store together with attribute information for each pixel. This apparatus has the disadvantage that the attribute information therefore occupies a large amount of storage space.
- It is an object of the present invention to provide an apparatus for controlling the display of characters with visual attributes applied thereto, which apparatus requires reduced storage capacity for the information to be displayed.
- According to the invention, there is provided an apparatus for controlling the display on video display means of characters with visual attributes applied thereto, each character being arranged to be displayed in a predetermined number of scan lines, and said apparatus including memory means in which characters to be displayed are stored, characterized in that said memory means is arranged to store each of the characters to be displayed as a set of data bytes, each data byte of each set representing one scan line of the respective character, and for each character, a further data byte is stored, said further data byte being an attribute byte containing attribute data bits for application to the data bits of all the other data bytes of the set, said apparatus further including display controller means having a data input arranged to receive from said memory means each set of data bytes and each attribute data byte in respect of each character to be displayed, said display controller means including selecting means for selecting the attribute byte of a character to be displayed, attribute logic means for applying the attribute bits of each selected attribute byte to the data bits of the other data bytes of the corresponding character, and a video output for outputting data signals representing the character to be displayed with the attribute bits applied.
- It will be appreciated that, in an apparatus in accordance with the present invention, storage space can be saved by virtue of the fact that attribute bits can be stored in a row of normally unused bits of a character matrix.
- One embodiment of the invention will now be described by way of the example with reference to the accompanying drawings, in which:-
- Fig. 1 is a diagram of a portion of a bit mapped memory plane for storing characters with visual attributes applied thereto;
- Fig. 2 is a block diagram of a character display system including a display control apparatus in accordance with the present invention;
- Fig. 3 is a diagram of the screen of a CRT display device of the system of Fig. 2;
- Figs. 4A and 4B, joined along line a-a, form a block diagram of a display controller of the system of Fig. 2;
- Fig. 5 is a schematic diagram of a decode circuit of the display controller;
- Fig. 6 is a schematic diagram of another decode circuit of the display controller;
- Fig. 7 is a schematic diagram of an inhibit circuit of the display controller;
- Fig. 8 is a schematic diagram of another decode circuit of the display controller; and
- Figs. 9A and 9B, joined along line b-b, form a schematic diagram of an attribute logic circuit of the display controller.
- Fig. 1 is a diagrammatic representation of a portion of the bit mapped memory plane for storing characters with visual attributes applied thereto, wherein a portion of the memory plane for a single character is shown. Each character is represented in the memory plane by a
matrix 10. Thematrix 10 is nine bits wide (numbered one through nine), and thirteen scan lines long (numbered zero through twelve). In thematrix 10 shown in Fig. 1, selected bits are turned on to form the character "A". It will be understood that each bit in the bit mapped memory plane, a portion of which is represented in Fig. 1, represents one picture element or pixel to be displayed on the screen of a cathode ray tube (CRT) of, for instance, a computer terminal. The scan lines zero, ten and twelve are left blank to provide the appropriate spacing between rows of characters on the CRT screen. As will be discussed further, scan line eleven may be used to provide an underline, where designated, of the characters displayed on the CRT screen. In the description of the invention herein, the bits representing pixels which are not part of the selected character, for instance the character "A" of Fig. 1, will be referred to as the background, and the pixels which form the character to be displayed will be referred to as the foreground. - As shown in Fig. 1, scan line zero of
matrix 10 contains nine bits which may be selectively activated to represent attributes of the character of that nine by thirteen matrix. The first bit of scan line zero of thematrix 10 for each character is a reversed video (R) bit, the second bit is a half intensity or bold (H) bit, the third bit is an underline (U) bit, the fourth bit is a blink (B) bit, the fifth bit is a pixel (P) bit, the sixth bit is a suppress (S) bit, and the seventh, eight and ninth bits are general purpose bits whose functions may be designated as desired. For instance, the seventh bit could be used to implement a propagate attribute mode for serial field attributes. Also, the eighth bit could provide a protect function for data entry form applications. The nine bits making up one scan line of one character are referred to herein as a byte, and such bits of scan line zero of one character are referred to herein as an attribute byte. Thus, in the present invention, the attribute byte for each character to be displayed on the screen is a portion of, and is passed to a display controller as a part of, each character to be displayed. - Fig. 2 is a block diagram of a system using the present invention. The system of Fig. 2 includes a central processing unit (CPU) 12, which may be a computer or microprocessor which has a CRT type video monitor device 24 for displaying data characters. The
CPU 12 is connected to amulticonductor data bus 14 for sending or receiving data, and amulticonductor address bus 16 for supplying an address to a memory. The system includes a random access memory (RAM) 18 for storing data to be read into theCPU 12 or written from theCPU 12 into theRAM 18 by appropriate read/write commands over thedata bus 14. Abidirectional gate 20 is in thedata bus 14 between theRAM 18 andCPU 12 for controlling data transmission between theCPU 12 and theRAM 18. TheCPU 12, theRAM 18, and thebi-directional bus gate 20 are well understood in the art and will not be discussed further herein. - A
display controller 22 is provided to display a screen of data stored in theRAM 18 on the video monitor device 24. Amultiplexer 26 is provided in theaddress bus 16 between theCPU 12 and theRAM 18. Anaddress bus extension 28 is connected between theaddress bus 16 of theCPU 12 and an address input A of thedisplay controller 22. Thecontroller 22 includes a direct memory access (DMA) counter, to be discussed later, which supplies display addresses over adisplay address bus 32 via themultiplexer 26 to theRAM 18. Amultiplexer control line 34 is connected between thedisplay controller 22 and themultiplexer 26 for controlling transmission of the display address to theRAM 18. The display address may come from either thedisplay controller 22 over thedisplay address bus 32 or over theaddress bus 16 from theCPU 12. Adatabus extension 36 is connected between theCPU data bus 14 and input D of thedisplay controller 22. Acrystal oscillator 40 supplies video dot clock signals to thedisplay controller 22 overconductor 42, and a synchronizer means (SYNC) 44 synchronizes both theCPU 12 anddisplay controller 22 overconductors - The video monitor device 24 receives video signals over
conductor 50 from thedisplay controller 22, vertical drive signals overconductor 52 and horizontal drive signals overconductor 54. As is known, the video monitor device 24 includes avideo amplifier 56 for receiving and amplifying a video signal for the electron gun of aCRT device 58, avertical amplifier 60 for receiving vertical drive signals overconductor 52, and ahorizontal amplifier 64 for receiving horizontal drive signals overconductor 54. As is well known, thehorizontal amplifier 64, when energized by the horizontal drive signal, generates a ramp signal which sweeps an electron beam horizontally across the face of theCRT 58, and thevertical amplifier 60 generates a ramp signal which sweeps the electron beam vertically down the face of theCRT 58. The operation of such video monitor device 24 is well understood in the art and will not be explained further herein. - It can thus be seen that a full screen of information may be written into the
RAM 18 by theCPU 12. The addresses for the placement of the screen data are passed over theRAM address bus 16 through themultiplexer 26 to the address terminal A of theRAM 18. The data may be passed, a byte at a time, over thedata bus 14 through thebus gate 20 to the data terminal D of theRAM 18. When that portion of theRAM 18 which represents the screen of the CRT 58 (referred to herein as the bit plane memory) is thus loaded, thedisplay controller 22 may access the screen data a byte at a time by sending an address over thebus 32 via themultiplexer 26. The screen data is then passed from theRAM 18 to thedisplay controller 22, a byte at a time, viadata bus extension 36. The starting address of the data to appear at the top of the screen is always zero in this description. The starting address could be passed by theCPU 12 to thedisplay controller 22 over theaddress buses - The bit plane memory in the
RAM 18 may be accessed starting at the designated top of screen byte. Certain global attributes to be applied to the entire screen, or portions of the screen, may be passed over thedata buses display controller 22 and identified by a specified RAM address transmitted by theCPU 12 over theaddress buses display controller 22 to recognize global attribute commands from theCPU 12. - Fig. 3 is a representation of a
screen 62 of theCRT 58 of Fig. 2. Thescreen 62 has a display character "A" in amatrix 66 at the first display position at the top of thescreen 62. As discussed in connection withmatrix 10 of Fig. 1, thematrix 66 may be nine pixels wide and have thirteen scan lines. The characters displayed on the screen are arranged in rows with each row having a predetermined number of characters. In the example used herein, each row contains eighty characters with a total of twenty-five rows of text being displayed on thescreen 62 at one time. As discussed previously, if each of the nine bits of one scan line of thecharacter matrix 66 is considered to be one byte, the entire screen of characters may be represented by eighty bytes per scan line times thirteen scan lines per character times twenty-five rows or 26,000 bytes. Thus, to store the bit plane memory for the entire contents of thescreen 62, theRAM 18 of Fig. 2 must contain storage for at least 26,000 bytes, each character to be displayed being represented by a set of 13 bytes. - Provision is made in the
display controller 22 of Fig. 2 to count the number of characters to be displayed in each row for controlling the horizontal drive signal output onconductor 54. Thecontroller 22 typically counts one hundred characters per row to provide time equivalent to twenty characters for flyback in thehorizontal amplifier 64. A total of 325 scan lines are required to provide twenty-five rows of characters with each row having thirteen scan lines. Time equivalent to an additional thirty scan lines is provided by thedisplay controller 22 to allow for vertical retrace of thevertical amplifier 60 of Fig. 2. - Figs. 4A and 4B form a block diagram of the
display controller 22 of Fig. 2. Thedisplay controller 22 includes a modulo nine counter 70, whose input receives the video dot clock signal overconductor 42 from thecrystal oscillator 40 of Fig. 2. The output of the counter 70 is connected to the input of a modulo one hundred counter 71, whose output is connected to the input of a modulo 355 counter 72 (see Fig. 4B). The counter 70 counts nine video dot clock signals from thecrystal oscillator 40 and outputs a character clock signal onconductor 102 to indicate the beginning of a new character. The counter 71 counts the character clocks signals output by the counter 70 and outputs a scan clock signal onconductor 122 to indicate the beginning of a new scan line. The counter 72 counts 355 scan clock signals from the output of counter 71 to keep track of the number of scan lines displayed on thescreen 62 of Fig. 3. The counter 71 also outputs seven bits overbus 73 to give the number of characters counted by counter 71. Similarly, counter 72 outputs a nine bit value overbus 74 to indicate the number of scan lines counted by the counter 72. The characters counted by the counter 71 are inputted to adecode circuit 76 for use in generating a horizontal drive signal and a horizontal blanking signal to be outputted onoutputs bus 74 by the counter 72 is inputted into adecode circuit 79 for generating a vertical drive signal and a vertical blanking signal onconductors conductor 80 is connected to terminal F of thedisplay controller 22 and the horizontal drive signal onconductor 77 is connected to terminal G of the display controller (see Fig. 4B). - Fig. 5 is a schematic diagram of the
decode circuit 76 of fig. 4A. Thedecode circuit 76 has anOR gate 83 whose input is connected to the fifth and sixth bits of the inputted character number over thebus 73 from counter 71. The output of theOR gate 83 is inputted to one input of an ANDgate 84, and a second input of the ANDgate 84 receives the seventh bit from thebus 73. The output of the ANDgate 84 provides the horizontal drive signal (HDRIVE) onconductor 77 and the horizontal blanking signal (HBLANK) onconductor 78. Thus, the HBLANK signal is enabled when the character count from counter 71 of fig. 4A is between eighty and one hundred. - Fig. 6 is a schematic diagram of the
decode circuit 79 of Fig. 4B. Thedecode circuit 79 has an ANDgate 85 whose inputs are connected to the third, seventh and ninth bits of the scan line number signal outputted on thebus 74 from the counter 72. When these bits are turned on, the value of the scan line number is equal to 324, and the output of the ANDgate 85 is enabled. The output of the ANDgate 85 is connected to the data terminal of a D-type flip flop 86. The clock terminal of theflip flop 86 is connected to the first bit of thebus 74. The reset terminal of theflip flop 86 is connected to the ninth bit, and the inverted output of theflip flop 86 is connected its set input. The non-inverted output of theflip flop 86 is connected toconductor 81 for supplying the vertical blanking (VBLANK) signal of Fig. 4B. On the next positive going edge of the first bit occurring after the scan line number value from counter 72 is equal to 324 (value 325), the non-inverted output of theflip flop 86 goes high. Thus, the VBLANK signal onconductor 81 goes high atscan line number 325 and stays high until the ninth bit turns off when the scan line number value from counter 72 becomes zero. - The
decode circuit 79 also includes an ANDgate 97 whose inputs are connected to the inverted fourth bit from aninverter 95, and to the fifth bit, the seventh bit and the ninth bit received onbus 74 from counter 72. When the count from counter 72 is equal to 336, the inputs of the ANDgate 97 are enabled, and the output of theAN D gate 97 goes high. The output of the ANDgate 97 is connected to the data terminal of a D-type flip flop 98, whose clock terminal is connected to the third bit of thebus 74. An ANDgate 99 has its input terminals connected to the fourth, fifth, seventh and ninth bits of thebus 74. When these bits are enabled, the scan line number value from the counter 72 is equal to 344. The output of the ANDgate 99 then goes high, which is inverted by aninverter 100, to a low, which is connected to the reset terminal of the D-type flip flop 98. The inverted output of theflip flop 98 is connected to its set input, and the non-inverted output is connected toconductor 80 of Fig. 4B for providing the vertical drive (VDRIVE) signal. It will thus be seen that when the third bit is turned on after the scan line number value of counter 72 reaches 336 (the value 340), the VDRIVE signal onconductor 80 goes high and remains high until the scan line number value of counter 72 reaches 344. - Returning now to Fig. 4A, it is seen that the
display controller 22 includes an inhibitcircuit 101 which inhibits passing of the character clock signal received overconductor 102 from the output of the counter 70 during either vertical blanking or horizontal blanking. - Fig. 7, on the drawing containing Fig. 2, is a schematic diagram of a circuit which may be used for the inhibit
circuit 101 of Fig. 4A. An ORgate 104 has one input connected toconductor 78 for receiving the HBLANKsignal fromdecode circuit 76, and has a second input connected toconductor 81 for receiving the HBLANK signal from thedecode circuit 79 of Fig. 4B. The output of theOR gate 104 is connected to one input of an ANDgate 105 whose second input is connected toconductor 102 for receiving the character clock signal from the counter 70 of Fig. 4A. The output of the ANDgate 105 is connected to conductor 106 (see also Fig. 4A). Thus, the inhibitcircuit 101 passes character clock signals fromconductor 102 only when both the VBLANK and HBLANK signals are not enabled. Theconductor 106 is connected to one input of a direct memory access (DMA) counter 107 (see Fig. 4A). The DMA counter 107 is a modulo 26,000 counter which counts from zero to 25,999.Conductor 80 provides the vertical drive signal to the counter 107 to reset it for each frame. Thus, RAM address zero is always the first data fetched for the top of thescreen 62. The DMA counter 107 is connected to thedisplay address bus 32 for supplying direct memory access addresses to themultiplexer 26 for addressing the RAM 18 (see Fig. 2). It will be understood that when the DMA counter 107 sends an address to theRAM 18 overbuses multiplexer 26, one byte of pixel display data is returned to thedisplay controller 22 overbus 36 from data stored at that address in theRAM 18. - The byte of pixel data thus received on
bus 36 is placed in a latch 110 (Fig. 4A) which acts as a one character delay device. Pixel data is clocked into the latch 110 by a character clock signal received overconductor 102 from the counter 70. After a one byte delay, pixel data is transferred from the latch 110 into a ninebit shift register 112 of Fig. 4B over anintermediate bus 114. The pixel data is caused to be loaded frombus 114 into theshift register 112 by the character clock signal viaconductors bus 114 are shifted one at a time from theshift register 112 by each video dot clock signal received overconductors shift register 112 ontoconductor 116 as the serial video (SERVIDEO) signal. When the SERVIDEO signal has a value of one, thescreen 62 foreground is enabled to form a character, and when the SERVIDEO signal has a value of zero, thescreen 62 background is enabled. The SERVIDEO signal fromoutput 116 ofshift register 112 is inputted into theattribute logic 118, to be discussed later with respect to Figs. 9A and 9B. - Referring to Fig. 4B, a modulo 13
counter 120 is provided which counts scan clocks received overline 122 from the output of counter 71 (Fig. 4A). Thecounter 120 counts from zero to twelve which represents the scan line being displayed for each character (see Fig. 1). The output of thecounter 120 is a binary value on a fourbit bus 123 which is inputted into adecode circuit 124. - Fig. 8 is a schematic diagram of the
decode circuit 124 of Fig. 4B. As illustrated, thedecode circuit 124 includes an ANDgate 126 whose inputs are connected to the third and fourth bits of thebus 123, and whose output provides a multiplexer control (MPX12/0) signal onconductor 128, to be explained. An ANDcircuit 130 is also provided having its inputs connected to the first, second and fourth bits of thebus 123. As discussed hereinafter with respect to Fig. 9A, when the count onbus 123 is equal to eleven, the output of ANDgate 130 will be an underline enable (ULENA) signal onconductor 131. When the ULENA signal onconductor 131 is active, the count ofcounter 120 will be eleven indicating that the eleventh scan line of a row of characters is being displayed. - An AND
gate 132 has its inputs connected to inverted first, second, third and fourth bits inverted byinverters gate 132 onconductor 138 is a scan line zero (SCANO) signal which indicates that the first scan line, or scan line zero, of a row of characters is being displayed. - Returning to Fig. 4B, a
multiplexer 140 is controlled by the MPX12/0 signal onconductor 12 from thedecode circuit 124 just explained. Aring shift register 142 has its input connected to the output of themultiplexer 140 for receiving bytes of pixel data from thedata bus 36. Thering shift register 142 forms part of a selecting circuit to select eighty bytes of attribute data from thedata bus 36, one byte for each character to be displayed in a complete row of data on theCRT screen 62, as previously discussed. One input of themultiplexer 140 is connected to thedata bus 36 from the RAM 18 (see Fig. 2). Adata bus 144 is provided from the output of thering shift register 142 to the other input of themultiplexer 140. Loading data to, and bypassing data around,ring shift register 142 is controlled by the MPX12/0 signal overconductor 128A to the LB terminal of thering shift register 142. - Because of the latch 110 of Fig. 4A, the byte of pixel data presented to the shift register 112 (Fig. 4B) will be one character time behind the pixel data being received through the
multiplexer 140 by thering shift register 142. On scan line zero, the MPX12/0 signal onconductor 128 will be active for passing the attribute data bytes through themultiplexer 140 from thedata bus 36 to thering shift register 142, thereby storing the attributes of a complete row of eighty characters to be displayed on thescreen 62.Conductor 160A, from the inhibitcircuit 101, controls the shifting of attribute bytes out of theregister 142. In the scan lines 1-12 of a current row, attribute bytes will be shifted sequentially out of theregister 142 to be used for the character presently being displayed. Attribute bytes are also fed back into thering shift register 142 over thebus 144 and through themultiplexer 140 to be used in subsequent scan lines of the same row of eighty characters, until all the scan lines of that row have been displayed. The attribute byte output from thering shift register 142 is placed on abus 170 to anattribute latch 172 and transmitted to theattribute logic 118 overbus 186. - An address decode circuit 150 of Fig. 4A is provided to decode the address on the RAM
address bus extension 28 to determine if the address passed by theCPU 12 to theRAM 18 is the address for the location of theRAM 18 for storing global functions, i.e. functions which, when enabled, continuously affect the display on theCRT screen 62. When the address for global functions is recognized by the address decode circuit 150, a load latch signal onconductor 156 is enabled to latch data on thedata bus 36 into alatch 158, (see Fig. 4B). These global functions may include a blink rate signal (BLINK) onconductor 160, a blank background signal (BLKBKG) onconductor 161, a graphics signal (GRAPHICS) onconductor 162, and an attribute propagation mode signal (APMODE) onconductor 163. - Figs. 9A and 9B form a schematic diagram of the
attribute logic 118 of Fig. 4B. Theattribute logic 118 includes a circuit 190 (Fig. 9A) for determining if the fifth pixel of scan line zero of each character is to be turned on when the pixel (P) attribute is activated, a circuit 191 (Fig. 9A) for decoding the global functions fromlatch 158 of Fig. 4B, a decode circuit 192 (Fig. 9A) for decoding the attribute bits passed by theattribute latch 172 and an output circuit 193 (Fig. 9B) for outputting a video signal overconductor 50 to the monitor device 24 of Fig. 2. - The
circuit 190 includes an inverter200 for inverting the second bit from abus 202 which carries the count from counter 70 of Fig. 4A. The first and third bits and inverted second bit are inputted into an ANDgate 203 to determine if the count on thebus 202 is equal to five. The output of the ANDgate 203 is inputted into an ANDgate 204 with the SCANO signal onconductor 138 from thedecode circuit 124 of Fig. 4B, and the pixel attribute bit (P) frombus 186 of Fig. 4B. Thecircuit 190 thus turns on the fifth pixel of scan line zero for those characters having the pixel attribute bit (P) enabled. The pixel attribute is used for a business graphics (orthogonal only) implementation in a text mode. Theoutput 205 of the ANDgate 204 is inputted into an ORgate 206. The SERVIDEO signal onconductor 116 is inputted into an ANDgate 900 while the SCANO signal onconductor 138 is inputted into aninverter 901 whoseoutput 902 is likewise inputted into the AND 900. Thus, theoutput 903 of ANDgate 900, which is connected to one input of theOR gate 206, is blanked during scan line zero, which is the attribute scan. In this way, the attribute bits in the attribute byte are not displayed on theCRT screen 62. - The
circuit 191 includes an exclusive ORgate 208 having one input connected to the blank background (BLKBKG) signal onconductor 161 fromlatch 158 of Fig. 4B. The other input of exclusive ORgate 208 is connected to the reverse attribute bit (R) of the attribute byte onbus 186. The output of exclusive ORgate 208 is inverted by aninverter 210 whose output is connected toconductor 225. Thus, the signal onconductor 225 is high if one only of either the BLKBKG global function onconductor 161, or the reverse attribute bit (R) is enabled. - The
circuit 192 includes an ANDgate 212 having one input connected to the BLINK global function onconductor 160, and another input connected to the blank attribute bit (B) of the attribute byte onbus 186. The output of the ANDgate 212 is inverted by aninverter 213. Aninverter 214 is included to invert the suppress attribute bit (S) of the attribute byte onbus 186. The output of theinverter 214 is inputted into an ANDgate 215, whose other input is connected to the output of theOR gate 206. The output of theinverter 213 and the output of the ANDgate 215 are inputted into an ANDgate 216 of Fig. 9B. Thus, the output of the ANDgate 216 contains the condition of a pixel in the foreground when the global functions and the attributes are applied. - An AND
gate 218 of Fig. 9A has one input connected to the underline attribute bit (U) from the attribute byte onbus 186, and a second input connected toconductor 131 for receiving the ULENA signal fromdecode circuit 124 of Fig. 4B. As discussed in connection with Fig. 8, the ULENAsignal is active only during the eleventh scan of a character. Thus, if the underline attribute is enabled, the bits of the foreground will be turned on during the eleventh scan of the character to form an underline. An ORgate 220 of Fig. 9B has one input connected to the output of the ANDgate 216, and one input connected to the output of the ANDgate 218. Thus, the output onconductor 222 of theOR gate 220 carries the foreground state of the pixel to be displayed and the underline when the underline attribute is enabled. - An exclusive OR
gate 224 has one input connected to theconductor 222 for receiving the output of ORgate 220, and one input connected toconductor 225 for receiving the output ofinverter 210 of Fig. 9A. Thus, the output of the exclusive ORgate 224 contains the foreground state of the pixel to be displayed with all of the attributes and global functions applied except the half intensity attribute (H). Amultiplexer 230, which is controlled by the GRAPHICS global function bit onconductor 162, has the SERVIDEO signal onconductor 116A of Fig. 9A inputted into one input thereof and has the output of the exclusive ORgate 224 inputted into a second input thereof overconductor 232. Thus, when the GRAPHICS global function bit onconductor 162 is enabled, the state of the pixel on theconductor 116A is multiplexed onto theconductor 234 by themultiplexer 230. On the other hand, when the GRAPHICS global function bit onconductor 162 is disabled, the state of the pixel on theconductor 232 is multiplexed onto theconductor 234 by themultiplexer 230. A non-invertingopen collector amplifier 235 receives the multiplexed value viaconductor 234 and its output is connected to anode 236 of a voltage divider circuit formed byresistors conductor 162 is inverted by aninverter 242 and inputted over aconductor 243 to one input of aNAND gate 244. A second input of theNAND gate 244 receives the half intensity attribute bit (H) of the attribute byte onbus 186. TheNAND gate 244 has an open collector output. Thus, when the GRAPHICS global function bit onconductor 162 is not enabled (GRAPHICS* is high) and the half intensity attribute bit (H) is enabled, the output ofNAND gate 244 is grounded, thereby grounding one end ofresistor 241 and forming a voltage divider with the resulting voltage onnode 236 being at a set percentage of its normal value. This will result in a signal being provided at a lower intensity to theCRT screen 62. In the GRAPHICS mode (GRAPHICS is high), the SERVIDEO signal will appear atnode 236 at its normal value, thus providing regular intensity to theCRT screen 62. Also, in the non-graphics mode (GRAPHICS* is high) with the half intensity attribute bit low, the signal atnode 236 will be at its normal value. An NPN transistor250 provides the video out signal onconductor 50 dependent upon the voltage atnode 236 which appears on its base.
Claims (8)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US93847486A | 1986-12-05 | 1986-12-05 | |
US938474 | 1986-12-05 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0292550A1 EP0292550A1 (en) | 1988-11-30 |
EP0292550B1 true EP0292550B1 (en) | 1992-07-01 |
Family
ID=25471503
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP88900291A Expired - Lifetime EP0292550B1 (en) | 1986-12-05 | 1987-11-27 | Apparatus for controlling the display of characters with visual attributes applied thereto |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0292550B1 (en) |
JP (1) | JPH01501576A (en) |
DE (1) | DE3780164T2 (en) |
WO (1) | WO1988004461A1 (en) |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0189140A3 (en) * | 1985-01-24 | 1990-05-30 | Siemens Aktiengesellschaft | Control system for raster scan displays |
-
1987
- 1987-11-27 DE DE19873780164 patent/DE3780164T2/en not_active Expired - Fee Related
- 1987-11-27 EP EP88900291A patent/EP0292550B1/en not_active Expired - Lifetime
- 1987-11-27 WO PCT/US1987/003074 patent/WO1988004461A1/en active IP Right Grant
- 1987-11-27 JP JP50065788A patent/JPH01501576A/en active Pending
Non-Patent Citations (2)
Title |
---|
IBM Technical Disclosure Bulletin, volume 23, no. 6, November 1980, (New York, US), D.R. Mersel: "Highlighting image data on pel for pel addressabledisplays" pages 2342-2343. * |
IBM Technical Dislosure Bulletin, vol. 27, no. 10A, March 1985, (New York, US) "Alphanumeric display buffer", pages 5530-5533. * |
Also Published As
Publication number | Publication date |
---|---|
EP0292550A1 (en) | 1988-11-30 |
JPH01501576A (en) | 1989-06-01 |
WO1988004461A1 (en) | 1988-06-16 |
DE3780164D1 (en) | 1992-08-06 |
DE3780164T2 (en) | 1993-02-25 |
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