EP0283891A3 - Cache memory with hit predictive logic - Google Patents

Cache memory with hit predictive logic Download PDF

Info

Publication number
EP0283891A3
EP0283891A3 EP88103991A EP88103991A EP0283891A3 EP 0283891 A3 EP0283891 A3 EP 0283891A3 EP 88103991 A EP88103991 A EP 88103991A EP 88103991 A EP88103991 A EP 88103991A EP 0283891 A3 EP0283891 A3 EP 0283891A3
Authority
EP
European Patent Office
Prior art keywords
cache memory
predictive logic
hit
hit predictive
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP88103991A
Other versions
EP0283891B1 (en
EP0283891A2 (en
Inventor
Claudio Fiacconi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Original Assignee
Bull HN Information Systems Italia SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull HN Information Systems Italia SpA filed Critical Bull HN Information Systems Italia SpA
Publication of EP0283891A2 publication Critical patent/EP0283891A2/en
Publication of EP0283891A3 publication Critical patent/EP0283891A3/en
Application granted granted Critical
Publication of EP0283891B1 publication Critical patent/EP0283891B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6026—Prefetching based on access pattern detection, e.g. stride based prefetch

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
EP88103991A 1987-03-25 1988-03-14 Cache memory with hit predictive logic Expired - Lifetime EP0283891B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT1983287 1987-03-25
IT19832/87A IT1202687B (en) 1987-03-25 1987-03-25 BUFFER MEMORY AT HIT'S PREDICTION

Publications (3)

Publication Number Publication Date
EP0283891A2 EP0283891A2 (en) 1988-09-28
EP0283891A3 true EP0283891A3 (en) 1990-07-18
EP0283891B1 EP0283891B1 (en) 1994-07-06

Family

ID=11161653

Family Applications (1)

Application Number Title Priority Date Filing Date
EP88103991A Expired - Lifetime EP0283891B1 (en) 1987-03-25 1988-03-14 Cache memory with hit predictive logic

Country Status (4)

Country Link
US (1) US4912626A (en)
EP (1) EP0283891B1 (en)
DE (1) DE3850514T2 (en)
IT (1) IT1202687B (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5151982A (en) * 1988-03-30 1992-09-29 Kabushiki Kaisha Toshiba Data processing system
US5123097A (en) * 1989-01-05 1992-06-16 Bull Hn Information Systems Inc. Apparatus and method for simultaneous execution of a write instruction and a succeeding read instruction in a data processing system with a store through cache strategy
US5093777A (en) * 1989-06-12 1992-03-03 Bull Hn Information Systems Inc. Method and apparatus for predicting address of a subsequent cache request upon analyzing address patterns stored in separate miss stack
JPH04233642A (en) * 1990-07-27 1992-08-21 Dell Usa Corp Processor which performs memory access in parallel with cache access and method used therrfor
US5392414A (en) * 1992-06-30 1995-02-21 Sun Microsystems, Inc. Rapid data retrieval from data storage structures using prior access predictive annotations
US5513143A (en) * 1992-07-31 1996-04-30 Sgs-Thomson Microelectronics, Inc. Data cache memory internal circuitry for reducing wait states
US5553270A (en) * 1993-09-01 1996-09-03 Digital Equipment Corporation Apparatus for providing improved memory access in page mode access systems with pipelined cache access and main memory address replay
US5548739A (en) * 1993-11-04 1996-08-20 Sun Microsystems, Inc. Method and apparatus for rapidly retrieving data from a physically addressed data storage structure using address page crossing predictive annotations
US5860104A (en) * 1995-08-31 1999-01-12 Advanced Micro Devices, Inc. Data cache which speculatively updates a predicted data cache storage location with store data and subsequently corrects mispredicted updates
US5752069A (en) * 1995-08-31 1998-05-12 Advanced Micro Devices, Inc. Superscalar microprocessor employing away prediction structure
US5987561A (en) 1995-08-31 1999-11-16 Advanced Micro Devices, Inc. Superscalar microprocessor employing a data cache capable of performing store accesses in a single clock cycle
US5838943A (en) * 1996-03-26 1998-11-17 Advanced Micro Devices, Inc. Apparatus for speculatively storing and restoring data to a cache memory
GB2378779B (en) * 2001-08-14 2005-02-02 Advanced Risc Mach Ltd Accessing memory units in a data processing apparatus
US20050050278A1 (en) * 2003-09-03 2005-03-03 Advanced Micro Devices, Inc. Low power way-predicted cache
US7117290B2 (en) * 2003-09-03 2006-10-03 Advanced Micro Devices, Inc. MicroTLB and micro tag for reducing power in a processor
US7395372B2 (en) * 2003-11-14 2008-07-01 International Business Machines Corporation Method and system for providing cache set selection which is power optimized
US10257264B1 (en) * 2016-02-22 2019-04-09 Yume, Inc. System and method for reducing data center latency

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4170039A (en) * 1978-07-17 1979-10-02 International Business Machines Corporation Virtual address translation speed up technique

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4363095A (en) * 1980-12-31 1982-12-07 Honeywell Information Systems Inc. Hit/miss logic for a cache memory
US4445177A (en) * 1981-05-22 1984-04-24 Data General Corporation Digital data processing system utilizing a unique arithmetic logic unit for handling uniquely identifiable addresses for operands and instructions
US4458310A (en) * 1981-10-02 1984-07-03 At&T Bell Laboratories Cache memory using a lowest priority replacement circuit
US4603380A (en) * 1983-07-01 1986-07-29 International Business Machines Corporation DASD cache block staging

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4170039A (en) * 1978-07-17 1979-10-02 International Business Machines Corporation Virtual address translation speed up technique

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 25, no. 11B, April 1983, pages 5978-5980, New York, US; R.N. RECHTSCHAFFEN: "Cache miss history table" *

Also Published As

Publication number Publication date
EP0283891B1 (en) 1994-07-06
US4912626A (en) 1990-03-27
IT1202687B (en) 1989-02-09
DE3850514D1 (en) 1994-08-11
IT8719832A0 (en) 1987-03-25
DE3850514T2 (en) 1994-10-27
EP0283891A2 (en) 1988-09-28

Similar Documents

Publication Publication Date Title
EP0412245A3 (en) Cache memory
EP0283891A3 (en) Cache memory with hit predictive logic
EP0409415A3 (en) Fast multiple-word accesses from a multi-way set-associative cache memory
EP0258559A3 (en) Cache memory coherency control provided with a read in progress indicating memory
EP0450285A3 (en) Cache memory
GB2260429B (en) Versatile cache memory
DE3176266D1 (en) Cache addressing mechanism
EP0596636A3 (en) Cache tag memory
AU1768288A (en) Parallel associative memory
EP0412247A3 (en) Cache memory system
HK5095A (en) Floating gate memories
EP0657819A3 (en) Cache memory.
EP0180239A3 (en) Content-addressable memory
EP0463770A3 (en) Computer with cache
BR8804635A (en) FRIDGE WITH THREE-DIMENSIONAL BRANDS
EP0284751A3 (en) Cache memory
AU578420B2 (en) Cache memory
EP0267628A3 (en) Microprocessor with a cache memory
EP0432524A3 (en) Cache memory architecture
EP0265108A3 (en) Cache storage priority
EP0250702A3 (en) Cache memory with variable fetch and replacement schemes
EP0365116A3 (en) Buffer memory arrangement
GB2214336B (en) Cache memory apparatus
EP0260837A3 (en) Microprocessor with selective cache memory
GB2214669B (en) Cache memory

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE FR GB

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: BULL HN INFORMATION SYSTEMS ITALIA S.P.A.

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): DE FR GB

17P Request for examination filed

Effective date: 19900927

17Q First examination report despatched

Effective date: 19920904

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

REF Corresponds to:

Ref document number: 3850514

Country of ref document: DE

Date of ref document: 19940811

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20040305

Year of fee payment: 17

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20050225

Year of fee payment: 18

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20050325

Year of fee payment: 18

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20051001

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20060314

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20060314

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20061130

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20060331