EP0272006A2 - Anzeigen-Steuereinrichtung für Datenverarbeitungsgeräte - Google Patents

Anzeigen-Steuereinrichtung für Datenverarbeitungsgeräte Download PDF

Info

Publication number
EP0272006A2
EP0272006A2 EP87310229A EP87310229A EP0272006A2 EP 0272006 A2 EP0272006 A2 EP 0272006A2 EP 87310229 A EP87310229 A EP 87310229A EP 87310229 A EP87310229 A EP 87310229A EP 0272006 A2 EP0272006 A2 EP 0272006A2
Authority
EP
European Patent Office
Prior art keywords
display
mode
memory
window
character
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP87310229A
Other languages
English (en)
French (fr)
Other versions
EP0272006A3 (de
Inventor
Pierangelo Tosi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telecom Italia SpA
Olivetti SpA
Original Assignee
Olivetti SpA
Ing C Olivetti and C SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olivetti SpA, Ing C Olivetti and C SpA filed Critical Olivetti SpA
Publication of EP0272006A2 publication Critical patent/EP0272006A2/de
Publication of EP0272006A3 publication Critical patent/EP0272006A3/de
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/14—Display of multiple viewports
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/40—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which both a pattern determined by character code and another pattern are displayed simultaneously, or either pattern is displayed selectively, e.g. with character code memory and APA, i.e. all-points-addressable, memory

Definitions

  • the present invention relates to a display controller for data processing apparatus, of the type set forth in the preamble of claim 1.
  • Normally display controllers the above-mentioned type comprise a display refresh memory which can be recorded with the codes for alpha-numeric characters or in accordance with a map of pixels or graphic dots.
  • the refresh memory has a capacity for map recording dots equal to the dots which can be displayed on the display, but it is not possible for it simultaneously to record alpha-numeric codes and graphic pixels.
  • the characters in such window must first be recorded as a map of dots in the refresh memory.
  • An alpha-numeric display controller has been proposed, which is capable of dividing the refresh memory into different windows which can be controlled independently to provide for horizontal and vertical movement or scroll of the texts.
  • an auxiliary memory carries the list of rows of characters to be displayed. Therefore on the one hand the windows divide the screen only vertically while on the other hand the memory is recorded in accordance with a single alpha-numeric mode in a manner corresponding to all the windows.
  • a display controller which comprises a refresh memory formed by a plurality of pages which are read in parallel relationship for displaying colour images. That controller makes it possible to record a first page by means of alpha-numeric codes while the other pages are recorded with a dot map. In the display operation, it is possible to select complementary zones of the first page and the other pages in such a way as to substitute an alpha-numeric text for a graphic portion.
  • control does not make it possible simultaneously to display characters and graphics of different definitions, so that it is not very flexible.
  • the object of the present invention is to provide a display control in which the refresh memory can be recorded and displayed simultaneously with character codes and dot map.
  • That arrangement finds practical application for example in work stations of banking type, in which the operation, by a single display operation, can check both the state of the account of the customer, which is recorded by means of codes, and the customer signature which is recorded in graphic form.
  • reference numeral 10 generally indicates a central unit (CPU) of a computer, for example a personal computer, which is connected by means of a data and address channel or bus 11 to a working read-write memory (RAM) 12 and a read only memory (ROM) 13. Also connected to the bus 11 is a series of input/output units such as a keyboard 14, a printer 15, a floppy disc unit 16 and a display controller 17 which controls the display of data and images on a display unit 18, for example of cathode ray tube (CRT) type.
  • CPU central unit
  • RAM working read-write memory
  • ROM read only memory
  • the display controller 17 (see Figure 2) comprises a tube control unit (CRTC) 19 which is programmable to generate the vertical and horizontal timing signals and the raster address signals for control of the display. It comprises a logic means for controlling the cursor, the movement of the image and the other functions required of the display.
  • the unit 19 may be formed by the integrated component HD6345 produced by Hitachi and permits sub-division into four segments in the vertical direction of the image on the screen, with independent scroll in the individual segments and control of two independent cursors.
  • the unit 19 comprises a series of registers for controlling the various functions, including two horizontal and vertical synchronisation registers, for indicating the position or cell of the character to be displayed, as a multiple of the period of a character on the line, or line of characters, as will be described in greater detail hereinafter.
  • the display controller 17 can control both the display of characters in accordance with a pixel or dot matrix having a given number of columns and rows, and the display of graphics, the pixels of which are recorded in a memory in accordance with a memory bit map.
  • the display is effected with the same definition as the graphic mode with 640 ⁇ 400 pixels.
  • the dot matrix of 8 columns ⁇ 16 rows defines a cell on the screen whereby the screen can contain a total of 2000 cells.
  • the logic means of the unit 19 is controlled by a group 21 of input/output registers (I/O) connected thereto by a data bus 20 which in turn is connected to the bus 11 by way of a data interface 22.
  • the registers 21 serve to define the operating conditions or modes of the control and the modes in which the images are to be displayed.
  • the controller 17 further comprises a display refresh memory 23 which is connected to the unit 19 by means of a latch 25 and a multiplexer 26.
  • An address interface 24 is connected to the multiplexer 26 and to a unit 44 for selection between the memory and the registers 21.
  • the logic means of the unit 19 can send an interrupt requires to the CPU 10 to permit the latter to recognise undesired accesses to the memory 23 or to the registers 21.
  • the interrupt request is transmitted on the bus 11 by way of an interrupt interface 30.
  • the controller 17 can control the video display unit 18 selectively in accordance with a standard condition or mode in which the display is effected uniformly in one of the above-listed modes, and in accordance with a condition or mode which will be referred to hereinafter as the window mode and in which the screen can be sub-divided into two or more windows which can be displayed in different ways.
  • the refresh memory 23 has a capacity of 32 Kbytes and is capable of being written selectively under the control of the CPU 10 and an arbiter unit formed by another multiplexer 45, with the character codes, or in accordance with a map of the pixels of the graphics to be displayed.
  • the memory 23 is subdivided in accordance with words of 2 bytes, the first of which represents the alpha-numeric code of the character while the second byte represents the attributes of the character, that is to say characteristic particulars in accordance with which the character is to be displayed such as underlining, reverse, colour of background and character, light strength, etc.
  • the refresh memory 23 can contain up to a maximum of 16 pages of text in the former case and 8 pages in the latter case.
  • the output of the memory 23 is held at a latch 46.
  • the alpha-numeric code of the latch 46 is used to address a ROM 27 acting as a character generator while the bytes of the attributes are used for addressing an attribute decoder 28.
  • the outputs of the generator 27 and the decoder 28 therefore define the pixels to be displayed on the video display, for each scanning line.
  • the characters in the alpha-numeric mode 40 ⁇ 25 are produced in known manner by the same character generator 27, repeating each output bit during horizontal scanning under the control of the unit 19.
  • the memory 23 For recording graphic pixels, the memory 23 records a map of a bit for each pixel in the monochrome display mode and two bits for each pixel in the case of colour display. In that case the two bits can define four different colours for the pixel, In the case of high-­definition display, the entire memory 23 can thus refresh a single graphic page while in the normal-definition display mode, 16 Kbytes of memory 23 are sufficient to refresh a graphic page, whereby half of the memory 23 can be disregarded or can be used to record another graphic page.
  • the unit 19 then controls reading of the map of the memory 23 in accordance with the line raster sequence provided for control of the display 18.
  • the memory 23 (see Figure 4) is allocated between the addresses B8000 and BFFFF.
  • the memory 23 In the normal-definition graphic mode of 200 lines the memory 23 is divided into two 16 Kbyte halves which are connected together by means of a transceiver 47 ( Figure 2) and connected to the bus 20 by means of another transceiver 48.
  • Each half of the memory 23 contains a display page; in the first half odd lines 1,3,5 etc of the image are recorded at the addresses between B8000 and B9FFF (see Figure 4) while the even lines 2, 4, 6 etc of the image are recorded at the addresses between BA000 and BBFFF.
  • the lines are recorded as above, but the bits of each byte are coupled in pairs for selecting the colour, whereby each byte controls the display of four dots.
  • an ROM 29 (see Figure 2) forming the colour table is addressed by a background mixer unit 49, by a serialiser 31 for the output signals from another mixer unit 50 for the signals to be displayed, and the output signals of the attribute decoder 28, to determine the colours of the pixels to be displayed.
  • the mixer units 49 and 50 also receive the signals from the registers 21 by way of a multiplexer 51 and a latch 52 and the signals from the memory 23 by way of a further latch 53.
  • the ROM 29 comprises two separate colour tables or palettes which can be selected, as will be described hereinafter.
  • the palette 1 comprises the colours black, green, red and yellow, while the palette 2 comprises the colours grey, cyan, magenta and white.
  • the signals from the colour table 29 are passed to an interface 32 of the video display unit 18, which thus provides for control of the display of the content of the memory 23.
  • the display 18 may be formed by a video display for displaying monochrome images in the positive mode, that is to say, for displaying characters in black on a white background.
  • a video display for displaying monochrome images in the positive mode, that is to say, for displaying characters in black on a white background.
  • Such a display has a standard capacity of 640 ⁇ 640, whereby that number of pixels can be displayed in the graphic mode.
  • the alpha-numeric mode by virtue of the optical effect of expansion of the black pixels, the characters are traced out differently with respect to those of the negative display, so that the result is different from that obtained by the negative character with the attribute 'reverse'.
  • the alpha-numeric mode it can be conditioned by means of a known circuit to display 640 ⁇ 480 pixels.
  • the matrix of the character was selected as 8 ⁇ 15 whereby the format of the display is provided by 80 ⁇ 32 characters.
  • the positive characters in standard mode and in 8 ⁇ 15 mode are generated by a second character generating ROM 34, as will be described hereinafter.
  • the refresh RAM 23 will have a capacity of 36 Kbytes.
  • the output signals from the character generator 34 are passed by way of the table 29 to the serialiser 31 from which they issue in series to provide pilot control for the display 18 in a similar manner to that described above for the negative mono­chrome display.
  • An OR circuit permits alternative connection as between the two character generators 27 and 34 and the mixer unit 50.
  • control unit 19 conditions means included in the unit 44 to address the individual cells at the refresh memory 23, both for display in accordance with an alpha-numeric mode and for display in accordance with a graphic mode. It is thus possible to define any graphic window which has an integral number of cells and thus a number of columns and rows which is a multiple of those of the character matrix. In that case the multiplexer 45 applies to the addresses of the memory 23 an offset such that it appears to the CPU 10 to be allocated to the addresses A 8000-AFFF (see Figure 5). In the normal-definition graphic mode, the memory 23 is now divided into eight zones which constitute the eight scanning lines of the cells.
  • the first zone between the addresses A8000 and A87FF is addressed directly by the unit 19, while the other portions are addressed successively by way of a constant offset of 800 hexadecimal. Therefore the scanning lines of the screen are recorded in the memory 23 in the sequence indicated in following table II (see also Figure 5). That sequence comprises only the first 16 Kbytes of memory 23 and is repeated in a similar manner for the second 16 Kbytes of memory 23.
  • the entire memory 23 is divided into 16 zones which constitute the 16 scanning lines of the cells.
  • the sequences of recording in the memory 23 are set out in following table III:
  • the controller 17 further comprises an auxiliary read-write memory (RAM) 33 (see Figure 2) which is addressed by way of the interface 24 and the arbiter multiplexer 45.
  • the memory 33 is connected by way of a latch 54 to the multiplexer 26 and by way of a transceiver 55 to the bus 20.
  • the control unit 19 is capable of associating with each alpha-numeric code in the memory 23 and with each graphic recording cell in the same memory, a byte of the auxiliary memory 33 in which there is recorded a window descriptor code which defines the mode in which the corresponding cell is to be displayed.
  • the memory 33 has a capacity of 4 Kbytes and is allocated to the addresses A0000-A7FFF (see Figure 6) and can therefore contain two separate pages of the screen.
  • the auxiliary memory 39 is suitably compiled in each byte with the window descriptors coherent with the data recorded in the refresh memory 23.
  • the two memories 23 and 33 are accessible to the CPU 10 at any time without waiting for the retrace period, either in sequence or individually.
  • the descriptors are recorded on each occasion at the time of recording of the cell while in the second case it is possible to modify the content of a cell or the descriptor thereof, one independently of each other, while obviously respecting coherence in respect of the alpha-numeric or graphic modes.
  • the display mode is defined by the three lowest-­value bits 0, 1 and 2 which are referred to as D0, D1 and D2.
  • Table IV sets out decoding of those three bits of the window descriptor byte.
  • bits D3-D7 of the byte are used for the definition of colours in the graphic modes and for the definition of some attributes in the alpha-numeric modes, as will become apparent hereinafter.
  • the various units of the controller 17 are controlled by the group 21 of I/O registers, which comprises six registers 36-42 (see Figure 3), the bits of which give the signals indicative of the various parameters required by the display.
  • the bit 3 provides the signal ILAT which determines the intensity of all the colours while the bit 4 provides the signal ALTB which provides the intensity of the colours of the data to be displayed in the colour graphic modes.
  • the registers 39, 41 and 42 constitute three mode registers.
  • the signals of the status 1 and status 2 registers 36 and 37 and the mode 3 register 42 as well as the signal VIDE of mode 1 register 39 and the signal ABWF of mode 2 register 41 maintain their functions without alteration.
  • the other functions are controlled by the bits D3-D7 of the window descriptors.
  • the bits D3 and D4 of the window descriptors have the same function respectively as the signal BLIB of the mode 1 register 39 and the signal UNDE of the mode 2 register 41.
  • the bits D3-D7 respectively perform the same functions as the signals BLAT, GLAT, RALT, ILAT and ALTB of the colour register 38.
  • the mode of operation of the display controller 17 as described above is as follows:
  • a page is to be recorded, which appears on the monochrome display as formed by a strip 60 (see Figure 6) formed by three lines of alpha-numeric characters in the mode 80 ⁇ 25, a window 61 formed by 30 ⁇ 15 cells for a graphic image in accordance with the graphic mode of 640 ⁇ 400, a window 62 of 10 ⁇ 15 characters in the mode 40 ⁇ 25, a window 63 formed by 30 ⁇ 15 cells for another graphic image in accordance with the graphic mode of 640 ⁇ 200, and a strip 64 formed by seven rows of characters in the mode 80 ⁇ 25.
  • 240 words are recorded in the zone A800-A87FF in the refresh memory 23 (see Figure 5). Each word is formed by a byte of alpha-­numeric code and a byte of the associated attribute.
  • the unit 19 defines the address of only the first line in each cell in the zone A8000 - A8700 while the subsequent lines in the same cell are automatically addressed by adding the hexadecimal constant 800 to the above-indicated address.
  • the unit 19 defines the address of just the first line of each cell in the zone A8000 - A8700 while the subsequent lines of the same cells are automatically addressed by adding the hexadecimal constant 800 to the address.
  • associated with the first line of words of graphic cells are 30 bytes of window descriptors in the auxiliary memory 33.
  • the fourth row of cells therefore also requires 80 descriptors.
  • auxiliary memory 33 records a constant number of window descriptors, independently of the modes in which the individual windows are recorded.
  • the unit 19 sequentially addresses the words of the first memory zone 23. For each word associated with window descriptors which identify one of the alpha-numeric modes, the first byte is emitted as the address of the character generator 27 and the second byte is passed to the attribute decoder 28 during the operation of scanning all the elementary lines of the row of cells.
  • the unit 19 For each word in the first memory zone 23 associated with window descriptors which identify one of the graphic modes during the scanning of the successive elementary lines of the cell, the unit 19 addresses the word which is read in the sequence of memory zones 23 provided by the respective graphic mode.
  • the output of the character generator 27 or 34 and the attribute decoder 28 in the alpha-numeric modes and the output of the memory 23 in the graphic modes is passed to the mixer unit 50 which thus provides for mixing of the graphic and alpha-­numeric signals.
  • the output from the unit 50 by way of the serializer 31, arrives at the colour table 29 whose output provides control for the video 18 by way of the display interface 32.
  • the controller described may be the subject of various modifications and improvements without departing from the scope of the invention.
  • the refresh memory 23 may be formed by a group of memory levels in order to produce images with a better selection of colours, defining each pixel by means of a group of corresponding bits in the various memory levels.
  • the con­troller 17 may also be provided for controlling different video display units, for example a negative display unit and a positive display unit.
  • the latter may be provided only to operate in a standard mode, in which case the character generator 34 will not be connected to the refresh memory 23.
EP87310229A 1986-12-16 1987-11-19 Anzeigen-Steuereinrichtung für Datenverarbeitungsgeräte Ceased EP0272006A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT67932/86A IT1196844B (it) 1986-12-16 1986-12-16 Governo video per apparecchiature di informatica
IT6793286 1986-12-16

Publications (2)

Publication Number Publication Date
EP0272006A2 true EP0272006A2 (de) 1988-06-22
EP0272006A3 EP0272006A3 (de) 1989-10-18

Family

ID=11306461

Family Applications (1)

Application Number Title Priority Date Filing Date
EP87310229A Ceased EP0272006A3 (de) 1986-12-16 1987-11-19 Anzeigen-Steuereinrichtung für Datenverarbeitungsgeräte

Country Status (3)

Country Link
EP (1) EP0272006A3 (de)
JP (1) JPS63233425A (de)
IT (1) IT1196844B (de)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0071744A2 (de) * 1981-08-12 1983-02-16 International Business Machines Corporation Verfahren zur Bedienung einer Rechnereinrichtung zum Schreiben von Textzeichen auf eine graphische Darstellung
EP0153789A2 (de) * 1984-02-27 1985-09-04 Philips Electronics Uk Limited Adressierung von Zeichenspeichern für Datenanzeige
EP0175342A2 (de) * 1984-09-17 1986-03-26 Honeywell Bull Inc. Gemischte Darstellung von Strichzeichnungen und Texten in einem Kathodenstrahlanzeigesystem
WO1986005910A1 (en) * 1985-04-03 1986-10-09 British Telecommunications Public Limited Company Video display apparatus

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS594591B2 (ja) * 1979-06-11 1984-01-30 株式会社ハツコ− 地下構造物の管体貫通部防水構造

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0071744A2 (de) * 1981-08-12 1983-02-16 International Business Machines Corporation Verfahren zur Bedienung einer Rechnereinrichtung zum Schreiben von Textzeichen auf eine graphische Darstellung
EP0153789A2 (de) * 1984-02-27 1985-09-04 Philips Electronics Uk Limited Adressierung von Zeichenspeichern für Datenanzeige
EP0175342A2 (de) * 1984-09-17 1986-03-26 Honeywell Bull Inc. Gemischte Darstellung von Strichzeichnungen und Texten in einem Kathodenstrahlanzeigesystem
WO1986005910A1 (en) * 1985-04-03 1986-10-09 British Telecommunications Public Limited Company Video display apparatus

Also Published As

Publication number Publication date
IT1196844B (it) 1988-11-25
EP0272006A3 (de) 1989-10-18
IT8667932A0 (it) 1986-12-16
JPS63233425A (ja) 1988-09-29

Similar Documents

Publication Publication Date Title
US4686521A (en) Display apparatus with mixed alphanumeric and graphic image
US5089811A (en) Advanced video processor having a color palette
US4290063A (en) Video display terminal having means for altering data words
CA2021831C (en) Display system
US4642794A (en) Video update FIFO buffer
CA1104730A (en) Character graphics colour display system
EP0004554A2 (de) Anzeigevorrichtung nach Art eines Fernsehgeräts mit mehreren Layouts
US6134021A (en) Presentation graphics system for a color laser copier
US5086295A (en) Apparatus for increasing color and spatial resolutions of a raster graphics system
US4616220A (en) Graphics display comparator for multiple bit plane graphics controller
EP0215984B1 (de) Graphik-Anzeigegerät mit kombiniertem Bitpuffer und Zeichengraphikspeicherung
US4937565A (en) Character generator-based graphics apparatus
US6281876B1 (en) Method and apparatus for text image stretching
US4706076A (en) Apparatus for displaying images defined by a plurality of lines of data
EP0195163B1 (de) Videokonvertiergerät
EP0349145B1 (de) Attributgenerator für ein flaches Bildschirmanzeigegerät
US4642626A (en) Graphic display scan line blanking capability
US5317684A (en) Method of storing character data in a display device
EP0272006A2 (de) Anzeigen-Steuereinrichtung für Datenverarbeitungsgeräte
US5266933A (en) Method and apparatus for displaying a screen separator line
EP0189567B1 (de) Farbanzeigesystem
US4857909A (en) Image display apparatus
USRE30785E (en) Microcomputer terminal system
EP0102750A2 (de) Zeichensatzanzeigeeinrichtung
KR0175142B1 (ko) 정지화상 표시장치 및 그것에 이용되는 외부 메모리 카트리지

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): CH DE ES FR GB LI NL SE

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): CH DE ES FR GB LI NL SE

17P Request for examination filed

Effective date: 19900403

17Q First examination report despatched

Effective date: 19920626

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN REFUSED

18R Application refused

Effective date: 19940218

RIN1 Information on inventor provided before grant (corrected)

Inventor name: TOSI, PIERANGELO