Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/317—Testing of digital circuits
  • G01R31/3181—Functional testing
  • G01R31/319—Tester hardware, i.e. output processing circuits
  • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
  • G01R31/31922—Timing generation or clock distribution
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/317—Testing of digital circuits
  • G01R31/3181—Functional testing
  • G01R31/319—Tester hardware, i.e. output processing circuits
  • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
  • G01R31/31919—Storing and outputting test patterns
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/02—Digital function generators
  • G06F1/03—Digital function generators working, at least partly, by table look-up
  • G06F1/0321—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers
  • G06F1/0328—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers in which the phase increment is adjustable, e.g. by using an adder-accumulator
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
  • G06F1/14—Time supervision arrangements, e.g. real time clock
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus

Definitions

• the present invention relates to universal program ⁇ mable modules for providing timing and/or address regis ⁇ ter functions for a broad family of test instruments. More particularly, the invention relates to a microcom ⁇ puter programmable time base generator for counter tim ⁇ ers, arbitrary function generators, real time digiti ⁇ zers, and pin electronics stimulus response generators; and to an address register module useful for regulating the flow of data into and out of an instrument memory.
• a programmable apparatus useful as a counter/timer, time base gener ⁇ ator, and memory address control or register is pro ⁇ vided.
• the apparatus includes a clock input means for receiving a clock input signal and a computer input means for providing input from a computer.
• a processing means processes at least one of the clock input signal and the input from the computer to produce at least one output.
• a control means controls the processing means in accordance with further input from the computer to determine the output produced.
• An output selecting means selects at least one output to be provided for use externally of the apparatus.
• the output selecting means which includes at least one multiplexer, selects at least one output in response to additional input from the computer.
• the multiplexer has circuits useful for directly addressing a memory.
• the processing means includes a counter responsive to the clock input signal. Means for preloading the counter in accordance with the input from the computer are also provided. A register stores the count in the counter.
• the computer input means includes a bidirectional data means for receiving and transmitting data. It also includes an input data buffer for storing data to be loaded into the counter.
• the computer in ⁇ put means includes a command buffer or register for storing the further input from the computer.
• the registers and the counter provide outputs to the output selecting means.
• FIG. 1 is a block diagram of a universal programmable counter/timer an address register module according to the invention
• FIG. 2A is a schematic diagram of a portion of the output multiplexer of FIG. 1
• FIG. 2B % is a schematic diagram of an additional portion of the output multiplexer of FIG. 1
• FIG. 2C - is a schematic diagram of yet another portion of the output multiplexer of FIG. 1;
• FIG. 1 is a block diagram of a universal programmable counter/timer an address register module according to the invention
• FIG. 2A is a schematic diagram of a portion of the output multiplexer of FIG. 1
• FIG. 2B % is a schematic diagram of an additional portion of the output multiplexer of FIG. 1
• FIG. 1 is a block diagram of a universal programmable counter/timer an address register module according to the invention
• FIG. 2A is a schematic diagram
• FIG. 2D is a schematic diagram of the remaining portion of the output multiplexer of FIG. 1;
• FIG. 3 is a schematic diagram of the command buffer of FIG. 1;
• FIG. 4 is a schematic diagram of the input data buffer of FIG. 1;
• FIG. 5 is a schematic diagram of the primary counter of FIG. 1;
• FIG. 6 is a schematic diagram of the pointer latch and external trigger countrol of FIG. 1;
• FIG. 7A is a schematic diagram of a portion of the prescaler and control of FIG. 1;
• FIG. 7B is a schematic diagram of the remainder of the prescaler and control of FIG. 1;
• FIG. 8 is a schematic diagram of the input controls portion of the input and clock control of FIG. 1;
• FIG. 9 is a schematic diagram of the clock controls portion of the input and clock control of FIG.
• FIG. 10 is a block diagram of a counter utilizing three of the modules of FIG. 1;
• FIG. 11 is a block diagram of an arbitrary function generator utilizing three of the modules of FIG. 1;
• FIG. 12 is a block diagram of a real time digitizer utilizing three of the modules of FIG. 1; and
• FIG. 13 is a block diagram of a digital word generator utilizing two the modules of FIG. 1.
• the apparatus of the present invention is prefer ⁇ ably constructed by depositing two layers of metalliza ⁇ tion on a gate array of the type commonly available from semiconductor manufacturers such as Applied Micro Cir- cuits Corporation of San Diego, California.
• the result ⁇ ing semiconductor chip may be packaged as a 100 pin grid array. While occupying an area of only 1.25 inches by 1.25 inches on a circuit board and having a height of approximately 0.2 inches, such design and packaging per ⁇ mits the module of the present invention, in applica ⁇ tions where the circuitry thereon is fully utilized, to replace approximately 60 to 70 conventional SSI/MSI in ⁇ tegrated circuits.
• BUS DESIGNATION address bus 22 ADDR internal data bus 36 DBUS programming bus 45 MBUS load bus 55 LBUS count bus 60 CBUS latch bus 64 PBUS status bus 72 SBUS
• interconnec- c tions are provided for various functions.
• An address function provided by data on a 12 bit address bus 22 permits the microcomputer to designate a certain portion of memory for use with apparatus 20.
• the data on ad- 0 dress bus 22 is provided to input and clock control 24 and to a 8:1 multiplexer 26 of output multiplexer 28 (FIGS. 2A, 2B, 2C and 2D).
• the three least significant bits (binary 0, 1 and 2) of address bus 22 are used to designate which of three internal registers of apparatus 20 are to be loaded or read, as more fully described below.
• Data from the microcomputer memory designated may be supplied to apparatus 20, or data from apparatus 20 may be provided to the memory by means of a bidirec ⁇ tional tristate data bus 30 which may be of a conven ⁇ tional 8 bit type, or of 16 bits or more for greater precision.
• a tristate bidirectional receiver/driver circuit 32 (FIGS. 2A, 2B, 2C and 2D) terminates the end of bus 30 associated with apparatus 20.
• Data from the output of multiplexer 26 may be provided to the input of receiver/driver circuit 32 by internal bus 34. This data is then placed on bidirectional data bus 30 to be provided to the microcomputer. Data appearing on bus 30 is routed to the 8 bits of internal data bus 36 to be distributed to selected registers of apparatus 20.
• receiver/driver circuit 32 The direction of operation of receiver/driver circuit 32 is determined by a control signal from input and clock con- trol 24 provided on bus 38.
• Bus 38 also provides con ⁇ trol signals to 8:1 multiplexer 26 and 2:1 multiplexer 40 (FIGS. 2A, 2B, 2C and 2D) of output multiplexer 28.
• Data on internal data bus 36 is provided to command buffer 42, input data buffer 44 and control register 46 of prescaler and control 48 (FIGS. 7A, 7B) .
• control bus 50 which provides inputs to input and clock control 24 for a chip select function, a clear function for an unconditional clear for initialization of registers and counters when power is turned on, read and write functions, and other func- tions as more fully described below. It is also neces ⁇ sary that timing functions on apparatus 20 be synchro ⁇ nized by an external clock (not shown).
• an ECL compatible input terminal is provided for a 100 MHz clock signal supplied as an input to prescaler 49 of prescaler and control 48 and a TTL input terminal is provided for lower frequencies as more fully described below.
• Prescaler 49 is programmed to provide various time bases by signals on a programming bus 45 from con ⁇ trol register 46 in accordance with command signals from input and clock control 24 appearing on bus 52.
• Bus 52 also supplies command signals from input and clock con ⁇ trol 24 to command buffer 42, input data buffer 44, and a primary counter 54.
• Pulses from prescaler 49 are con ⁇ ducted to input and clock control 24 by line 51.
• Data from apparatus 20 is provided directly to the memory of the microcomputer (without the need to do a block transfer of data) by means of a 12 bit ECL output bus 56 or a 12 bit TTL output bus 58, with the data thereon provided by outputs of 2:1 multiplexer 40.
• Mul ⁇ tiplexer 40 can provide, on buses 56 and 58, data from a first group of its inputs connected to address bus 22 or from a second group of its inputs connected to a count bus 60 having data thereon corresponding to the count of primary counter 54.
• Primary counter 54 may be preloaded with data from input data buffer 44 carried by load bus 55.
• Any one of eight different inputs to 8:1 multi- plexer 26 can be placed on bidirectional data bus 30 by way of bus 34 to the tristate receiver/driver circuit 32 under the direction of control signals on bus 38.
• the first two inputs of 8:1 multiplexer 26 are connected to ,_ the same buses as the inputs of 2:1 multiplexer 40; that is count bus 60 and address bus 22.
• a third input to multiplexer 26 is provided by the output of a pointer latch 62 by way of a latch bus 64.
• Pointer latch 62 (FIG. 6) stores the count from primar ⁇ - * counter 54 provided by count bus 60 when directed to do so by a signal on line 66 from external trigger control 68. This signal on line 66 is synchronized to clock by a clock pulse provided to external trigger control 68 on line 70 from input and clock control 24.
• a fourth input to multiplexer 26 is the data on a status bus 72 originating at command buffer 42.
• the data on status bus 72 is also supplied to input and clock control 24. This data is representative of the state of certain selected signals, some of which are not necessary to the operation of apparatus 20, but serve to facilitate a determination, made by automatic test equipment, as to whether apparatus 20 is functioning properly.
• Counter state bus 74 Another input to multiplexer 26 is provided by a counter state bus 74 which originates at primary counter l 54 and provides data indicative of the state of counter 54.
• Counter state bus 74 also provides an input to in ⁇ put and clock control 24.
• Bus 74 is also lead out ex-
• An additional input to multiplexer 26 is data from programming bus 45 as noted above, and as more fully 0 described below.
• a clock pulse output line 78 provides clock pulses and other outputs from input and clock control 24 exter ⁇ nally of apparatus 20 as more fully described below. 5
• Each bit of address bus 22 is terminated in one of receivers 0 80A to 80L.
• the output of each receiver 80A to 80L is supplied to a respective driver 81A to 81L.
• the output of each driver 81A to 81L is supplied to a respective first input of respective multiplexers 40A to 40L which 5 together constitute 2:1 multiplexer 40 (FIG. 1).
• the respective second inputs of multiplexers 40A to 40L are connected to corresponding bits of count bus 60.
• the selector input S of each of multiplexers 40A to 40L is 0 connected to a line corresponding to bit 3A of status bus 72 (SBUS3).
• the state of said bit of status bus 72 determines whether the contents of address bus 22 or that of county bus 60 is provided by the collective outputs of multiplexers 40A to 40L.
• the inputs of respective. ECL drivers 82A to 82L are each provided with the respective output of respective multiplexers 40A to 40L.
• IAO inverter/driver
• An additional inverter/driver 88E' (FIG. ⁇ 2B) is connected to the inverted output of input buffer 80E thus providing an output IA2N (or A2; that is, the logical opposite of A2).
• Outputs IAO, IA1, IA2 and IA2N are used internally for register selection as noted 5 above, and as more fully described below.
• a series of 16 4:1 multiplexers 26A to 26H and 26A 1 to 26H' (FIGS. 2A, 2B, 2C and 2D) collectively consti ⁇ tute 8:1 multiplexer 26 (FIG. 1).
• Multiplexers 26A to ° 26H and 26A' to 26H' each have four data inputs 10, II, 12 and 13. The presence of logic high or low on data select inputs SO and SI determines which of the four inputs 10, II, 12 and 13 is presented at data output Y. 5
• the enable inputs of a first group of mul ⁇ tiplexers 26A to 26H are connected so as to assume the logic states of IA2.
• the enable in ⁇ puts of a second group of multiplexers 26A' to 26H' are 0 connected to IA2N.
• the data outputs Y of each pair of multiplexers 26A and 26A' , 26B and 26B', etc. are con-
• OR gates 90A to 90F are simple wire OR gates, thus enhancing speed of operation.
• the respective out ⁇ puts of OR gates 90A to 90H are connected to respective 0 inputs of input buffers 92A to 92H of respective receiver/driver 32A to 32K which collectively constitute receiver/driver circuit 32.
• the outputs of buffers 92A to 9211 are connected to respective drivers 94A to 94H of receiver/drivers 32A to
• Drivers 94A to 94H each have a control input.
• drivers 94A to 94H present data on bidi- rection tristate data bus 30.
• the outputs of drivers 94A to 94H are also supplied to respective receivers 96A to 96H of receiver/drivers 5 32.
• the outputs of receivers 96A to 96H are in turn supplied to the inputs of respective drivers 98A to 98H.
• the outputs of drivers 98A to 98H provide the 8 tits of data on internal data bus 36.
• drivers 94A to 94H are enabled by OUTEN the data supplied to bidirectional tristate bus 30 and internal data bus 36 is that from OR gates 90A to 90H originating at the output of the first group of multiplexers 26A to 26H or the data originating at the output of the second group of multiplexers 26A' to 26H'.
• drivers 94A to 94H are not enabled by OUTEN, the tristate output of drivers 94A to 94H are in an open condition. Data on bidirectional tristate data bus 30 then appears at the inputs of receivers 9SA to
• drivers S1A to 81L which represent the 12 bits of address bus 22, and are applied to the 10 input of one of multiplexers 26A to 26M and 26A 1 to
• the least significant bit, or zero bit, A0 is applied to the 10 input of tnul- tiplexer 26A.
• the least significant bits of coust bus 60, latch bus 64 and status bus 72 are applied to inputs II, 12 and 13, respectively of multiplexer 26A.
• the eighth bit, A8 of address bus 22 is applied to irqpfut 10 of multiplexer 26A' by driver 8IB.
• the eighth bits of count bus 80, latch bus 64 and status bus 72 are applied to input II, 12, and 13, respectively, of multiplexer
• the second least significant bit, or 1 bit, Al of address register 22 is applied to the 10 input of srulti- plexer 26B by driver 81C.
• Corresponding bits of count bus 60, latch bus 64 and status bus 72 are applied to inputs II, 12 and 13, respectively of multiplexer 26B.
• the ninth bit of address bus 22 is applied to the input of multiplexer 26B' by driver 81D.
• Corresponding bits of count bus 60, latch bus 64 and status bus 72 are ap ⁇ plied to inputs II, 12 and 13, respectively of multi ⁇ plexer 26B 1 .
• Select inputs SO of multiplexer 26A, 26A', 26B and 26B' are connected to the output of driver 81A while select inputs SI of multiplexer 26A, 26A', 26B and 26B' are connected to the output of driver 81C.
• the logic values of bits AO and Al of address bus 22 deter ⁇ mine which input to multiplexer 26A, 26A' , 26B and 26B' is present at the respective Y outputs.
• bits AO and Al select which corresponding bit's logic value of four buses (address bus 20, count bus 60, latch bus 64 or status bus 72) is presented at the output of multiplexers 26A, 26A* , 26B and 26B 1 .
• logic values of IA2 and IA2N deter ⁇ mine which byte the bit is actually selected from.
• the logic value of either the least significant bit (0 bit) or the eighth bit of the selected bus is presented at the output of driver 94A to become the least significant bit of internal data bus 36 and the least significant bit of bidirectional tristate data bus 30 if OUTEN is at the appropriate logic level.
• the logic value of the 1 bit or the 9 bit of the selected bus is presented at the output of driver 94B to become the value of the 1 bit of internal data bus 36 and of tristate data bus 30 if OUTEN is at the appropriate logic level.
• bits 2 of the same four buses are supplied as inputs to multiplexer 26C, while the 10 or A bits are supplied as inputs to multiplexer 26C.
• the three bits of the same buses are supplied as inputs to multiplexer 26D while the 11 or B bits are supplied to multiplexer 26D'.
• Select inputs SO of multiplexers 26C, 26C, 26D and 26D' are controlled by the value of IAO, while select inputs SI of said multiplexers are controlled by the value of IA1.
• the logic value of either the 2 or 10 bit appears as bit 2 of internal data bus 36 (and if required as bit 2 of bus 30).
• the logic value of either the third bit or the eleventh bit appears as bit 3 of internal data bus 36.
• bit 4 inputs of address bus 22, count bus 60, latch bus 64 and status bus 72 are
• the 0 bit of programming bus 45 is supplied to the 10 input to multiplexer 26E'.
• the 12 bit or C bit of count bus 60 is supplied to the II input of multiplexer 26E'.
• the output of a trigger flip-flop (FIG. 6) is supplied to the 12 input of multiplexer 26E', while the 13 input is connected to ground.
• bit 5 lines of address bus 22, count bus 60, latch bus 64 and status bus 72 are connected to inputs 10, 12, 12 and 13, respectively, of multiplexer 26F.
• the 1 bit of programming bus 45 is supplied to the 10 input of multiplexer 26F' .
• Bit 13 or D of count bus 60 is supplied to the II input of multiplexer 26F'.
• the end of count output of a flip flop associated with pri ⁇ mary counter 54 (FIG. 5) is supplied to the 12 input of multiplexer 26F', while the 13 input is connected to ground.
• Select inputs SO of multiplexers 26E, 26E', 26F and 26F' are controlled by the logic value of IAO, while select inputs SI are controlled by the logic level of IA1.
• bit 6 of address bus 22, count bus 60, latch bus 64 and status bus 72 are sup ⁇ plied to the 10, II, 12 and 13 inputs, respectively, of multiplexer 26G.
• Bit 2 of programming bus 45 is sup- ⁇ j _ plied to the 10 input of multiplexer 26G 1 .
• Bit 15 or E of count bus 60 is supplied to the II input of multi ⁇ plexer 26G'.
• the logical inverse of the top count out- r- put of primary counter 54 (FIG. 5) is applied to the 12 input of flip flop 26G', while the 13 input is grounded.
• bit 7 lines of address bus 22, count bus 60, latch bus 64 and status bus 72 are connected to the 10, 10 II, 12 and 13 inputs, respectively, of multiplexer 26H.
• Bit 3 of progra ⁇ ing bus 45 is connected to input 10 of multiplexer 26H and bit 16 or F of count bus 60 is con ⁇ nected to the II input.
• the 12 input is connected to
• 26H 1 are controlled by the logic level of IAO, while select lines SI are controlled by the logic level of 20
• IA1 Operation, based on the values of IA2 and IA2N is as described above.
• command buffer 42 has a series p r of flip flops 100A to 100H which each receive respec ⁇ tively, at the D inputs thereof, data from respective bits 0 to 7 of internal data bus 36.
• Flip flops 100A to 100H are all reset by a signal RESET 4 from input and
• clock control 24 (FIG. 8) and are clocked by a signal CPMODL from input and clock control 24 (FIG. 8) by way of gates 102A to 102H, respectively.
• the Q outputs of flip flops 100A to 100H are applied to status bus 72 as
• the QN (i.e. Q) outputs of flip flops 100A, 100B, 100E, 100F, 100G and 100H are also available for use throughout apparatus 20'.
• the QN output of flip flcp 100D is provided as an input to OR gate 104.
• the second and third inputs of gate 104 are grounded.
• the - > output of gate 104 is provided to the input of a driver 106 which generates the signal SBUS3B which is logically identical to SBUS3A. Two outputs are provided, instead of one, for additional fan out capability. 0
• Command buffer 42 also has four flip flops 100A' to 100D 1 which each receive, respectively, at the D input thereof, data from respective bits 0 to 3 of internal data bus 36.
• Flip flops 100A' to 100H 1 are all reset by 5 a signal RESET 4 from input and clock control 24 (FIG. 8) and are clocked by a signal CPMODH from input and clock control 24 (FIG. 8) by way of gates 102A' to 0 102D* , respectively.
• the Q outputs of flip flops 100A' to 100D' are applied to status bus 72 as bit 8 to bit 11.
• the QN outputs are available as well.
• the signifi ⁇ cance of the CPMODL and CPMODH will be discussed below 5 with respect to FIG. 8.
• the programming of apparatus 20 is accomplished via status bus 72, because data thereon, used directly, and distributed by internal data bus 36, controls operation 0 of the various blocks of FIG. 1.
• the following table indicates how the various bits of status bus 72 are utilized.
• Test counter 54B 5 A Test counter 54C 5 B Test counter 54D 5
• input data buffer 44 is com ⁇ prised of eight pairs of flip flops 108A, 108A' to 108H, 108H 1 .
• Bits 0 to 7 of internal data bus 36 are con ⁇ nected, respectively, to the D inputs of said pairs of flip flops.
• Flip flops 108A to 108H are reset by a signal RESET 1, while flip flops 10SA' to 108H' are re ⁇ set by signal RESET 2 from input and clock control 24 (FIG. 8).
• Flip flops 108A to 108H are clocked by a sig- nal CPDATL (by way of gates 110A to 110H), while flip flops 108A' to 108H * are clocked by a signal CPDATH (by way of gates 110A' to 110H'), which originate in input and clock control 24 (FIG. 8) and are discussed more fully below.
• the Q outputs of flip flops 108A to 108H appear as bits 0 to 7 on load bus 55, while the Q outputs of flip flops 108A' to 108H' appear as bits 8 to F of load bus 55.
• primary counter 54 is com ⁇ prised of four, four bit up counters 54A to 54D. Bits 0 to 3 of load bus 55 are connected respectively to the DO to D3 inputs of counter 54A. Bits 4 to 7 are connected to the corresponding inputs of counter 54B, bits 8 to 11 to those of counter 54C and bits 12 to 15 to those of counter 54D. Thus, counter 54 is a 16 bit up counter which can be preload with the data on load bus 55.
• the QON to Q3N outputs of counter 54A are the source of bits 0 to 3 of count bus 60.
• the QON to Q3N outputs of counter 54B are the source of bits 4 to 7 of count bus 60.
• the QON to Q3N outputs of counter 54C are the source of bits 8 to B, while the corresponding out ⁇ puts of counter 54D are the source of bits C to F of count bus 60.
• Counters 54A and 54B are clocked by signal CPC1, while counters 54C and 54D are clocked by signal CPC2, both from input and clock control 24 (FIG. 9).
• An external enable signal ENT (provided by a line of control bus 50) , which is active on logic low, is provided to an input of an ECL comparator 112.
• the out ⁇ put of comparator 112 is provided as an input to driver 114.
• the output of driver 114 is in turn provided as a first input to NAMD gate 116.
• a second input of NAND gate 116 is connected to the bit
• a third input of gate 116 is grounded.
• the output of gate 116 is connected to a first input of OR gate 118.
• the second input of OR gate 118 is connected to the output of a KAND gate 120.
• Two inputs of NAND gate 120 are grounded.
• the third input of gate 120 is connected to the logical opposite of SBUS8, SEUS8N.
• a sec- t - ond input of gate 122 is connected to ground.
• the third input is connected to SBUS9, i.e., bit 10 of status bus 72.
• the output of NAND gate 122 is connected to one input of OR gate 124.
• the second input of OR gate 124 0 is connected to the output of NAND gate 126.
• Two inputs of NAND gate 126 are grounded, while a third input is connected to SBUS9N.
• the output of OR gate 124 is con ⁇ nected to the count enable input CE of counter 54B. 5
• counter 54B counts pulses of CPCl when SBUS9N is at a logic low, or when the TCN output of coLinter 54A is low, indicating counter 54 is at full count and SBUS9 is low. This permits independent testing of counter 54B or 0 testing in conjunction with counter 54A.
• Bit 11 of status bus 72, SBUSA is connected to one input of a NAND gate 128.
• the other two inputs are con ⁇ nected, respectively, to the TC outputs of counter 54A 5 and 54B.
• the output of NAND gate 128 is connected to one input of an OR gate 130.
• the other input of OR gate 130 is connected to the output of a NAND gate 132.
• Two 0 inputs of NAND gate 132 are grounded, while the third input is connected to SBUSAN.
• the output of OR gate 130 is connected to the count enable input of counter 54C.
• the TCN outputs of counters 54A and 54B are also supplied to the first two inputs of NOR gate 134.
• the other two inputs of an EXCLUSIVE NOR gate 134 are grounded.
• the output of KOR gate 134 is connected to one input of NAND gate 136.
• a second input of NAND gate 136 is connected to the TCN output of counter 54C.
• the third input of NAND gate 136 is connected to SBUSB, the bit 12 line of status bus 72.
• OR gate 138 is connected to the input of OR gate 138.
• the other input of OR gate 138 is connected to the output of a
• NAND gate 140 Two inputs of NAND gate 140 are ground ⁇ ed, while a third input is connected to SBUSN.
• the out ⁇ put of OR gate 138 is connected to the count enable in- & put CE of counter 54D.
• counter 54D counts pulses of CPC2 when SBUSBN is low, or when the TCN output of counters 54A, 54B and 54C and SBUSB are all low. Coun- ter 5 D can thus be tested independently, or in conjunc ⁇ tion with counters 54A, 54B and 54C.
• the testing arrangement described above permits a full test of counter 54 with only 65 clock pulses.
• the Q1N, Q2N and Q3N outputs of counter 54A are connected, respectively, to the three inverting inputs of an ASD gate 142.
• the QON output of counter 54A is connected to one input of an OR gate 144.
• the other two inputs of gate 144 are connected to ground.
• the non-inverted output of gate 142 is high when counter 54A has a count therein of 14, or one less than its top count.
• the inverted output YN of gate 142 is connected to an input of inverting OR gate 146.
• the other three in ⁇ puts of gate 146 are connected to respective TCN outputs of counters 54B, 54C and 54D.
• the inverted output of TCNTLl of gate 146 is thus high when counter 54A is at count 14 and counters 54B, 54C and 54D are at count 15.
• TCNTLl is an internal pre-top count signal which is used to provide an indication to other components of appara ⁇ tus 20 that there is only one count to go before counter 54 is at a top count condition.
• TCNTLl is connected to one input of OR gate 148.
• the other input of OR gate 148 is grounded.
• OR gate 148 The outputs of OR gate 148 are con ⁇ nected to the input of an output cell or driver 150, which provides a pre-top count output PR.ETC, externally of apparatus 20 when TCNTLl makes a transition from low to high.
• the TCN outputs of counters 54A to 54D are provided to respective inputs of inverting OR gates 152 and 154.
• the inverted output of gate 152 which is high only when all of counters 54A to 54D are at a top count of.15, is connected to an input of OR gate 156.
• the other input of OR gate 156 is grounded.
• the output of gate 156 is connected to a driver 158 which provides an output TCI externally of apparatus 20.
• the output of gate 152 is also connected to one input of OR gate 160.
• OR gate 160 The other input of OR gate 160 is connected to ground.
• the in- verted output of OR gate 160 is connected to the input of driver 162 which provides a low output at TC2N when counter 54 is at top count.
• the output of gate 152 is also available as a sig ⁇ nal TCNT for use elsewhere in apparatus 20. Further, said output is applied as an output 10 to a 2:1 multi ⁇ plexer 164.
• the output of multiplexer 164 is connected to the D input of a flip flop 166.
• the Q output of flip flop 166 is connected to the II and select input SI of multiplexer 164.
• the clock input of flip flop 166 is connected to the output of an OR gate 168.
• OR gate 168 is grounded, while another input is con ⁇ nected to CPC2.
• the Q output of flip flop 166 is high when reset, which causes multiplexer 166 to provide a logic high signal to input D of flip flop 166.
• the output of flip flop 166 is also connected to one input of an OR gate 170.
• the other input of OR gate 170 is connected to ground.
• the inverted output of OR j- gate 170 is connected to an output cell or driver 172.
• the output of OR gate 154 is connected to one input of a NAND gate 174.
• Another input of NAND gate 174 is connected to ground.
• the third input of NAND gate 174 is connected to the bit 5 line SEUS4 of status bus 72.
• NAND gate 174 is connected to one input of an OR gate 176.
• the other input or OR gate 176 is con ⁇ nected to the output of a NAND gate 178.
• a first input of NAND gate 178 is grounded and a second input is con ⁇ 0 nected to SBUS4N.
• the third input of NAND gate 178 is connected to a line EXLD originating in input and con ⁇ trol 24 (FIG. 9).
• c - The output of OR gate 176 is connected to the pre ⁇ load enable input of counters 54A to 54D. This output assumes a high state when counter 54 is at top count and SBUS4 is low, or when SBTJS4N and EXLD are both at logic 0 low.
• data from counter 54 corre- sponding to bits 0 to B of count bus 60 is provided to the D inputs of a series of flip flops 180A to 180L of pointer latch 62.
• the Q outputs of flip flops 180A to 180L are connected to bits 0 to B of latch bus 64.
• An external trigger is supplied by a line of control bus 50 to an ECL comparator 182 of external trigger control 68 (FIG. 6).
• the output of comparator 182 is in turn connected to a driver 184.
• the non- inverted output of driver 184 is connected to a first input of a NAND gate 186.
• a second input of NAND gate 186 is connected to SBUS5N.
• the third input of NAND gate 186 is connected to SBUS6N which serves as an ex ⁇ ternal trigger enable signal.
• NAND gate 186 The outputs of NAND gate 186 is connected to one input of an OR gate 188.
• the other input of OR gate 188 is connected to the output of a NAND gate 190.
• a first input of NAND gate 190 is connected to the inverted out ⁇ put of driver 184, a second input to SBUS5, and the third input to SBUS6N.
• the output of OR gate 188 goes high when SBUS6N, the non-inverted output of driver 184 and SBUS5N are all low. These conditions are indicative of triggering on the negative slope of the signal ap ⁇ plied to comparator 182.
• the output of OR gate 188 is also high when SBUS6N, SBUS5 and the inverted output of ECL comparator 184 are all low. These conditions are . indicative of triggering on the positive slope of the signal applied to comparator 182.
• OR gate 188 The output of OR gate 188 is supplied to one input ⁇ - of OR gate 192. The other input thereof is grounded.
• the output of OR gate 192 clocks flip flop 194.
• the D input of flip flop 194 is connected to SBUS6.
• SBUS6N provides an enable external trigger signal by 0 being at logic low
• SBUS6 provides a logic high signal which is asynchronously clocked to the Q output of flip flop 194 when the external signal applied to comparator 182 causes a change in the state thereof. 5
• the Q output of flip flcp 194 is applied to the D input of flip flop 196.
• the clock input of flip flop 196 is connected to the output of an OR gate 198.
• a first input of OR gate 198 is grounded and the second 0 input is connected by line 70 (FIG. 1) to CPCl, the clock used by primary counter 54 and originating in in ⁇ put and clock control 24 (FIG. 9).
• Flip flop 196 is 5 thus synchronously clocked, on the pulse of CPCl occur ⁇ ring after the Q output of flip flop 194 goes high.
• the state of the Q output TRIGFF of flip flop 196 is thus indicative of an external trigger of selected slope hav- 0 i n g occurred and been synchronized to the pulse of CPCl immediately after the occurrence of said external trig ⁇ ger.
• the QN output of flip flop 196 is connected to an 5 input of an OR gate 198.
• the other two inputs of gate 198 are grounded.
• the output of gate 198 is connected to the input of a driver 200.
• Driver 200 has sufficient fan out capability so that the inverted output thereof, transmitted over line 66 (FIG. 1) , can drive the first input of each of a series of OR gates 202A to 202L.
• the second input of each of OR gates 2C2A to 202L is ground ⁇ ed.
• a reset signal RESET 3 from input and clock control 24 (FIG. 8) resets flip flops 180A to 180L.
• prescaler 49 pro ⁇ grammed by control register 46, avoids this difficulty.
• Primary counter 54 may operate at a lower count rate, while prescaler 49 operates at 100 MHz.
• control register 46 is comprised of four flip flops 204A to 204D having D inputs which are connected to bits 3 to 0, respectively, of internal data bus 36.
• Flip flops 204A to 204D are reset by a signal RESET 1 and are clocked by a signal CPPRE from input and control 24 (FIG. 8) by way of OR gates 206A to 206B.
• the Q outputs of flip flops 204A to 204D are the origin of bits 3 to 0, respectively, of programming bus 45.
• the QN outputs of flip flops 204A to 204D are provided, respectively, to the inputs of inverted OR gates 208A to 208D of prescaler 49.
• a four bit presettable binary counter of a type well known in the art, is comprised of inverted OR gates 208A to 208D, 210A to 210D, 212A to 212C, 214A, 214B, wire OR gates 216A to 216D, and flip flops 218A to 218D. This ar- rangement is designed for high speed counting.
• Flip flops 218A to 218D are clocked by the 100 MHz system clock CP100 (FIG. 9) by way of CR gates 220A to 220D, respectively.
• the QN outputs of flip flops 204A to 204D of control register 46 provide preset inputs for flip flops 218A to 218D.
• prescaler 49 can generate time bases of predetermined width depending on the bina ⁇ ry number loaded into control register 46.
• Prescaler 49 functions as a divide by N counter, where N is the one's compliment of the bin?ry number in control register 46.
• the ON outputs of flip flops 218C and 218D, desig ⁇ nated as CNT1N and CNT0N are each provided as an input to inverted OR gates 222 and 224 (FIG. 7A) .
• the QN outputs of flip flops 218A and 218B are also each provided as an input to inverted OR. gates 222 and 224.
• prescaler 49 When the QN outputs of flip flops 218A to 218D are all low, prescaler 49 is at top count, and the inverted out ⁇ put of gate 222 is high, providing a signal COUNTN.
• the non-inverted output of gate 224 is low, providing a sig ⁇ nal LOADN (FIG. 7A) .
• COUNTN is supplied to one input of gate 210C and to one input of gate 210D.
• LOADN is sup ⁇ plied to a second input of gate 21OC and an input of gate 208D (FIG. 7B).
• COUNTN or LOADN are the outputs of prescaler 49 used as a tine base or clock. The occur ⁇ rence of COUNTN may be the event which causes loading of the number stored in control register 46 into prescaler 49.
• Flip flops 218A to 218D are reset by a signal RESET 6 from input and clock control 24 (FIG. 8).
• prescaler 49 can produce pulses having time bases of 10 to 160 nsec in increments of 10 nsec. Time bases of 170, 180 and 190 nsec are not produced. However, the output of prescaler 49 may be provided to the input of primary counter 54 to produce time bases of from 20 to at least 20 milli ⁇ seconds (2 x 160 ns) in increments of 20 nsec, as described below.
• the input control section of input and clock con ⁇ trol 24 is shown in FIG 8.
• a base address specifying which of several input or output ports is to be opera- tively associated with the microcomputer at a given time is decoded therein, in a manner well known in the art.
• the microcomputer provides a logic low level by way of control bus 50 to external chip select input CSN.
• a receiver 226 converts from TTL to ECL and has an out ⁇ put connected to the input of a driver-228.
• the non- inverted output of driver 228 is connected to one input of an OR gate 230.
• the output of OR gate 230 is con ⁇ nected to the input of a tri-state enable driver 232.
• Driver 232 provides at its output the output enable sig ⁇ nal OUTEN used to enable drivers 94A to 94H (FIG. 2A, 2B, 2C and 2D).
• _ Control bus 50 also provides a read signal RDN to receiver 234 which in turn drives a driver 236.
• the output of driver 236 is connected to the second input of
• ⁇ RDN is at logic low, but a signal WRN, supplied by the microcomputer to a receiver 238 by a line of control bus
• the output of receiver 238 is connected to the input of a driver 240.
• the output of 20 driver 240 is connected to one input of each of gates
• P _. inverted outputs respectively.
• the output of driver 228 is connected to a second input of each of gates 242 and 244.
• a third input of each of gates 242 and 244 is connected to ground.
• the fourth input of gate 242 is
• gate 242 is connected to internal address line IA2N.
• the fourth input of gate 242 is connected to internal address line IA2N.
• the non-inverted output of gate 242 is connected to the inverting enable input of a decoder 246.
• FIG. 9 1 SELF TEST CLOCK PULSE
• a microcomputer software ordered reset of all reg ⁇ isters is accomplished, as noted above, when the Y2 out ⁇ put of decoder 248 is applied to a first input of each of OR gates 250A to 250H.
• the output of each of OR gates 250A to 250H is connected to the input of a.re ⁇ spective driver 252A to 252H which produce, at the re ⁇ spective outputs thereof, RESET 1 to RESET 6, RESET 8 and RESET 9.
• a microcomputer software ordered reset of all non ⁇ programmable registers is accomplished, as noted above, when the Y3 output of decoder 248 is applied to a second input of each of OR gates 250C, 250F, 250G and 250H.
• the corresponding input of OR gates 250A, 250B, 250D and 25OE are grounded.
• RESET 3, RESET 6, RESET 8 and RESET 9 are driven to logic high, resetting, respec ⁇ tively, only pointer latch 62, prescaler 49 and primary counter 54.
• the registers having loaded values, i.e., input data buffer 44, control register 46, and command buffer 42 are not disturbed, and the values loaded therein are retained for use in subsequent operations.
• An external clear input CLEAR is provided, on a line of control bus 50, to a receiver 254.
• the output of receiver 254 is connected to a driver 256.
• the inverted output of driver 256 is connected to the third input of OR. gates 250A to 250H, thus providing a reset of all registers when CLEAR is at logic low.
• an ECL clock CPECL or its log ⁇ ical opposite CPECLN are supplied to the clock control portion of input and clock control 24 by lines of con ⁇ trol bus 50.
• a receiver 258 processes CPECL and sup ⁇ plies an output to the non-inverting input of a driver 260.
• a receiver 262 process CPECLN and supplies a sig ⁇ nal to the inverting input of driver 260.
• the inverted output of driver 260 is connected to the B input of a NAND gate 264.
• the A input of NAND gate 264 is con ⁇ nected to SBUS1.
• the output of NAND gate 264 is con- nected to the input of a driver 266.
• the 100 MHz ECL clock appears at the output of driver 266 and produces the output CPiOO used as an input for prescaler 49 (FIGS. 7A and 7B) only if SBUS1 is at a high logic level.
• the output EOCFF of end of count flip flop .166 (FIG. 5) is provided to the A input of an A_ND gate 268. EOCFF is also provided to a first input of an OR gate 270. The second input of OR gate 270 is grounded. The inverted output of OR gate 270 is connected to the input of an output cell or driver 272, which provides an out ⁇ put EOCN external of apparatus 20.
• the B input of AND gate 268 is connected to SBUS4. A logic high output is produced by gate 268 only when counters 54A to 54D of primary counter 54 are at an end of count condition.
• the output of AND gate 268 is con ⁇ nected to a first input of an AND gate 274 having three inverting inputs.
• a second input of gate 274 is con ⁇ nected to SBUS1N.
• the third input of gate 274 is con- nected to the inverted output of an AND gate 276. Both inputs of AND gate 276 are connected to the top count output COUNTN of prescaler 49.
• gate 274 will pro ⁇ vide a logic high output to OR gate 278 only when pre ⁇ scaler 49 is not in a top count condition, the output of AND gate 268 is low, and SBUS1N is low. This last con- 1 dition results in prescaler 49 being used to provide a clock input for primary counter 54.
• OR. gate 278 is connected to the - output of an AND gate 280 having three inverting inputs. A first input thereof is grounded. A second input is connected to the inverted output of driver 260. The third input is connected to SBUS1. ° The output of OR gate 278 is connected to one input of each of OR gates 282 and 284. A second input of each of OR gates 282 and 284 is connected to the output of an
• OR gate 286 One input of OR gate 286 is driven by a 5
• TTL to ECL receiver which receives a TTL clock pulse
• CPTTL of a frequency under 50 MHz, along a line of con ⁇ trol bus 50.
• the third inputs of OR gates 282 and 284 are connected to the CPBIT output of decoder 248 (FIG. 8).
• gates 282 and 284 are connected to the inputs of respective drivers 290 and 292, which gen- 5 erate, respectively clock signals CPCl and CPC2 used by primary counter 54 (FIG. 5).
• Gates 282 and 284 permit a selection of one clock 5 from the group consisting of the clock provided as above, CPTTL or CPBIT. 1
• the top count TCNT of primary counter 54 may be used.
• TCNT is provided to the 10 input of a nulti- 5 plexer 294.
• the II input is connected to CPCl.
• the select input SI of multiplexer 294 is connected to SBUS 2.
• SBUS2 When SBUS2 is low, TCNT appears at the output of multiplexer 294.
• SBUS2 is high, the output of ° prescaler 49 or the 100 MHz clock signal appears at the output of multiplexer 294, the selection being made as previously described.
• the non-inverted output of multi ⁇ plexer 294 is converted to an output cell or driver 296. 5 T,he output of driver 296 is available externally of ap ⁇ paratus 20 as an ECL nominal clock output CPOUT 1.
• the inverted output of multiplexer 294 is provided to one input of OR gate 298.
• the second input of OR gate 298 is grounded.
• the output of OR gate 298 clocks a flip flop 300.
• the QN output of flip flop 300 is con ⁇ nected to the D input thereof.
• Flip flop 300 is reset by RESET 8.
• the Q output of flip flop 300 is connected to a ° first input of OR gate 302. The second input thereof is grounded.
• the inverted output of OR gate 302 is sup ⁇ plied to an output cell or driver 304 which provides an
• ECL symmetric clock output CP0UT2 externally of appara- 5 tus 20.
• the QN output of flip flop 300 is connected to a first input of an OR gate 306. The second input thereof is grounded.
• the output of OR gate 306 drives a TTL output cell 308 which provides TTL symmetric clock out ⁇ put CPOUT 3 externally of apparatus 20.
• Control bus 50 has an additional two lines LOAD 1 and LOAD 2 which are used to supply signals directing the preloading of counter 54.
• LOAD 1 is a TTL signal supplied to a TTL to ECL receiver 310.
• the output of receiver 310 is supplied to one input of an OR gate 312.
• OR gate 312 The other input of OR gate 312 is grounded.
• the invert- ing output of OR gate 312 is supplied to an input of a gate 314 which serves as an AND gate with inverting in ⁇ puts and an inverted output.
• LOAD 2 is an ECL signal which is connected to the input of an ECL comparator 316.'
• the output of compara ⁇ tor 316 is connected to the input of a driver 318.
• the inverted output of driver 318 is connected to another 5 input of gate 314.
• the remaining inputs of gate 314 are grounded.
• the inverted output of gate 314 is connected to a first input of NAND gate 320.
• a second input of NAND ° gate 320 is connected to SBUS7N. The third input there ⁇ of is grounded.
• the output of NAND gate 320 is connect ⁇ ed to a first input of OR gate 322.
• OR gate 322 is connected to the output of NAND gate 324. 5
• NAND gate 324 Two inputs of NAND gate 324 are grounded, while the third is connected to SBUSON.
• the inverted output EXLD of OR gate 322 is used to cause primary counter 54 to preload data from input data buffer 44 on load bus 55. i- This occurs when SBUSON is at logic low, or when one of LOAD 1 or LOAD 2 and SBUS7N are at logic low.
• apparatus 20 nay be pro ⁇ grammed by appropriate lcgic signals from a microcom- 0 puter to provide time base signals, to serve as a coun ⁇ ter, or to directly address memory . Further, count and address data from apparatus 20 may readily be acquired by the microcomputer. ⁇ 5 Referring to Fig. 10, three modules 20A, 20B and
• a 100 MHz clock is provided to module 20A to provide an appropriate time base, when 0 module 20A is programmed by a microcomputer.
• the tine base output of module 20A is connected to a first input of a gate 328.
• a second input of gate 328 is connected to the output of a conventional selector 330 of the type generally used in a counter/ imer.
• a first input of se ⁇ lector 330 is connected to the output of a comparator 332A which is fed by a driver 334A.
• a second input of 0 comparator 332A is connected to a first reference volt ⁇ age VREF1. Conparator 332A should have some hysteresis.
• a signal representative of a first event is applied to an input CHA of a microcomputer programmable atten- 5 uator 336A.
• the output of attenuator 336A is connected to the input of driver 334A.
• the arrangement and opera- tion of comparator 332A, driver 334A and attenuator 336A, are well known in the art.
• a comparator 332B, a driver 334B and an attenuator 336B provide another channel for an input CHB.
• Compara ⁇ tor 332B is provided with a reference voltage VREF2.
• the output of comparator 332B is connected to selector 330.
• the output of gate 328 is connected to a module 20B constructed according to the invention, which serves as a count accumulator for counts gated through gate 328.
• a second module 20C is provided to count the top count output of nodule 20B.
• Count data from modules 20B and 20C is provided to the microcomputer.
• modules 20B and 20C are both used, a counter/tiner with a 32 bit accunulator is produced.
• FIG. 11 illustrates how three modules 20D, 20E and 20F of the present invention can be utilized to provide a nicroconputer controlled arbitrary function generator 338.
• a stable frequency source such as a 100 MHz clock is connected to the input of module 20D which is pro ⁇ grammed by the microconputer to act as a time base gen- erator.
• the tining output of nodule 20D is supplied to nodule 20E which is configured as a burst counter and programmed to provide a signal to module 20D when the required predeternined nunber of repetitions of the ar- bitrary function have been generated.
• the output of nodule 20D is also supplied to module 20F which is pro- granmed as a nenory address control.
• Module 20F con ⁇ trols a stinulus nenory 340 loaded with computer sup ⁇ plied stinulus data for making up the arbitrary func- tion.
• Base address 342 has a bit which is used to provide a unique indication that base address 342 has been ac ⁇ Stepd. For exanple, this bit nay be of logic value "1" while the corresponding bits in other addresses in stin ⁇ ulus * nenory 3 0 are a logic zero. When this logic one bit is detected, a synchronization signal indicating the start of the arbitrary function is produced by a buffer 344.
• Module 20F steps through the locations in stinulus nenory 340 providing the data in each location sequen ⁇ tially to a digital to analog converter 346 upon successive ⁇ sive pulses of the tine base generator (nodule 20D) to the nenory address control (nodule 20F).
• the output of digital to analog converter 346 is supplied to a buffer 348 which has sufficient output drive capability to pro ⁇ vide a signal to be used for test or other purposes.
• nodule 20E When the function produced by the data in stimulus nem- ory 340 has been repeated the nunber of tines programmed into the burst counter (nodule 20E) , operation ceases until a nicroconputer reset has occurred and a new trig ⁇ ger signal is received by nodule 20F.
• FIG. 12 illustrates the manner in which three nod ⁇ ules according to the present invention nay be intercon- nected to provide a digitizer 350 for storing a digital representation of an analog signal.
• a clock preferably of 100 MHz, is provided to the input of a first module 20G configured as a tine base generator.
• the time base output CPOUT thereof is supplied to a second nodule 20H used as a memory address control.
• CPOUT is also sup ⁇ plied to a third nodule 201 which serves as a sanples to go counter.
• An input signal to be digitized is provided to an input terninal having a standard 50 ohm terminating re ⁇ sistor 352, connected therefrom to ground.
• a program- nable attenuator 354 adjusts the level of the signal so that it is suitable as an input for a buffer 356.
• a sample and hold circuit 358 sanples the output of buffer 3 and periodically holds the value thereof for conver ⁇ sion by an analog to digital converter 360.
• the output of analog to digital converter 360 is provided as a dig ⁇ ital input to a circular nenory file 362.
• a synchronization pulse is provided as an input to a buffer 364.
• the output thereof is provided to a driv ⁇ er 366 having hysteresis so as to prevent undesirable nultiple triggering.
• the output of driver 366 is pro- vided to the nenory address control (nodule 20H) and the samples to go counter (nodule 201) .
• Module 20H is programmed by the nicrocomputer so that the count bus 60 thereof has data thereon, from prinary counter 54, corresponding to the address in nen ⁇ ory 362 being accessed by nodule 20H.
• this value is stored in pointer latch 62 and provides a reference corresponding to a location in memory 362.
• the samples to go counter (nodule 201) is programmed by the nicroconputer to count a predetermined nunber of tine base signals fron nodule 20G, corresponding to a like nunber of locations in memory 362.
• nodule 201 provides an end of count EOC pulse to nodule 201!, preventing ad- 15 ditional locations in memory 362 fron being addressed, and therefor holding the data desired in digital for in menory 362.
• r_ Q It will be understood that the value programmed into the sanples to go counter (module 201) by the nicroconputer can be used to provide storage of the analog signal being digitized for a period of time
• circular nenory 362 is constantly updated with new data written over the oldest data therein, at a rate determined by the tine base provided to nodule 20H by
• An additional module (not shown) according to the invention may be used to provide a time delay, after the occurrence of a synchronization pulse, before the exter-
• nal trigger and count enable signals are supplied to nodules 20H and 201, respectively.
• a digital word generator 368 is constructed using a tine base generator module 20J and a memory address control module 20K according to the invention.
• the output of a stable oscillator, prefer ⁇ ably of 100 MHz, is provided to nodule 20J.
• nodule 20K is used to address a stinulus nenory 370, a response nenory 372, a tristate control memory 374 and an expected response nemory 376.
• Stimulus nemory 370 may be an N bit by M bit mem ⁇ ory, where N is the nunber of bits or outputs presented at any given tine, and K is the number of different out ⁇ puts to be presented.
• the data in one of the M locations of nenory 370 is provided to an N bit driver 378 and placed on a bidirec ⁇ tional tristate data bus 380 when an appropriate enable signal is received fron tristate control nenory 374.
• Data bus 380 provides the data thereon to a unit under test (not shown) .
• the output of receiver 386 provides the returning data to response nemory 372 which is under the control of nodule 20K.
• a digital conparator 388 com ⁇ pares the data being provided to response memory 372 with data from the corresponding address location in expected response nenory 376. If the response fron the unit under test does not correspond to the expected re- sponse, comparator 388 provides an output which nay be used, for exanple, to stop the test.
• Conparator 388 nay also be configured with appropriate circuitry for indi- eating that one of the bits of data returned from the unit under test is neither logic high or logic low, but is at a level sonewhere between.

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• 1987
  • 1987-05-04 WO PCT/US1987/001038 patent/WO1987007054A1/en not_active Application Discontinuation
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